WO2019153102A1 - 垂直式晶片与水平式晶片的嵌入型封装结构及其制造方法 - Google Patents

垂直式晶片与水平式晶片的嵌入型封装结构及其制造方法 Download PDF

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WO2019153102A1
WO2019153102A1 PCT/CN2018/000068 CN2018000068W WO2019153102A1 WO 2019153102 A1 WO2019153102 A1 WO 2019153102A1 CN 2018000068 W CN2018000068 W CN 2018000068W WO 2019153102 A1 WO2019153102 A1 WO 2019153102A1
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Prior art keywords
wafer
substrate
blind holes
blind
circuit layer
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PCT/CN2018/000068
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English (en)
French (fr)
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璩泽明
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璩泽明
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Application filed by 璩泽明 filed Critical 璩泽明
Priority to PCT/CN2018/000068 priority Critical patent/WO2019153102A1/zh
Publication of WO2019153102A1 publication Critical patent/WO2019153102A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

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  • the invention relates to a package structure of a wafer and a manufacturing method thereof, in particular to an embedded package structure in which a vertical wafer or a horizontal wafer is embedded and soldered in a blind hole of a substrate to effectively reduce the thickness of the package structure and Its manufacturing method.
  • the existing chip packaging technology is generally to use a surface adhesion technology (SMT) or other electrical connection methods such as wire bond technology to solder and fix a wafer on a substrate (core board, or carrier substrate, such as printing) a circuit board) on a surface of each predetermined line to complete a chip package structure such as a common flip-chip package structure, but is not limited; in application, the chip package structure is correspondingly soldered and fixed in a The subsequent mounting process of the chip package structure is completed at a predetermined position on the surface of the motherboard (such as a printed circuit board).
  • SMT surface adhesion technology
  • other electrical connection methods such as wire bond technology
  • the wafer can be divided into a vertical wafer and a horizontal wafer, and a vertical wafer has at least two crystal pads (such as P/N pole) and Divided on a first surface and an opposite second surface of the wafer, such as a power chip, a light emitting diode (LED) chip (such as a red LED), etc., but not limited thereto; a horizontal wafer has at least two crystal pads and The same is provided on a surface of the wafer as the second surface of the present invention, but is not limited.
  • a vertical wafer has at least two crystal pads (such as P/N pole) and Divided on a first surface and an opposite second surface of the wafer, such as a power chip, a light emitting diode (LED) chip (such as a red LED), etc., but not limited thereto;
  • a horizontal wafer has at least two crystal pads and The same is provided on a surface of the wafer as the second surface of the present invention, but is not limited.
  • each of the crystal pads provided on one surface (such as the first surface) is electrically connected to the other surface (such as the first
  • the surface mount technology (SMT) is used for the subsequent flip-chip packaging operation; and the package position is different according to the position of the contacts of the preset lines on the surface of the substrate.
  • the structure can be further divided into a fan-in type (Fan-In) or a fan-out type (Fan-Out) package structure.
  • the thickness of a chip package structure substantially includes the thickness of the wafer and the thickness of the substrate, and the thickness of the vertical chip package structure is generally greater than
  • the thickness of the horizontal chip package structure is difficult to effectively reduce due to the thickness of the chip package structure, and it has been unable to meet the current requirements of lightness, thinness, and shortness.
  • An embedded type package structure for a vertical wafer characterized by comprising:
  • a substrate having a first surface and an opposite second surface, wherein a first circuit layer is disposed on the second surface, and at least one first blind hole is drilled on the first surface of the substrate and at least a second blind hole, wherein each of the first blind holes and each of the second blind holes are respectively connected to the first circuit layer by the first surface passing through the thickness of the substrate;
  • each vertical wafer has at least two crystal pads, wherein at least one crystal pad is disposed on a first surface of each vertical wafer, and the other at least one crystal pad is disposed on the opposite second surface, each The vertical wafer is embedded in each of the corresponding first blind holes, and each of the crystal pads disposed on the second surface can be electrically connected to the first circuit layer of the substrate by the conductive material;
  • An insulating layer is disposed on the first surface of the substrate, and at least one third blind hole and at least one fourth blind hole are bored on the insulating layer; wherein each third blind hole passes through the insulating layer The thickness is connected to the first surface of the vertical wafer; wherein each of the fourth blind holes penetrates the thickness of the insulating layer and is correspondingly connected to each of the second blind holes provided on the substrate, so that each of the fourth blind holes corresponds to the corresponding Each of the second blind holes can form an integral blind hole that communicates up and down;
  • a second circuit layer which is formed on the surface of the insulating layer by using an electroplating technique, and the third blind via, each of the fourth blind vias and the inner wall surface of each of the second blind vias, so as to be disposed on the vertical wafer
  • Each of the crystal pads on the first surface can be electrically connected to the first circuit layer by the second circuit layer.
  • the embedded type package structure of the vertical type wafer wherein the insulating layer further fills a gap left by each vertical type wafer embedded in each of the first blind holes.
  • the embedded type package structure of the vertical wafer further comprising an outer cover layer overlying the second circuit layer and filling each of the third blind holes, each of the fourth blind holes, and each The second blind hole.
  • the embedded type package structure of the vertical wafer wherein a depth of the first blind via of the substrate is equal to a thickness of the vertical wafer.
  • a method of manufacturing an embedded package structure for a vertical wafer comprising the steps of:
  • Step S1 providing a substrate having a first surface and an opposite second surface, wherein the second surface is provided with a first circuit layer, and at least one first blind is formed on the first surface of the substrate a hole and at least one second blind hole, wherein each of the first blind holes and each of the second blind holes are respectively connected to the first circuit layer by the first surface of the substrate passing through the thickness of the substrate;
  • Step S2 providing at least one vertical wafer, each vertical wafer is provided with at least two crystal pads, wherein at least one crystal pad is disposed on a first surface of each vertical wafer, and at least one other crystal pad is disposed on each vertical wafer On a second surface opposite;
  • Step S3 embedding each of the vertical wafers in each of the corresponding first blind holes, and electrically connecting each of the crystal pads provided on the second surface of each vertical wafer to the substrate by means of a conductive material a circuit layer
  • Step S4 coating an insulating layer on the first surface of the substrate
  • Step S5 drilling at least one third blind hole and at least one fourth blind hole on the insulating layer, wherein each third blind hole is respectively connected to the first surface of each vertical wafer through the thickness of the insulating layer
  • Each of the crystal pads is provided, wherein each of the fourth blind holes can penetrate the thickness of the insulating layer at the same time during the drilling and correspondingly communicate with the second blind holes provided on the substrate, so that the fourth blind holes can be Corresponding second blind holes form an integrated blind hole that communicates up and down;
  • Step S6 forming a second circuit layer on the surface of the insulating layer and the inner walls of each of the third blind holes, the fourth blind holes, and the second blind holes by using an electroplating technique, so as to be disposed in the vertical type
  • Each of the crystal pads on the first surface of the wafer can be electrically connected to the first circuit layer disposed on the second surface of the substrate by the second circuit layer.
  • the manufacturing method of the embedded type package structure of the vertical wafer further comprising a step S7: providing an outer sheath layer, the outer sheath layer is overlaid on the second circuit layer and filling each third blind a hole, each of the fourth blind holes and each of the second blind holes.
  • An embedded type package structure for a horizontal wafer characterized by comprising:
  • a substrate having a first surface and an opposite second surface, wherein a first circuit layer is disposed on the second surface, and at least one first blind hole is bored on the first surface of the substrate, wherein each The first blind holes are respectively connected to the first circuit layer by the first surface passing through the thickness of the substrate;
  • At least one horizontal wafer having at least two crystal pads, the at least two crystal pads being disposed on a first surface of the vertical wafer, wherein each horizontal wafer is embedded in each corresponding first blind hole, and Each of the crystal pads disposed on the second surface can be electrically connected to the first circuit layer of the substrate separately by the conductive material;
  • An insulating layer is disposed on the first surface of the substrate and fills a space left by each horizontal wafer embedded in each of the first blind holes.
  • a method of manufacturing an embedded package structure for a horizontal wafer comprising the steps of:
  • Step S1 providing a substrate having a first surface and an opposite second surface, wherein the second surface is provided with a first circuit layer, and at least one first is drilled on the first surface of the substrate a blind hole, wherein each of the first blind holes respectively passes through the thickness of the substrate to communicate with the first circuit layer;
  • Step S2 providing at least one horizontal wafer, each horizontal wafer is provided with at least two crystal pads and separately disposed on the second surface of the horizontal wafer;
  • Step S3 embedding each horizontal wafer in each of the corresponding first blind holes, and electrically connecting each of the crystal pads disposed on the second surface to the first circuit of the substrate by means of a conductive material On the floor
  • Step S4 providing an insulating layer, the insulating layer is disposed on the first surface of the substrate and filling the gap left by each horizontal wafer embedded in each of the first blind holes.
  • the main advantage of the present invention is that the embedded package structure of a horizontal wafer is completed in such a manner that the thickness is greatly reduced, the process is relatively simplified, and the reliability of the conduction is improved.
  • FIG. 1 is a cross-sectional view showing the process of an embodiment of an embedded package structure for a vertical wafer of the present invention.
  • FIG. 2 is a cross-sectional view of the embedded package structure of FIG. 1.
  • 3 to 7 are schematic views showing the manufacturing process of the embedded package structure shown in FIG. 2, respectively.
  • Figure 8 is a cross-sectional view showing the process of an embodiment of the embedded package structure of the horizontal wafer of the present invention.
  • Figure 9 is a cross-sectional view showing the embedded package structure shown in Figure 8.
  • 10 to 12 are schematic views showing the manufacturing process of the embedded package structure shown in FIG. 9, respectively.
  • the present embodiment is an embedded type package structure 1 for a vertical wafer, comprising: a substrate 10 , at least one vertical wafer 20 , an insulating layer 30 , a second circuit layer 40 , or An outer cover layer 50, wherein the package structure 1 utilizes a substrate 10 having a large area to simultaneously fabricate a sheet-like parent body 2 having a plurality of package structures 1 (child bodies) (as shown in FIG. 1), and then The sheet-like precursor 2 is cut to form a plurality of package structures 1 (child bodies), but is not intended to limit the invention.
  • the substrate 10 has a first surface 11 and an opposite second surface 12, and a first circuit layer 13 is formed on the second surface 12.
  • at least one first blind hole 14 and at least one second blind hole 15 are bored on the first surface 11 of the substrate 10, and the first embodiment is a first blind as shown in FIG. 1 to FIG.
  • the aperture 14 and a second blind aperture 15 are illustrated by way of example and not limitation.
  • Each of the first blind holes 14 and the second blind holes 15 respectively pass through the thickness of the substrate 10 and communicate with the inner surface of the first circuit layer 13 , wherein the depth of each of the first blind holes 14 is designed to be approximately Equal to the thickness of the vertical wafer 20.
  • each of the first blind holes 14 and each of the second blind holes 15 pass through the thickness of the substrate 10 and communicate with the inner surface of the first circuit layer 13, the mechanical drilling technique does not easily control the blind hole depth and is thus easily injured.
  • the first circuit layer 13 the present embodiment is preferably formed by using a laser drilling technique to form the blind holes 14, 15.
  • the substrate 10 can further adopt a conventional two-layer circuit board, that is, the substrate 10 is provided with a copper foil layer 13a on the first surface 11 and the second surface 12, wherein the copper foil layer 13a is disposed on the second surface 12. That is, the first circuit layer 13 is formed, wherein the copper foil layer 13a disposed on the first surface 11 can have a thin thickness for utilizing a laser drilling technique to directly penetrate the thin copper foil.
  • Each of the first blind holes 14 and each of the second blind holes 15 is bored by the layer 13a.
  • Each of the vertical wafers 20 has at least two crystal pads 21 such as a crystal pad 21a, 21b including positive and negative electrodes, wherein the at least two pads 21 are formed on a first surface 22 of each wafer 20 and an opposite second.
  • a crystal pad 21a, 21b including positive and negative electrodes On the surface 23, for example, at least one pad 21a is disposed on a first surface 22 of each of the wafers 20, and the remaining at least one pad 21b is disposed on a second surface 23 of each of the wafers 20, but is not limited, that is, generally formed.
  • the vertical pad 20 is embedded in the corresponding first blind holes 14 of the substrate 10, since the depth of each of the first blind holes 14 is designed to be approximately equal to the vertical type.
  • the thickness of the wafer 20 is such that at least one of the pads 21a disposed on the first surface 22 of each of the vertical wafers 20 can be exposed just at the opening of the first blind via 14.
  • the at least one pad 21b on the second surface 22 of the vertical wafer 20 is formed by electrically connecting to the inner surface of the first circuit layer 13 of the substrate 10 by a conductive material 24 such as solder ball or silver paste. On state.
  • the insulating layer 30 is disposed on the first surface 11 of the substrate 10, and the insulating layer 30 can further fill the gap left when the vertical wafers 20 are embedded in the first blind holes 14 as shown in FIG. 5. As shown in the figure, the vertical wafers 20 can be firmly positioned, and the problem that the thermal expansion is likely to occur during use in the presence of air bubbles when unfilled is avoided can be avoided.
  • a laser drilling technique is further applied to the insulating layer 30 to form at least a third blind via 31 and at least a fourth blind via 32.
  • Each of the third blind vias 31 communicates with the at least one pad 21a on the first surface 21 of the vertical wafer 20 through the thickness of the insulating layer 30, but each of the third blind vias 31 is preferably capable of laser drilling.
  • each of the fourth blind holes 32 can be simultaneously penetrated and correspondingly connected to the second blind holes 15 provided on the substrate 10 during the laser drilling, so that the fourth blind holes 32 can correspond to the corresponding ones.
  • the second blind hole 15 forms an integral blind hole 32, 15 that communicates up and down. Since the drilling depths of the first, second and third blind holes 14, 15, 31 must be precisely controlled, it is preferred that the present invention utilizes a laser drilling technique to make the blind holes 14, 15 optimal. In addition, the total blind depths of the integrated blind holes 32, 15 formed by the fourth blind holes 32 and the corresponding second blind holes 15 are relatively deep, and it is difficult to form the integrated blind by a laser drilling operation.
  • the holes 32, 15, so the present invention is formed by the second laser drilling operation, first forming the second blind holes 15, and then forming and forming the fourth blind holes 32 while communicating and communicating to the corresponding second blind holes.
  • the fourth blind holes 32 and the corresponding second blind holes 15 form an integral blind hole 32, 15 that communicates up and down, thereby improving the efficiency of the drilling operation.
  • the second circuit layer 40 is formed on the surface of the insulating layer 30 and the third blind holes 31, the fourth blind holes 32, and the inner wall surfaces of the corresponding second blind holes 15 by using an electroplating technique.
  • At least one pad 21a on the first surface 22 of each of the vertical wafers 20 can be electrically connected to the first circuit layer 13 by the second circuit layer 40, so that the vertical wafer 20 is vertically divided
  • Each of the at least one pad 21a, 21b on the first and second surfaces 22, 23 can be electrically connected to the first circuit layer 13 and form a solder joint, respectively. Therefore, when the package structure 1 of the present invention is as shown by arrow A in FIG. The direction is downwardly mounted on an external motherboard such as a printed circuit board (not shown), and the solder joints formed on the first circuit layer 13 can be kept flat, which is favorable for subsequent mounting processes such as surface adhesion.
  • Technology Surface Mount Technology
  • the embedded package structure 1 of the present embodiment may further be provided with an outer cover 50 which is laid flat on the second circuit layer 40 and fills each third blind hole 31, each The four blind vias 32 and the interconnected second blind vias 15 protect the second circuit layer 40 and the package structure 1 formed.
  • the manufacturing method of the embedded package structure 1 of the vertical wafer 20 of the present embodiment includes the following steps:
  • Step S1 Referring to FIG. 3, a substrate 10 having a first surface 11 and an opposite second surface 12 is disposed.
  • the second surface 12 is provided with a first circuit layer 13 at the first of the substrate 10.
  • At least one first blind hole 14 and at least one second blind hole 15 are drilled into the surface 11 , wherein each of the first blind holes 14 and each of the second blind holes 15 respectively pass through the thickness of the substrate 10 by the first surface 11 It is connected to the inner surface of the first circuit layer 13.
  • Step S2 Referring to FIG. 4, at least one vertical wafer 20 is provided.
  • Each vertical wafer 20 is provided with at least two crystal pads 21, wherein at least one crystal pad 21a is disposed on a first surface 22 of the wafer 20, at least one of which A crystal pad 21b is provided on the opposite second surface 23 of the wafer 20.
  • Step S3 Referring to FIG. 4, each of the vertical wafers 20 is respectively embedded in each of the first blind vias 14 of the substrate 10, and at least one of the crystal pads 21b disposed on the second surface 22 of each of the vertical wafers 20 is provided.
  • the first circuit layer 13 of the substrate 10 can be electrically connected by the conductive material 24.
  • Step S4 Referring to FIG. 5, an insulating layer 30 is disposed on the first surface 11 of the substrate 10, wherein the insulating layer 30 further fills the remaining vertical wafers 20 embedded in the first blind vias 14 Void.
  • Step S5 Referring to FIG. 6, at least one third blind hole 31 and at least one fourth blind hole 32 are drilled into the insulating layer 30, wherein each of the third blind holes 31 is respectively connected to the thickness of the insulating layer 30 to be connected to Corresponding to each of the crystal pads 21a of the first surface 21 of each of the vertical wafers 20, wherein each of the fourth blind holes 32 can further penetrate the thickness of the insulating layer 30 and be connected to the corresponding layer during laser drilling.
  • Each of the second blind holes 15 on the substrate 10 enables the fourth blind holes 32 to form an integral blind hole 32, 15 that communicates with the corresponding second blind holes 15.
  • Step S6 Referring to FIG. 7, a second circuit layer 40 is formed on the surface of the insulating layer 30 and the third blind holes 31, the fourth blind holes 32, and the inner wall surfaces of the second blind holes 15 so that a second circuit layer 40 is formed.
  • Each of the crystal pads 21a disposed on the first surface 22 of each of the vertical wafers 20 can be electrically connected to the first circuit layer 13 disposed on the second surface 12 of the substrate 10 by the second circuit layer 40. This completes a package structure 1.
  • a step S7 may be further included.
  • an outer sheath 50 is disposed on the second circuit layer 40 and fills the third blind holes 31 and the first layer.
  • the four blind vias 32 and each of the second blind vias 15 protect the second circuit layer 40.
  • the embodiment is a horizontal type embedded package structure 1a, which mainly comprises: a substrate 10, at least one horizontal wafer 20a, and an insulating layer 30a, wherein the package structure 1a A sheet-shaped parent body 2a having a plurality of package structures 1 (child bodies) is formed in synchronization with a substrate 10 having a relatively large area (as shown in FIG. 8), and the sheet-shaped parent body 2a is cut to form a plurality of sheets.
  • the package structure 1a (child body) is not limited.
  • the substrate 10 has a first surface 11 and an opposite second surface 12, wherein the second surface 12 is formed with a first circuit layer 13.
  • at least one first blind hole 14 is formed on the first surface 11 of the substrate 10 by using a laser drilling technique. As shown in FIG. 8 to FIG. 12, a first blind hole 14 is taken as an example. Description but not limited.
  • Each of the first blind holes 14 is communicated to the inner surface of the first circuit layer 13 by the first surface 11 through the thickness of the substrate 10, wherein the depth of each of the first blind holes 14 is designed to be approximately equal to the horizontal wafer 20 thickness.
  • Each horizontal wafer 20a has at least two crystal pads 21 such as crystal pads 21a, 21b including positive and negative electrodes, but is not limited, and is disposed on the second surface 23 of each horizontal wafer 20; each horizontal wafer 20a is embedded therein In each of the corresponding first blind holes 14 of the substrate 10, the depth of each of the first blind holes 14 is designed to be approximately equal to the thickness of each horizontal wafer 20a.
  • the at least two pads 21 (21a, 21b) provided on the second surface 22 of each horizontal wafer 20a are respectively electrically connected to the substrate 10 by means of a conductive material 24 such as solder balls or silver paste, but are not limited.
  • a circuit layer 13 forms a positive and negative conduction state.
  • the manufacturing method of the embedded package structure 1a of the horizontal wafer 20a of the present embodiment includes the following steps:
  • Step S1 Referring to FIG. 10, a substrate 10 is provided having a first surface 11 and an opposite second surface 12, wherein the second surface 12 is provided with a first circuit layer 13 (but including at least two separate circuits) And forming at least one first blind via 14 on the first surface 11 of the substrate 10, wherein each of the first blind vias 14 respectively communicates to the first circuit layer 13 through the thickness of the substrate 10.
  • Step S2 Referring to FIG. 11, at least one horizontal wafer 20a is provided. Each of the horizontal wafers 20a is provided with at least two crystal pads 21 and is separately provided on the second surface 12 of the horizontal wafer 20a.
  • Step S3 Referring to FIG. 11, each horizontal wafer 20a is embedded in each of the corresponding first blind holes 14, and each of the crystal pads 21 provided on the second surface 12 is electrically separated by a conductive material. Bonding (soldering) to at least two separate circuits in the first circuit layer 13 of the substrate 10.
  • Step S4 Referring to FIG. 12, an insulating layer 30a is disposed on the first surface 11 of the substrate 10 and filled with the horizontal wafers 20a embedded in the first blind holes 14 The gap is completed to complete the embedded package structure 1a of a horizontal wafer 20a.
  • the embedded package structure 1, 1a of the vertical wafer 20 or the horizontal wafer 20a of the present invention has at least the following advantages over the background art of the prior art:
  • Each vertical wafer 20 or horizontal wafer 20a is embedded in each of the corresponding first blind holes 14 of the substrate 10, and the depth of each of the first blind holes 14 is designed to be approximately equal to the vertical wafer 20 or Since the thickness of the horizontal wafer 20a is such that the thickness of the package structures 1, 1a can be reduced.
  • the vertical wafer 20 of the present invention is an integrated blind hole 32, 15 which is embedded in the substrate 10 (printed circuit board) and which is formed by each of the fourth blind holes 32 and the corresponding second blind holes 15. It is formed on the external substrate 10 around the vertical wafer 20. Therefore, the package structure 1 of the present invention forms a fan-out type (FOiP, Fan-Out in) in which the vertical wafer 20 is embedded in the substrate 10 (printed circuit board).
  • the PCB) package structure type achieves the advantages of greatly reduced thickness and relatively simplified process, which cannot be achieved by the prior art.
  • each of the blind holes 14, the second blind holes 15, the third blind holes 31, the fourth blind holes 32, and the respective fourth blind holes 32 and the corresponding second blind holes 15 of the present invention are formed by laser drilling technology, so that the process of blind holes in the package structure 1 can be simplified.
  • the second circuit layer 40 is formed on the surface of the insulating layer 30 by using an electroplating technique, and the third blind via 31, each of the fourth blind vias 32, and the corresponding inner wall surface of each of the second blind vias 15 Up, it can effectively improve the conductivity reliability.

Abstract

一种垂直式晶片（20）与水平式晶片（20a）的嵌入型封装结构（1）及其制造方法，其包含：一基板（10），其具有一第一面（11）及相对的一第二面（12），在该第二面（12）上设有一第一电路层（13），在该第一面（11）上钻孔成型至少一第一盲孔（14）或至少一第二盲孔（15），且各盲孔（14/15）分别穿过该基板（10）厚度而连通至该第一电路层（13）；至少一晶片（20），其包含垂直式晶片（20）或水平式晶片（20a）；其中各晶片（20）分别嵌入设在相对应的各第一盲孔（14）内，并使第二表面（12）上所设的各晶垫（21）能凭借导电材（24）以连结至该基板（10）的第一电路层（13）；之后再设一第二电路层（40），使设在该垂直式晶片（20）的第一表面（11）上的至少一晶垫（21）能凭借该第二电路层（40）以电性连结至该第一电路层（13）；如此完成一嵌入型封装结构（1），达成厚度大幅减少、制程相对简化、导电信赖度提升的优点。

Description

垂直式晶片与水平式晶片的嵌入型封装结构及其制造方法 技术领域
本发明涉及一种晶片的封装结构及其制造方法，尤指一种将垂直式晶片或水平式晶片嵌入并焊结设在一基板的盲孔内以有效降低封装结构厚度的嵌入型封装结构及其制造方法。
背景技术
在晶片封装结构技术领域中，目前已存在多种背景技术如：US8,211,722、US6,914,268、US8,049,230、US7,985,979、US7,939,832、US7,713,353、US7,642,121、US7,462,861、US7,393,411、US7,335,519、US7,294,866、US7,087,526、US5,557,115、US6,514,782、US6,497,944、US6,791,119、US2011/0014734、US2002/0163302、US2004/0113156等。现有晶片封装技术大抵是利用表面粘着技术(SMT)或其他电性连结方式如导线连结(wire bond)技术将一晶片焊结并固定在一基板(core board，或称载板substrate，如印刷电路板)表面上各预设线路的接点上以完成一晶片封装结构如常见的覆晶式(flip-chip)封装结构但不限制；在应用时该晶片封装结构再对应焊结并固定在一主板(如印刷电路板)表面的预设位置上，如此完成该晶片封装结构之后续安装制程。
另以晶片上各晶垫(如P/N极)的设置型态而言，晶片可分为垂直式晶片及水平式晶片，一垂直式晶片具有至少二晶垫(如P/N极)且分开设在该晶片的一第一表面及相对的第二表面上如电源(power)晶片、发光二极管(LED)晶片(如红LED)等但不限制；一水平式晶片具有至少二晶垫且同设在该晶片的一表面上如本发明所指的第二表面但不限制。此外，以一垂直式晶片的覆晶式封装结构而言，一般是将设在其中一表面(如第一表面)上的各晶垫先电性连结至与设在其中另一表面(如第二表面)上的各晶垫同位于同一平面上，再利用表面粘着技术(SMT)来进行后续的覆晶式封装作业；而随着基板表面上各预设线路的接点位置的不同，一封装结构进一步又可分成扇内型(Fan-In)或扇出型(Fan-Out)封装结构。
在现有晶片封装结构中，由于晶片是焊结并固定于基板的表面上，故一晶 片封装结构的厚度基本上包含晶片的厚度及基板的厚度，而且垂直式晶片封装结构的厚度一般又大于水平式晶片封装结构的厚度，因晶片封装结构的厚度难以有效降低，已无法满足目前轻、薄、短小的要求。
发明内容
由上可知，对一晶片封装结构而言，如何有效减少封装厚度或简化封装结构或其制程，且又能适用于垂直式晶片或水平式晶片，仍存有改进的需要，本发明即针对上述需要而提出解决方案。
为实现上述目的，本发明采用的技术方案是：
一种垂直式晶片的嵌入型封装结构，其特征是包含：
一基板，其具有一第一面及相对的一第二面，其中在该第二面上设有一第一电路层，在该基板的第一面上钻孔成型至少一第一盲孔及至少一第二盲孔，其中各第一盲孔及各第二盲孔分别由该第一面穿过该基板厚度而连通至该第一电路层；
至少一垂直式晶片，各垂直式晶片具有至少二晶垫，其中至少一晶垫设在各垂直式晶片的一第一表面上，而其他至少一晶垫设在相对的第二表面上，各垂直式晶片嵌入于所对应的各第一盲孔内，并使设在第二表面上的各晶垫能凭借导电材以电性连结至该基板的第一电路层；
一绝缘层，其覆设在该基板的第一面上，且在该绝缘层上钻孔成型至少一第三盲孔及至少一第四盲孔；其中各第三盲孔穿过该绝缘层厚度而连通至该垂直式晶片的第一表面；其中各第四盲孔贯穿该绝缘层厚度并对应连通至设在该基板上的各第二盲孔，使各第四盲孔与所对应的各第二盲孔能形成一上下连通的一体式盲孔；
一第二电路层，其利用电镀技术以成型在该绝缘层的表面上以及各第三盲孔、各第四盲孔与各第二盲孔的内壁面上，使设在该垂直式晶片的第一表面上的各晶垫能凭借该第二电路层以电性连结至该第一电路层。
所述的垂直式晶片的嵌入型封装结构，其中：该绝缘层进一步填满各垂直式晶片嵌入在各第一盲孔中所留下的空隙。
所述的垂直式晶片的嵌入型封装结构，其中：还包含一外护层，该外护层覆设在该第二电路层上并填满各第三盲孔、各第四盲孔及各第二盲孔。
所述的垂直式晶片的嵌入型封装结构，其中：该基板的第一盲孔的深度等 于该垂直式晶片的厚度。
一种垂直式晶片的嵌入型封装结构的制造方法，其特征是包含下列步骤：
步骤S1：提供一基板，其具有一第一面及相对的一第二面，在该第二面上设有一第一电路层，在该基板的第一面上钻孔成型至少一第一盲孔及至少一第二盲孔，其中各第一盲孔及各第二盲孔分别由该基板的第一面穿过该基板厚度而连通至该第一电路层；
步骤S2：提供至少一垂直式晶片，各垂直式晶片设有至少二晶垫，其中至少一晶垫设在各垂直式晶片的一第一表面上，其他至少一晶垫设在各垂直式晶片的相对的一第二表面上；
步骤S3：将各垂直式晶片分别嵌入于所对应的各第一盲孔内，并使设在各垂直式晶片的第二表面上的各晶垫凭借导电材以电性连结至该基板的第一电路层；
步骤S4：在该基板的第一面上覆设一绝缘层；
步骤S5：在该绝缘层上钻孔成型至少一第三盲孔及至少一第四盲孔，其中各第三盲孔分别穿过该绝缘层厚度而连通至各垂直式晶片的第一表面上所设的各晶垫，其中各第四盲孔系在钻孔成型时能同时贯穿该绝缘层厚度并对应连通至设在该基板上的各第二盲孔，使各第四盲孔能与所对应的各第二盲孔形成一上下连通的一体式盲孔；
步骤S6：利用电镀技术以在该绝缘层的表面上及各第三盲孔、各第四盲孔及各第二盲孔的内壁面上成型一第二电路层，以使设在该垂直式晶片的第一表面上的各晶垫能凭借该第二电路层以电性连结至设在该基板的第二面上的该第一电路层。
所述的垂直式晶片的嵌入型封装结构的制造方法，其中：还包含一步骤S7：设一外护层，使该外护层覆设在该第二电路层上并填满各第三盲孔、各第四盲孔及各第二盲孔。
一种水平式晶片的嵌入型封装结构，其特征是包含：
一基板，其具有一第一面及相对的一第二面，在该第二面上设有一第一电路层，在该基板的第一面上钻孔成型至少一第一盲孔，其中各第一盲孔分别由该第一面穿过该基板厚度而连通至该第一电路层；
至少一水平式晶片，其具有至少二晶垫，该至少二晶垫分开设在该垂直式晶片的一第一表面上，其中各水平式晶片嵌入于所对应的各第一盲孔内，并使 设在第二表面上的各晶垫能分别凭借导电材以分开地电性连结至该基板的第一电路层；
一绝缘层，其覆设在该基板的第一面上并填满各水平式晶片嵌入在各第一盲孔中所留下的空隙。
一种水平式晶片的嵌入型封装结构的制造方法，其特征是包含下列步骤：
步骤S1：提供一基板，其具有一第一面及相对的一第二面，其中该第二面上设有一第一电路层，并在该基板的第一面上钻孔成型至少一第一盲孔，其中各第一盲孔分别穿过该基板厚度而连通至该第一电路层；
步骤S2：提供至少一水平式晶片，各水平式晶片设有至少二晶垫且分开地设在该水平式晶片的第二表面上；
步骤S3：将各水平式晶片分别嵌入于相对应的各第一盲孔内，并使设在第二表面上的各晶垫分别凭借导电材以分开地电性连结至该基板的第一电路层上；
步骤S4：设一绝缘层，使该绝缘层覆设在该基板的第一面上并填满各水平式晶片嵌入在各第一盲孔中所留下的空隙。
本发明主要优点在于：如此完成一水平式晶片的嵌入型封装结构，使得厚度大幅减少、制程相对简化及获得导电信赖度提升。
附图说明
图1是本发明垂直式晶片的嵌入型封装结构一实施例的制程中剖视示意图。
图2是图1所示嵌入型封装结构的剖视示意图。
图3至图7分别是图2所示嵌入型封装结构的制造流程示意图。
图8是本发明水平式晶片的嵌入型封装结构一实施例的制程中剖视示意图。
图9是图8所示嵌入型封装结构的剖视示意图。
图10至图12分别是图9所示嵌入型封装结构的制造流程示意图。
附图标记说明：1-封装结构；1a-封装结构；2-片状母体；2a-片状母体；10-基板；11-第一面；12-第二面；13-第一电路层；13a-铜箔层；14-第一盲孔；15-第二盲孔；20-垂直式晶片；20a-水平式晶片；21-晶垫；21a-晶垫；21b-晶垫；22-第一表面；23-第二表面；30-绝缘层；30a-绝缘层；31-第三盲孔；32-第四盲孔；40-第二电路层；50-外护层。
具体实施方式
为使本发明更加明确详实，兹列举较佳实施例并配合下列图示，将本发明的结构及其技术特征详述如后，其中各图示只用以说明本发明的结构关系及相关功能，因此各部尺寸或形状或大小并非依实际比例设置且非用以限制本发明：
参考图1至图7，本实施例系一种垂直式晶片的嵌入型封装结构1，其包含：一基板10、至少一垂直式晶片20、一绝缘层30、一第二电路层40、或一外护层50，其中该封装结构1利用一具较大面积的基板10以同步制作完成一具有多个封装结构1(子体)的片状母体2(如图1所示)，再对该片状母体2进行切割以形成多个封装结构1(子体)，但非用以限制本发明。
该基板10具有一第一面11及相对的一第二面12，其中该第二面12上成型设有一第一电路层13。本实施例系在该基板10的第一面11上钻孔成型至少一第一盲孔14及至少一第二盲孔15，如图1至图7所示本实施例系以一第一盲孔14及一第二盲孔15为例说明但不限制。各第一盲孔14及各第二盲孔15分别由该第一面11穿过该基板10厚度并连通至该第一电路层13的内面，其中各第一盲孔14的深度设计成约等于该垂直式晶片20的厚度。此外，由于各第一盲孔14及各第二盲孔15穿过该基板10厚度并连通至该第一电路层13的内面，但机械钻孔技术不容易精密控制盲孔深度且因而容易伤及该第一电路层13，故本实施例以利用雷射钻孔技术来制作各盲孔14、15为最佳。
该基板10进一步可采用现有的双层电路板，即该基板10在第一面11及第二面12上各设有一铜箔层13a，其中设在第二面12上的铜箔层13a即用以制作形成该第一电路层13，其中设在该第一面11上的铜箔层13a可具有较薄的厚度，供可利用雷射钻孔技术以直接贯穿该较薄的铜箔层13a而钻孔成型各第一盲孔14及各第二盲孔15。
各垂直式晶片20具有至少二晶垫21如包含正负电极的晶垫21a、21b但不限制，其中该至少二晶垫21分开设在各晶片20的一第一表面22及相对的第二表面23上，如至少一晶垫21a设在各晶片20的一第一表面22上，而其余的至少一晶垫21b设在各晶片20的一第二表面23上但不限制，即形成一般通称垂直式晶片的晶垫型态；各垂直式晶片20嵌入在该基板10的相对应的各第一盲孔14内，由于各第一盲孔14的深度系被设计成约等于该垂直式晶片20的厚度，故设在各垂直式晶片20的第一表面22上的至少一晶垫21a能恰好外露在该第一盲孔14的孔口处。该垂直式晶片20的第二表面22上的至少一晶垫21b凭借 导电材24如锡球或银胶等但不限制，以电性连结至该基板10的第一电路层13的内面而形成导通状态。
该绝缘层30覆设在该基板10的第一面11上，并使该绝缘层30能进一步填满各垂直式晶片20嵌入在各第一盲孔14中时所留下的空隙如图5所示，以使各垂直式晶片20能牢固定位，并可避免未填满而有气泡存在时在使用中容易发生热膨胀而爆裂的问题。在该绝缘层30上再利用雷射钻孔技术以成型至少一第三盲孔31及至少一第四盲孔32。各第三盲孔31穿过该绝缘层30厚度而连通至该垂直式晶片20的第一表面21上的至少一晶垫21a，但各第三盲孔31在雷射钻孔时最好能有效控制以避免伤及该垂直式晶片20。此外，各第四盲孔32进一步在雷射钻孔成型时能同时贯穿并对应连通至设在该基板10上的各第二盲孔15，使各第四盲孔32能与所对应的各第二盲孔15形成一个上下连通的一体式盲孔32，15。由于各第一、二、三盲孔14、15、31的钻孔深度须精密控制，故本发明以利用雷射钻孔技术来制作各盲孔14、15为最佳。此外由各第四盲孔32与相对应的各第二盲孔15所形成一体式盲孔32，15的总深度相对较深，恐难以凭借一次雷射钻孔作业就成型出该一体式盲孔32，15，因此本发明乃凭借二次雷射钻孔作业，先成型各第二盲孔15，再于成型各第四盲孔32的同时贯穿并连通至相对应的各第二盲孔15，以使各第四盲孔32与各对应的第二盲孔15形成一上下连通的一体式盲孔32，15，如此可提升钻孔作业的效率。
该第二电路层40利用电镀技术以成型在该绝缘层30的表面上及各第三盲孔31、各第四盲孔32与各对应的第二盲孔15的内壁面上，使设在各垂直式晶片20的第一表面22上的至少一晶垫21a能凭借该第二电路层40以电性连结至该第一电路层13，如此使该垂直式晶片20分设在垂直上下的第一、二表面22、23上的各至少一晶垫21a、21b都能电性连结至该第一电路层13并分别形成一焊点，因此当本发明的封装结构1如图2中箭头A方向所示要向下安装在外部一主板如印刷电路板(图未示)，在该第一电路层13上所分别形成的各焊点能保持平整，有利于进行后续的安装制程如表面黏着技术(Surface Mount Technology，SMT)。
此外，本实施例的嵌入型封装结构1进一步可设一外护层50，该外护层50系平整地覆设在该第二电路层40上并填满各第三盲孔31、各第四盲孔32及各连通的第二盲孔15，以保护该第二电路层40及所形成的封装结构1。
本实施例的垂直式晶片20的嵌入型封装结构1的制造方法，包含下列步骤：
步骤S1：参考图3，提供一基板10，其具有一第一面11及相对的一第二面12，在该第二面12上设有一第一电路层13，在该基板10的第一面11上钻孔成型至少一第一盲孔14及至少一第二盲孔15，其中各第一盲孔14及各第二盲孔15分别由该第一面11穿过该基板10厚度而连通至该第一电路层13的内面。
步骤S2：参考图4，提供至少一垂直式晶片20，各垂直式晶片20设有至少二晶垫21，其中至少一晶垫21a设在该晶片20的一第一表面22上，其中至少一晶垫21b设在该晶片20的相对的一第二表面23上。
步骤S3：参考图4，将各垂直式晶片20分别对应嵌入于该基板10的各第一盲孔14内，并使各垂直式晶片20的第二表面22上所设的至少一晶垫21b能凭借导电材24以电性连结至该基板10的第一电路层13。
步骤S4：参考图5，在该基板10的第一面11上覆设一绝缘层30，其中该绝缘层30进一步填满各垂直式晶片20嵌入在各第一盲孔14中所留下的空隙。
步骤S5：参考图6，在该绝缘层30上钻孔成型至少一第三盲孔31及至少一第四盲孔32，其中各第三盲孔31分别穿过该绝缘层30厚度而连通至所对应的各垂直式晶片20的第一表面21所设的各晶垫21a，其中各第四盲孔32进一步在雷射钻孔成型时能同时贯穿该绝缘层30厚度并对应连通至设在该基板10上的各第二盲孔15，使各第四盲孔32能与所对应的各第二盲孔15形成一上下连通的一体式盲孔32、15。
步骤S6：参考图7，在该绝缘层30的表面上及各第三盲孔31、各第四盲孔32与各第二盲孔15的内壁面上制作成型一第二电路层40，使设在各垂直式晶片20的第一表面22上的各晶垫21a能凭借该第二电路层40以电性连结至设在该基板10的第二面12上的该第一电路层13，如此完成一封装结构1。
此外，进一步可包含一步骤S7：参考图2，设一外护层50，使该外护层50平整地覆设在该第二电路层40上并填满各第三盲孔31、各第四盲孔32及各第二盲孔15以保护该第二电路层40。
再参考图8至图12，本实施例系一种水平式晶片的嵌入型封装结构1a，其主要包含：一基板10，至少一水平式晶片20a、及一绝缘层30a，其中该封装结构1a利用一具较大面积的基板10以同步制作完成一具有多个封装结构1(子体)的片状母体2a(如图8所示)，再对该片状母体2a进行切割以形成多个封装结构1a(子体)但不限制。
该基板10具有一第一面11及相对的一第二面12，其中该第二面12上成型 设有一第一电路层13。本实施例利用雷射钻孔技术以在该基板10的第一面11上成型至少一第一盲孔14，如图8至图12所示本实施例系以一第一盲孔14为例说明但不限制。各第一盲孔14分别由该第一面11穿过该基板10厚度而连通至该第一电路层13的内面，其中各第一盲孔14的深度设计成约等于该水平式晶片20的厚度。
各水平式晶片20a具有至少二晶垫21如包含正负电极的晶垫21a、21b但不限制，且分开设在各水平式晶片20的第二表面23上；各水平式晶片20a嵌入在该基板10的相对应的各第一盲孔14内，其中各第一盲孔14的深度系被设计成约等于各水平式晶片20a的厚度。各水平式晶片20a的第二表面22上所设的至少二晶垫21(21a、21b)分别凭借导电材24如锡球或银胶但不限制，以分开电性连结至该基板10的第一电路层13而形成正负极分开导通状态。
本实施例的水平式晶片20a的嵌入型封装结构1a的制造方法，包含下列步骤：
步骤S1：参考图10，提供一基板10，其具有一第一面11及相对的一第二面12，其中该第二面12上设有一第一电路层13(但包含至少二分开的电路)，并在该基板10的第一面11上钻孔成型至少一第一盲孔14，其中各第一盲孔14分别穿过该基板10厚度而连通至该第一电路层13。
步骤S2：参考图11，提供至少一水平式晶片20a，各水平式晶片20a设有至少二晶垫21且分开地设在该水平式晶片20a的第二表面12上。
步骤S3：参考图11，将各水平式晶片20a分别嵌入于相对应的各第一盲孔14内，并使设在第二表面12上的各晶垫21分别凭借导电材以分开地电性连结(焊结)至该基板10的第一电路层13中至少二分开的电路上。
步骤S4：参考图12，设一绝缘层30a，使该绝缘层30a覆设在该基板10的第一面11上并填满各水平式晶片20a嵌入在各第一盲孔14中所留下的空隙，而完成一水平式晶片20a的嵌入型封装结构1a。
本发明的垂直式晶片20或水平式晶片20a的嵌入型封装结构1、1a，与本领域的背景技术相比，至少有下列优点：
(1)各垂直式晶片20或水平式晶片20a嵌入在该基板10的相对应的各第一盲孔14内，且各第一盲孔14的深度被设计成约等于该垂直式晶片20或水平式晶片20a的厚度，故确实能减少该封装结构1、1a的厚度。
(2)本发明的垂直式晶片20是嵌入在基板10(印刷电路板)内，且由各 第四盲孔32与所对应的各第二盲孔15所形成的一体式盲孔32、15是成型在该垂直式晶片20周围的外部的基板10上，因此本发明的封装结构1系形成一垂直式晶片20嵌入基板10(印刷电路板)内的扇出型(FOiP，Fan-Out in PCB)封装结构型态，如此达成厚度大幅减少、制程相对简化的优点，此乃现有技术无法达成的。
(3)本发明的各一盲孔14、各第二盲孔15、第三盲孔31、各第四盲孔32、以及由各第四盲孔32与相对应的各第二盲孔15所形成的一体式盲孔32、15，都利用雷射钻孔技术来形成，故能简化该封装结构1中各盲孔的制程。
(4)该第二电路层40利用电镀技术以成型设在该绝缘层30的表面上及该第三盲孔31、各第四盲孔32与所对应的各第二盲孔15的内壁面上，故能有效提升导电信赖度。
以上说明对本发明而言只是说明性的，而非限制性的，本领域普通技术人员理解，在不脱离权利要求所限定的精神和范围的情况下，可作出许多修改、变化或等效，但都将落入本发明的保护范围之内。

Claims (8)

  1. 一种垂直式晶片的嵌入型封装结构，其特征是包含：
    一基板，其具有一第一面及相对的一第二面，其中在该第二面上设有一第一电路层，在该基板的第一面上钻孔成型至少一第一盲孔及至少一第二盲孔，其中各第一盲孔及各第二盲孔分别由该第一面穿过该基板厚度而连通至该第一电路层；
    至少一垂直式晶片，各垂直式晶片具有至少二晶垫，其中至少一晶垫设在各垂直式晶片的一第一表面上，而其他至少一晶垫设在相对的第二表面上，各垂直式晶片嵌入于所对应的各第一盲孔内，并使设在第二表面上的各晶垫能凭借导电材以电性连结至该基板的第一电路层；
    一绝缘层，其覆设在该基板的第一面上，且在该绝缘层上钻孔成型至少一第三盲孔及至少一第四盲孔；其中各第三盲孔穿过该绝缘层厚度而连通至该垂直式晶片的第一表面；其中各第四盲孔贯穿该绝缘层厚度并对应连通至设在该基板上的各第二盲孔，使各第四盲孔与所对应的各第二盲孔能形成一上下连通的一体式盲孔；
    一第二电路层，其利用电镀技术以成型在该绝缘层的表面上以及各第三盲孔、各第四盲孔与各第二盲孔的内壁面上，使设在该垂直式晶片的第一表面上的各晶垫能凭借该第二电路层以电性连结至该第一电路层。
  2. 如权利要求1所述的垂直式晶片的嵌入型封装结构，其特征在于：该绝缘层进一步填满各垂直式晶片嵌入在各第一盲孔中所留下的空隙。
  3. 如权利要求1所述的垂直式晶片的嵌入型封装结构，其特征在于：还包含一外护层，该外护层覆设在该第二电路层上并填满各第三盲孔、各第四盲孔及各第二盲孔。
  4. 如权利要求1所述的垂直式晶片的嵌入型封装结构，其特征在于：该基板的第一盲孔的深度等于该垂直式晶片的厚度。
  5. 一种垂直式晶片的嵌入型封装结构的制造方法，其特征是包含下列步骤：
    步骤S1：提供一基板，其具有一第一面及相对的一第二面，在该第二面上设有一第一电路层，在该基板的第一面上钻孔成型至少一第一盲孔及至少一第二盲孔，其中各第一盲孔及各第二盲孔分别由该基板的第一面穿过该基板厚度而连通至该第一电路层；
    步骤S2：提供至少一垂直式晶片，各垂直式晶片设有至少二晶垫，其中至少一晶垫设在各垂直式晶片的一第一表面上，其他至少一晶垫设在各垂直式晶片的相对的一第二表面上；
    步骤S3：将各垂直式晶片分别嵌入于所对应的各第一盲孔内，并使设在各垂直式晶片的第二表面上的各晶垫凭借导电材以电性连结至该基板的第一电路层；
    步骤S4：在该基板的第一面上覆设一绝缘层；
    步骤S5：在该绝缘层上钻孔成型至少一第三盲孔及至少一第四盲孔，其中各第三盲孔分别穿过该绝缘层厚度而连通至各垂直式晶片的第一表面上所设的各晶垫，其中各第四盲孔系在钻孔成型时能同时贯穿该绝缘层厚度并对应连通至设在该基板上的各第二盲孔，使各第四盲孔能与所对应的各第二盲孔形成一上下连通的一体式盲孔；
    步骤S6：利用电镀技术以在该绝缘层的表面上及各第三盲孔、各第四盲孔及各第二盲孔的内壁面上成型一第二电路层，以使设在该垂直式晶片的第一表面上的各晶垫能凭借该第二电路层以电性连结至设在该基板的第二面上的该第一电路层。
  6. 如权利要求5所述的垂直式晶片的嵌入型封装结构的制造方法，其特征在于：还包含一步骤S7：设一外护层，使该外护层覆设在该第二电路层上并填满各第三盲孔、各第四盲孔及各第二盲孔。
  7. 一种水平式晶片的嵌入型封装结构，其特征是包含：
    一基板，其具有一第一面及相对的一第二面，在该第二面上设有一第一电路层，在该基板的第一面上钻孔成型至少一第一盲孔，其中各第一盲孔分别由该第一面穿过该基板厚度而连通至该第一电路层；
    至少一水平式晶片，其具有至少二晶垫，该至少二晶垫分开设在该垂直式晶片的一第一表面上，其中各水平式晶片嵌入于所对应的各第一盲孔内，并使设在第二表面上的各晶垫能分别凭借导电材以分开地电性连结至该基板的第一电路层；
    一绝缘层，其覆设在该基板的第一面上并填满各水平式晶片嵌入在各第一盲孔中所留下的空隙。
  8. 一种水平式晶片的嵌入型封装结构的制造方法，其特征是包含下列步骤：
    步骤S1：提供一基板，其具有一第一面及相对的一第二面，其中该第二面 上设有一第一电路层，并在该基板的第一面上钻孔成型至少一第一盲孔，其中各第一盲孔分别穿过该基板厚度而连通至该第一电路层；
    步骤S2：提供至少一水平式晶片，各水平式晶片设有至少二晶垫且分开地设在该水平式晶片的第二表面上；
    步骤S3：将各水平式晶片分别嵌入于相对应的各第一盲孔内，并使设在第二表面上的各晶垫分别凭借导电材以分开地电性连结至该基板的第一电路层上；
    步骤S4：设一绝缘层，使该绝缘层覆设在该基板的第一面上并填满各水平式晶片嵌入在各第一盲孔中所留下的空隙。
PCT/CN2018/000068 2018-02-07 2018-02-07 垂直式晶片与水平式晶片的嵌入型封装结构及其制造方法 WO2019153102A1 (zh)

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CN102456636A (zh) * 2010-10-19 2012-05-16 矽品精密工业股份有限公司 嵌入式芯片的封装件及其制造方法
CN105870092A (zh) * 2015-02-10 2016-08-17 台达电子国际（新加坡）私人有限公司 封装结构
US20170170123A1 (en) * 2015-12-11 2017-06-15 J-Devices Corporation Semiconductor package and its manufacturing method
CN206312887U (zh) * 2016-12-06 2017-07-07 苏州源戍微电子科技有限公司 带有封闭空腔的芯片嵌入式封装结构

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CN102456636A (zh) * 2010-10-19 2012-05-16 矽品精密工业股份有限公司 嵌入式芯片的封装件及其制造方法
CN105870092A (zh) * 2015-02-10 2016-08-17 台达电子国际（新加坡）私人有限公司 封装结构
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