TW202234602A - 半導體封裝件及其製造方法 - Google Patents

半導體封裝件及其製造方法 Download PDF

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TW202234602A
TW202234602A TW111117898A TW111117898A TW202234602A TW 202234602 A TW202234602 A TW 202234602A TW 111117898 A TW111117898 A TW 111117898A TW 111117898 A TW111117898 A TW 111117898A TW 202234602 A TW202234602 A TW 202234602A
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wiring
hole
terminal
semiconductor
semiconductor package
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TW111117898A
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TWI834165B (zh
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林直毅
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日商安靠科技日本公司
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Abstract

在此提供一種接合方法，係於半導體裝置之晶片之雙面所形成之電極與配線之間建構高程度熱可靠性之接合。半導體封裝件之製造方法包含以下步驟。以夾住接合膜之方式將半導體晶片接合於第一基板上。於半導體晶片上形成第一絕緣膜。於第一絕緣膜形成第一通孔。以經由第一通孔而電性連接於半導體晶片之方式於第一絕緣膜上形成第一配線。於接合膜形成第二通孔。以經由第二通孔而電性連接於半導體晶片之方式於半導體晶片之下形成第二配線。

Description

半導體封裝件及其製造方法
本發明為有關於一種半導體封裝件，例如為關於安裝有電力用半導體裝置之半導體封裝件及其製造方法。
電力用半導體裝置為以電力之變換與控制做為基本功能之半導體裝置。不僅應用於家電或辦公室自動化（Office Automation，OA）機器中所使用之逆變器（inverter）或小型馬達，亦可擔任發電廠之電力系統、電車或汽車等之中用以支配馬達驅動系統等之電力變換或控制之重要的角色。舉例而言，可列舉具有pn接合二極體構造或蕭特基能障（Schottky barrier）二極體構造之整流二極體、MOSFET（Metal Oxide Semiconductor Field Effect Transistor）等之電力用電晶體、晶體閘流管（thyristor）等做為電力用半導體裝置之代表。通常的電力用半導體裝置如日本國際專利公開案第2012-164817號公報、日本專利公開案第H9-74193號公報或日本專利公開案第2001-352009號公報所揭示，以做為上下具有一個或其以上之電極（端子）之半導體晶片（以下稱之為晶片）進行供給，於晶片之上表面及下表面之雙方建構配線，且通過配線而電性連接於外部電源或其他裝置。
本發明之實施型態之一種半導體封裝件包含半導體晶片、第一絕緣膜、第一配線、接合膜及第二配線。第一絕緣膜具有第一通孔，且半導體晶片埋入第一絕緣膜。第一配線位於半導體晶片上，且通過第一通孔而電性連接於半導體晶片。接合膜具有第二通孔，且位於半導體晶片之下。第二配線位於接合膜之下，且通過第二通孔而電性連接於半導體晶片。第一絕緣膜所含有之材料與接合膜所含有之材料相異。
半導體晶片亦可具有第一端子及第二端子分別位於半導體晶片之下及之上，且半導體晶片亦可分別通過第一端子及第二端子而電性連接於第二配線及第一配線。
半導體封裝件亦可更包含第三配線，第一絕緣膜內亦可具有第三通孔，第三配線位於第一絕緣膜之下，且通過第三通孔而電性連接於第一配線。第一配線及第三配線亦可於第三通孔中連接。第二配線及第三配線亦可存在於同一層內。
第一通孔之尺寸、第二通孔之尺寸及第三通孔之尺寸亦可彼此相異。接合膜亦可更具有多個通孔。
接合膜亦可含有絕緣材料。
半導體封裝件亦可更包含基板，位於第一配線上。
本發明之實施型態之一種半導體封裝件之製造方法，包含以下步驟。以夾住接合膜之方式將半導體晶片接合於第一基板上。於半導體晶片上形成第一絕緣膜。於第一絕緣膜形成第一通孔。以通過第一通孔而電性連接於半導體晶片之方式於第一絕緣膜上形成第一配線。於接合膜形成第二通孔。以通過第二通孔而電性連接於半導體晶片之方式於半導體晶片之下形成第二配線。
製造方法中，半導體晶片亦可具有第一端子及第二端子分別位於半導體晶片之下及之上，第一配線及第二配線亦可以分別通過第二端子及第一端子而電性連接於半導體晶片之方式形成。
製造方法中，亦可更包含於形成第一通孔同時於第一絕緣膜形成第三通孔。第一配線亦可以嵌設於第三通孔之方式形成。亦可更包含以電性連接於第一配線之方式於形成第二配線同時於第三通孔之下形成第三配線。
於上述製造方法中，第一通孔之尺寸、第二通孔之尺寸及第三通孔之尺寸亦可彼此相異。第二通孔亦可以貫通第一基板之方式形成。第二通孔亦可以於接合膜具有多個通孔之方式形成。
於製造方法中，接合膜亦可含有絕緣材料。第一絕緣膜所含有之材料亦可與接合膜所含有之材料相異。
於上述製造方法中，第一基板亦可包含開口部及貫通開口部之配線，以通過第三通孔而電性連接於配線之方式形成第一配線。
以下，針對本發明之半導體封裝件將參照圖式進行說明。然而，本發明能夠於不脫離要旨之範圍中以各種態樣實施，而並非解釋成限定於以下所例示之實施型態之記載內容。
此外，為了更明確地說明，相較於實際的態樣，圖式中針對各個部分之幅寬、厚度、形狀等雖有以模式之方式表達之情形，但僅為一範例，而並非用以限定本發明之解釋。而且，於本說明書及各個圖式中，與關於已出現之圖而已說明之元件具備相同功能元件，將標註相同符號，且將省略重覆之說明。
於本發明中，對於某一特定膜體進行加工且形成多個膜體之場合中，此些多個膜體能夠具有相異之功能及所扮演之角色。然而，此些多個膜體可來自於利用同一工程而形成為同一層之膜體。因此，此些多個膜體定義為存在於同一層。
針對相異於由以下所記載之各個實施型態之態樣所帶來之作用效果之其他作用效果，自本說明書之記載可明確得知之內容，或者相關業者中可易於預測之內容，亦可當然理解為由本發明所帶來之內容。
以下將說明第一實施型態。
本實施型態中，使用圖1A說明關於本發明之一實施型態之半導體封裝件之構造。
半導體封裝件包含半導體晶片120。半導體晶片120於晶片雙面之至少一者形成有端子（引出電極）。圖1A中，描繪半導體晶片120具有第一端子122及二個第二端子124、126之範例。
半導體封裝件中，於半導體晶片120上具有第一絕緣膜130，且以埋入有半導體晶片120及第二端子124、126之方式形成。第一絕緣膜130保護半導體晶片120，且對於半導體封裝件賦予物理性強度，藉此具有令半導體封裝件自身之處理變得容易之功能。
第一絕緣膜130具有通孔（via）（開口部）。具體而言，第一絕緣膜130於與第二端子124、126重疊之區域上具有第一通孔142、144。更甚者，第一絕緣膜130於半導體晶片120之附近且不與半導體晶片120重疊之區域具有第三通孔146及148。第一通孔142、144分別到達第二端子124、126，而第三通孔146、148則貫通第一絕緣膜130。
半導體封裝件於第一絕緣膜130上具有第一配線152及154。第一配線152設置成埋入第一通孔142及第三通孔146，另一方面，第一配線154設置成埋入第一通孔144及第三通孔148。第一配線152、154之一部分接觸於第一絕緣膜130之上表面。第一配線152、154分別通過第二端子124、126而電性連接於半導體晶片120。如後所述，第一配線152或154能夠使用電解電鍍法或導電性金屬膠體（以下為金屬膠體）等材料而形成。
如圖1A所示，半導體封裝件中，亦可經由第二絕緣膜135而於第一配線152、154上更具有基板（第二基板）105。第二絕緣膜135具有令第二基板105黏著於第一配線152、154之功能。第二基板105具有保護半導體晶片120之同時對於半導體封裝件賦予物理性強度之功能。另外，如後所述，第二基板105具有於形成第二配線170或第三配線172、174時做為支撐基板之功能。因此，關於本實施型態之半導體封裝件中第二絕緣膜135或第二基板105不一定為必須的，考量半導體封裝件之物理性強度或處理難易度，亦可不設置第二絕緣膜135或第二基板105。
半導體封裝件中，於半導體晶片120之下具有接合膜110，接合膜110具有至少一個第二通孔160。而且，於半導體晶片120及接合膜110之下以埋入第二通孔160之方式設置第二配線170。第二配線170通過第一端子122而電性連接於半導體晶片120。如後所述，第一配線152或154能夠使用電解電鍍法或金屬膠體等材料而形成。
接合膜110之材料亦可相異於第一絕緣膜130之材料。換言之，接合膜110所含有之材料及第一絕緣膜130所含有之材料亦可彼此相異。因此，圍繞第一通孔142、144之材料亦可相異於圍繞第二通孔160之材料。
半導體封裝件於第三通孔146、148之下更可具有第三配線172、174。第一通孔142、144、第二通孔160及第三通孔146、148之尺寸（截面積）亦可彼此相異。舉例而言，第三通孔146、148亦可為最大，第二通孔160亦可為最小。或者，第一通孔142、144亦可為最小。
第三配線172電性連接於第一配線152，第三配線174電性連接於第一配線154。而且，第二配線170及第三配線172、174雖為彼此物理性地不連接而相互分離，但亦可存在於同一層。如後所述，第二配線170或第三配線172、174能夠使用電解電鍍法或金屬膠體等材料而形成。
半導體封裝件於第二配線170、第三配線172、174之下亦可更具有阻劑層（resist layer）180。阻劑層180具有保護第二配線170、第三配線172、174之端部之功能，而且例如於焊料能夠選擇性地接觸於第二配線170、第三配線172、174之時，阻劑層180亦可與焊料具有低的親和性。
根據關於本實施型態之半導體封裝件，能夠將配線建構於晶片雙面所設之端子，且能夠藉由使用此些配線而自晶片之單側方向對於晶片雙面所設之端子提供電性訊號。而且，能夠將相同之配線形成方法（例如電解電鍍法）適用於晶片雙面之端子。
通常而言，於安裝雙面具有端子之晶片之場合中，可藉由電解電鍍法於晶片上表面之端子形成配線。另一方面，會使用高熔點焊料、燒結金屬（例如燒結銀等）或如導電性晶粒附著膜層（Die Attach Film，DAF）之導電性膜層，或者利用因接觸金屬間之擴散而形成之連接（金屬擴散接合），而將晶片下表面之端子接合於印刷配線基板等所設有之配線導電墊。換言之，晶片之上表面及下表面之配線形成方法相異。因此，必須要備有於上表面端子形成配線時卻不使用之裝置，例如晶片連結裝置等，如此會導致處理流程之複雜化及製造成本之增加。而且，使用高熔點焊料、燒結金屬或導電性膜層之接合方式或者藉由金屬擴散接合之接合方式，對於熱的可靠度相對較低，而容易發生接合面之剝離，且容易於接合面或其附近產生空隙。
對此，本發明之實施型態之一種半導體封裝件中，如後所述，因能夠對於晶片雙面之端子使用相同手法建構配線，故能夠於雙面端子上使用相同工程及相同製造裝置而形成配線。因此，能夠簡化製造處理流程，且能夠降低製造成本。而且，因能夠使用相同於晶片雙面之端子之材料（例如銅）而形成配線，故能夠達成具有高程度之熱可靠性之接合。
以下將說明第二實施型態。
於本實施型態中，將使用圖1B說明關於本發明之一實施型態之半導體封裝件之構造。本實施型態之半導體封裝件中，相較於第一實施型態之相異點在於第二通孔160之構造相異。以下將省略與第一實施型態同樣之構造所相關之記述內容。
如圖1B所示，本實施型態之半導體封裝件中，接合膜110設有單一個通孔（第二通孔160）。而且以埋入此通孔160之方式形成第二配線170。藉由採用此構造，能夠擴大第一端子122與第二配線170之接觸區域，而能夠大幅降低接觸阻抗。而且還能夠促進來自晶片之熱能逸散。
以下將說明第三實施型態。
於本實施型態中，將使用圖1C說明關於本發明之實施型態之半導體封裝件之構造。本實施型態之半導體封裝件中，相較於第一、第二實施型態之相異點在於第三通孔146、148之構造相異。以下將省略與第一、第二實施型態同樣之構造所相關之記述內容。
如圖1C所示，本實施型態之半導體封裝件中，第三通孔146、148具有多種直徑。換言之，第三通孔146、148具有二個以上開口面積相異之區域。因此，第一配線152、154及第三配線172、174於第三通孔146、148內連接。具有如此形狀之第三通孔146、148之製作方法，能夠藉由例如以不貫通第一絕緣膜130之方式自第一絕緣膜130之上表面形成開口部，之後自第一絕緣膜130之下表面形成更大之開口部。藉由採用此構造，能夠更有效率地以電解電鍍法將材料埋入各個通孔中，而且能夠大幅降低於通孔形成時發生於通孔內之污損（smear）。
以下將說明第四實施型態。
於本實施型態中，將使用圖2說明關於本發明之實施型態之半導體封裝件之構造。本實施型態之半導體封裝件中，相較於第一至第三實施型態之相異點在於具有多個半導體晶片120。而且，相較於第一至第三實施型態之相異點還可在於能夠於晶片之上下建構配線。以下將省略與第一至第三實施型態同樣之構造所相關之記述內容。
如圖2所示，本實施型態之半導體封裝件具有二個半導體晶片120。其中，半導體晶片120之數量並非限定於二個，亦可具有三個以上之半導體晶片120。半導體封裝件中，更具有設置於第一絕緣膜130及半導體晶片120之第二端子124、126上之第一配線152、154、156，二個半導體晶片120藉由第一配線154而相互電性連接。
第二配線170分別經由具有第二通孔160之接合膜110而分別設置於二個半導體晶片120之下。而且，以覆蓋第一配線152、154、156及第二配線170之端部之方式形成阻劑層180。而且，半導體封裝件中不一定必須於半導體封裝件雙面皆具有阻劑層180，亦可例如僅於半導體封裝件之下表面具有阻劑層180。
第一配線152、154、156及第二配線170以相同方法形成，例如可使用電解電鍍法或金屬膠體法而形成。因此，能夠於簡化處理流程及降低成本之情況下製造含有多個半導體晶片之半導體封裝件。而且，能夠賦予更高程度之熱可靠性。本實施型態之半導體封裝件中，第一配線152、154、156具有做為於晶片上表面露出之電極之功能。另一方面，第二配線170具有做為於晶片下表面露出之電極之功能。因此，能夠堆疊半導體封裝件，進而能夠製造高密度之晶片安裝基板。
以下將說明第五實施型態。
於本實施型態中，關於本發明之實施型態之半導體封裝之製作方法，將使用圖3A至圖3E、圖4A至圖4D及圖5說明圖1A所示之半導體封裝件之製作方法。
使用接合膜110將半導體晶片120接合於第一基板100上。第一基板能夠使用由金屬或玻璃、陶瓷、樹脂等材料所形成之基板。樹脂亦可例如為將玻璃纖維等材料混合於環氧系樹脂之基板。或者，亦可使用預先形成有配線之印刷基板等。或者亦可使用以銅等之金屬薄膜夾住絕緣薄膜之膜層且此膜層設置於表面之基板。
接合膜110具有令半導體晶片120黏著於第一基板100之功能即可。因此，能夠使用以環氧樹脂或聚醯亞胺（polyimide）、聚矽氧烷（polysiloxane）等之有機材料做為代表之絕緣材料等材料。亦能夠例如使用絕緣性之DAF做為絕緣材料。然而，因如後所述將於製作流程中剝離第一基板100，故較佳為使用能夠以物理性或化學性剝離第一基板100之接合膜110。舉例而言，亦可使用藉由光照射而降低黏著性之黏著劑做為接合膜110。
半導體晶片120為利用半導體特性之裝置即可，此半導體特性可含有矽或鎵（gallium）、碳化矽（silicon carbide）、氮化鎵（gallium nitride）等之半導體。舉例而言，可列舉有整流二極體或電晶體等，亦可為用以供大電壓大電流驅動之電力用電晶體或晶體閘流管等之電力用半導體裝置。半導體晶片120於晶片雙面之至少一者形成有端子（引出電極）。圖3A中，描繪具有第一端子122及二個第二端子124、126之範例。
以埋入有半導體晶片120及第二端子124、126之方式形成第一絕緣膜130（圖3B）。第一絕緣膜130能夠使用環氧系樹脂或聚醯亞胺系樹脂，且能夠藉由噴墨（ink jet）法或印刷法、旋塗（spin coating）法、浸塗（dip coating）法等之濕式製膜法而形成。或者，亦可於半導體晶片120上配置絕緣性膜層，且藉由層壓（laminate）加工等加熱壓接方式而形成第一絕緣膜130。第一絕緣膜130之材料亦可相異於接合膜110之材料。換句話說，第一絕緣膜130所含有之材料及接合膜110所含有之材料亦可彼此相異。因此，圍繞第一通孔142、144之材料亦可相異於圍繞第二通孔160之材料。
之後，如圖3C所示，於第一絕緣膜130之與第二端子124、126重疊之區域形成第一通孔142、144，以露出第二端子124、126。同時於第一絕緣膜130形成到達第一基板100之第三通孔146、148。第三通孔146、148之尺寸能夠大於第一通孔142、144之尺寸，藉此能夠對半導體晶片120供給大電流。第一通孔142、144及第三通孔146、148亦可藉由光微影或雷射照射而形成。
接下來，於第一絕緣膜130上以埋入第一通孔142、144及第三通孔146、148之方式形成第一配線層150（圖3D）。第一配線層150能夠使用電解電鍍法或金屬膠體形成。第一配線層150能夠含有銅或金。對所形成之第一配線層150進行蝕刻加工以去除不要之部分，進而形成第一配線152、154（圖3E）。第一配線152埋入第一通孔142及第三通孔146，且通過第二端子124而電性連接於半導體晶片120。另一方面，第一配線154埋入第一通孔144及第三通孔148，且通過第二端子126而電性連接於半導體晶片120。第一配線152及154可不直接連接而彼此分離。其中，第一配線152及154為藉由加工第一配線層150而形成，故此些配線可存在於同一層內。
利用電解電鍍法形成第一配線層150之場合中，金屬可能不會充分埋入第一通孔142、144及第三通孔146、148。此時，能夠使用金屬膠體做為補充材料。舉例而言，亦可於第一配線層150形成前於第一通孔142、144或第三通孔146、148之一部分塗佈金屬膠體以形成金屬層，之後使用電解電鍍法形成第一配線層150。或者亦可於形成第一配線層150之後，使用金屬膠體追加形成金屬層。
接下來，剝離第一基板100（圖4A）。此剝離步驟能夠藉由施加物理性之力道或者藉由化學性之處理而進行。因此，第一基板100具有做為假基板之功能。剝離之後，亦可依需求而以蝕刻用之顯像液等物質洗淨與第一基板100接觸之表面。
之後，可經由第二絕緣膜135而於第一配線152、154上形成第二基板105。第二基板105能夠使用與第一基板100同樣的基板。第二基板105亦可直接使用剝離下來之第一基板100，亦可使用相異之新基板。第二絕緣膜135能夠使用與第一絕緣膜130同樣之材料。
接下來對接合膜110進行雷射照射或進行光微影，以形成第二通孔160，進而露出第一端子122（圖4B）。此處雖形成多個第二通孔160且以其尺寸小於第一通孔142、144之尺寸之方式描繪，但亦可形成單一個第二通孔160，且其尺寸亦可大於第一通孔142、144之尺寸。
接下來，可例如使用電解電鍍法或金屬膠體而形成第二配線層175（圖4C）。第二配線層175以埋入第二通孔160且接觸於第一端子122之方式形成。對所形成之第二配線層175進行蝕刻加工以去除不要之部分，進而形成第二配線170及第三配線172、174（圖4D）。第二配線170及第三配線172、174彼此分離。第二配線170電性連接於第一端子122，第三配線172電性連接於第一配線152，且第三配線174電性連接於第一配線154。第二配線170及第三配線172、174之任一者為加工第二配線層175而形成，故此些配線可存在於同一層內。
與第一配線層150之形成相同，亦可於第二配線層175形成前於第二通孔160之一部分塗佈金屬膠體以形成金屬層，之後使用電解電鍍法形成第二配線層175。或者亦可於藉由電解電鍍法形成第二配線層175之後，使用金屬膠體追加形成金屬層。
之後，亦可於第二配線170與第三配線172、174之間形成阻劑層180（圖5）。阻劑層180具有保護第二配線170、第三配線172、174之端部之功能，能夠例如使用樹脂且利用濕式製膜法而形成。而且於焊料選擇性地配置於第二配線170、第三配線172、174上之場合中，阻劑層180亦可使用焊料遮罩（mask）等之對於焊料具有較低親和性之材料。之後，亦可剝離第二基板105，或者亦可反過來留下第二基板105。使用金屬做為第二基板105之場合中，第二基板105留在半導體封裝件時，能夠使其具有做為散熱板之功能。
如上所述，關於本發明之實施型態之半導體封裝件之製造流程中，因能夠對於晶片雙面之端子使用相同手法（例如電解電鍍法）建構配線，故能夠於雙面端子上使用相同工程及相同製造裝置而形成配線。因此，能夠簡化製造處理流程，且能夠降低製造成本。而且，因能夠使用相同於晶片雙面之端子之材料（例如銅）而形成配線，故能夠達成具有高程度之熱可靠性之接合。
以下將說明第六實施型態。
於本實施型態中，將說明關於本發明之實施型態之半導體封裝之製作方法。具體而言，將使用圖6A至圖6D、圖7A至圖7D及圖8A及圖8B，說明使用形成有配線之基板做為第五實施型態所示之第一基板之範例。以下將省略與第五實施型態同樣之構造所相關之說明內容。
於本實施型態中，使用預先形成有配線（基板配線）202、204之基板（例如印刷配線基板）（圖6A）做為第一基板200。於第一基板200形成貫通通孔208，且設置有貫穿貫通通孔208之基板配線202、204。再者，於二個貫通通孔208之間設置貫通孔206。貫通孔206為至少一個即可，亦可設置為多個。
經由接合膜210將具備第一端子222及第二端子224、226之半導體晶片220接合於第一基板200上。此時，半導體晶片220以與貫通孔206重疊之方式接合（圖6A）。接下來，以埋入有半導體晶片220及第二端子224、226之方式形成第一絕緣膜230（圖6B）。半導體晶片220之固定方法或第一絕緣230之形成方法可與第五實施型態相同。
與第五實施型態同樣地，於第一絕緣膜230形成第一通孔242、244及第三通孔246、248。之後使用電解電鍍法或金屬膠體，於第一絕緣膜230上以埋入第一通孔242、244及第三通孔246、248之方式形成第一配線層250（圖6D）。再者，對第一配線層250進行蝕刻加工以形成第一配線252、254（圖7A）。因此，第一配線252、254雖彼此分離卻可存在於同一層內。第一配線252通過第二端子224而電性連接於半導體晶片220，第一配線254通過第二端子226而電性連接於半導體晶片220。
之後，與第五實施型態同樣地，於第一配線252、254上形成第二絕緣膜235（圖7B）。雖圖未示，但於第二絕緣膜235上亦可更形成有基板。
之後，通過貫通孔206進行雷射照射，以於接合膜210形成第二通孔260，進而露出第一端子222（圖7C）。此處雖形成多個第二通孔260，但亦可形成單一個第二通孔260。
之後，與第五實施型態同樣地，以與基板配線202、204、第一基板200重疊之方式且以埋入第二通孔260之方式，使用電解電鍍法或金屬膠體形成第二配線層275（圖7D），更進行蝕刻加工以形成第二配線270、第三配線272、274（圖8A）。另亦可依據需求於第二配線270與第三配線272、274之間形成阻劑層280（圖8B）。
如上所述，關於本發明之實施型態之半導體封裝件之製造流程中，因能夠對於晶片雙面之端子使用相同手法（例如電解電鍍法）建構配線，故能夠於雙面端子上使用相同工程及相同製造裝置而形成配線。因此，能夠簡化製造處理流程，且能夠降低製造成本。而且，因能夠使用相同於晶片雙面之端子之材料（例如銅）而形成配線，故能夠達成具有高程度之熱可靠性之接合。再者，因第一基板200並非必須剝離，且因如第五實施型態所進行而於第一配線252、254上並非必須形成第二基板105，故能夠縮短製造流程。而且，因能夠預先任意設計設置於貫通通孔208之基板配線202、204，故能夠使用適用於流通大電流之基板。
100:第一基板 105:第二基板 110:接合膜 120:半導體晶片 122:第一端子 124、126:第二端子 130:第一絕緣膜 135:第二絕緣膜 142、144:第一通孔 146、148:第三通孔 150:第一配線層 152、154、156:第一配線 160:第二通孔 170:第二配線 172、174:第三配線 175:第二配線層 180:阻劑層 200:第一基板 202、204:基板配線 206:貫通孔 208:貫通通孔 210:接合膜 220:半導體晶片 222:第一端子 224、226:第二端子 230:第一絕緣膜 235:第二絕緣膜 242、244:第一通孔 246、248:第三通孔 250:第一配線層 252、254:第一配線 260:第二通孔 270:第二配線 272、274:第三配線 275:第二配線層 280:阻劑層
[圖1A至圖1C]為本發明之一實施型態之半導體封裝件之剖面模式圖。
[圖2]為本發明之一實施型態之半導體封裝件之剖面模式圖。
[圖3A至圖3E]繪示本發明之一實施型態之半導體封裝件之製造方法之圖。
[圖4A至圖4D]繪示本發明之一實施型態之半導體封裝件之製造方法之圖。
[圖5]繪示本發明之一實施型態之半導體封裝件之製造方法之圖。
[圖6A至圖6D]繪示本發明之一實施型態之半導體封裝件之製造方法之圖。
[圖7A至圖7D]繪示本發明之一實施型態之半導體封裝件之製造方法之圖。
[圖8A及圖8B]繪示本發明之一實施型態之半導體封裝件之製造方法之圖。
105:第二基板
110:接合膜
120:半導體晶片
122:第一端子
124:第二端子
126:第二端子
130:第一絕緣膜
135:第二絕緣膜
142:第一通孔
144:第一通孔
146:第三通孔
148:第三通孔
152:第一配線
154:第一配線
160:第二通孔
170:第二配線
172:第三配線
174:第三配線
175:第二配線層
180:阻劑層

Claims (20)

  1. 一種半導體封裝件，包括： 半導體晶片； 絕緣結構，具有第一通孔，該半導體晶片藉由該絕緣結構覆蓋； 第一配線，位於該半導體晶片上，該第一配線通過該第一通孔而耦接至該半導體晶片； 接合膜，具有至少一第二通孔且位於該半導體晶片之下；以及 第二配線，位於該接合膜之下且該第二配線通過該第二通孔而耦接至該半導體晶片； 第三通孔，在該絕緣結構中；以及 第三配線，位於該絕緣結構之下且通過該第三通孔而耦接至該第一配線； 其中該絕緣結構所含有之材料與該接合膜所含有之材料相異，並且其中該第三配線與該第二配線電性分離。
  2. 如請求項1所述之半導體封裝件，其中： 該半導體晶片包括分別在該半導體晶片下方和上方的第一端子及第二端子，以及 該半導體晶片分別經由該第一端子和該第二端子而電性連接到該第二配線和該第一配線。
  3. 如請求項2所述之半導體封裝件，其中： 第三端子，設置在該半導體晶片上方並且與該第二端子電性分離； 第四配線，位在該半導體晶片上方並且經由在該絕緣結構中的第四通孔而耦接至該第三端子； 第五通孔，在該絕緣結構中；以及 第五配線，位在該絕緣結構下方並且經由該第五通孔而耦接至該第四配線，其中： 該第五配線、該第三配線以及該第二配線存在於同一層中，以及 該第一配線和該第四配線存在於同一層中。
  4. 如請求項1所述之半導體封裝件，其中： 該第二配線具有第一寬度； 該半導體晶片具有第二寬度；以及 該第一寬度大於該第二寬度。
  5. 如請求項1所述之半導體封裝件，其中： 該第二配線及該第三配線存在於同一層中。
  6. 如請求項1所述之半導體封裝件，其中： 該第一配線包括電鍍配線。
  7. 如請求項1所述之半導體封裝件，其中： 該接合膜之該至少一第二通孔之數量為多個；以及 該第二配線與該接合膜重疊且延伸至多個該第二通孔的每一個第二通孔中，以接觸該第一端子的部分。
  8. 如請求項1所述之半導體封裝件，其進一步包括： 基板，其包含穿透孔洞及基板配線，其中： 該半導體晶片藉由該接合層而被接合到該基板，如此以重疊所述穿透孔洞； 該接合膜進一步包括多個通孔，所述多個通孔包括該至少一第二通孔； 所述穿透孔洞與該多個通孔對準； 該第二配線在該基板下方並且經由所述穿透孔洞以及該多個通孔而電性連接到該半導體晶片；以及 該第三配線經由該基板配線及該第三通孔而電性連接到該第一配線。
  9. 如請求項1所述之半導體封裝件，其中： 該接合膜是絕緣材料。
  10. 一種半導體封裝件，包括： 半導體晶片，包括： 頂側； 底側，與該頂側相對； 橫向側，在該頂側和該底側之間延伸； 第一端子，在該頂側處；以及 第二端子，在該底側處，該第二端子比該第一端子寬； 第一絕緣結構，嵌入該半導體晶片，該第一絕緣結構包括： 第一側； 第二側，與該第一側相對； 第一通孔，自該第一側延伸至該第一端子；以及 第二通孔，自該第一側延伸至該第二側，該第二通孔與該第一通孔橫向地間隔開； 第一配線，在該第一通孔中且耦接至該第一端子，該第一配線延伸以與該第一絕緣結構的該第一側重疊； 第二配線，與該第一絕緣結構的該第二側相鄰且耦接至該第二端子；以及 第三配線，與該第一絕緣結構的該第二側相鄰且通過該第二通孔而耦接至該第一配線。
  11. 如請求項10所述之半導體封裝件，其進一步包括： 在該第一配線上方的第二絕緣結構。
  12. 如請求項11所述之半導體封裝件，其進一步包括： 在該第二絕緣結構上方的基板。
  13. 如請求項11所述之半導體封裝件，其中： 該第二絕緣結構覆蓋該第一配線，使得該第一配線沒有部分露出在該半導體封裝件之外。
  14. 如請求項10所述之半導體封裝件，其進一步包括： 在該第二配線和該第三配線上方的第二絕緣結構。
  15. 如請求項14所述之半導體封裝件，其中： 該第二絕緣結構將該第二配線與該第三配線電性分離； 該第二絕緣結構包括第一開口與第二開口； 該第二配線層藉由該第一開口露出；以及 該第三配線層藉由該第二開口露出。
  16. 如請求項10所述之半導體封裝件，其進一步包括： 接合層，其介於該第二端子和該第二配線層之間。
  17. 如請求項16所述之半導體封裝件，其中： 該接合層包括接合層通孔；以及 該第二配線層通過該接合層通孔而耦接至該第二端子。
  18. 如請求項10所述之半導體封裝件，其中： 該半導體晶片進一步包括位於該頂側處且與該第一端子橫向地間隔開的第三端子； 該第一絕緣結構包括自該第一絕緣結構的該第一側延伸至該第三端子的第三通孔； 該半導體封裝件進一步包括第四配線，該第四配線設置於該第三通孔中且耦接至該第三端子；以及 該第三端子比該第一端子寬。
  19. 如請求項18所述之半導體封裝件，其中： 該第一絕緣結構包括自該第一絕緣結構的該第一側延伸至該第二側的第四通孔； 該第四配線延伸以與該第一絕緣結構的該第一側重疊； 該第四配線包括鍍層，其進一步設置在該第四通孔內；以及 該半導體封裝件進一步包括與該第一絕緣層的該第二側相鄰的第五配線，該第五配線通過該第四通孔而耦接至該第四配線。
  20. 一種半導體封裝件，包括： 半導體晶片，包括分別在該半導體晶片下方和上方的第一端子和第二端子； 第一絕緣膜，具有第一通孔，該半導體晶片嵌入該第一絕緣膜中； 第一配線，在該半導體晶片上方，該第一配線通過該第一通孔而電性連接到該半導體晶片； 接合膜，位於該半導體晶片下方且具有至少一第二通孔；以及 第二配線，位於該接合膜下方，該第二配線通過該第二通孔而電性連接到該半導體晶片，其中該半導體晶片分別通過該第一端子和該第二端子而電性連接到該第二配線和該第一配線； 第三通孔，在該第一絕緣膜中； 第三配線，位於該第一絕緣膜下方且通過該第三通孔而電性連接到該第一配線； 第三端子，設置在該半導體晶片上方且與該第二端子電性分離； 第四配線，位於該第一絕緣膜上方且通過該第一絕緣膜中的第四通孔而電性連接到該第三端子； 第五通孔，在該第一絕緣膜中；以及 第五配線，位於該第一絕緣膜下方且通過該第五通孔而電性連接到該第四配線， 其中： 該第四通孔比該第一通孔寬， 該第五配線、該第三配線和該第二配線存在於同一層中， 該第一配線和該第四配線存在於同一層中，以及 該第一絕緣層所含有之材料與該接合膜所含有之材料相異，並且其中該第三配線與該第二配線電性分離。
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