TWI672784B - 封裝結構及封裝結構的製造方法 - Google Patents

封裝結構及封裝結構的製造方法 Download PDF

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TWI672784B
TWI672784B TW107135382A TW107135382A TWI672784B TW I672784 B TWI672784 B TW I672784B TW 107135382 A TW107135382 A TW 107135382A TW 107135382 A TW107135382 A TW 107135382A TW I672784 B TWI672784 B TW I672784B
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semiconductor wafer
conductive adhesive
adhesive layer
layer
metal carrier
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TW107135382A
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TW202008543A (zh
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林孝羲
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台達電子工業股份有限公司
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Publication of TW202008543A publication Critical patent/TW202008543A/zh

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Abstract

一種封裝結構，包含金屬載板、設置於金屬載板上的導電黏著層、設置於導電黏著層上的導電體、設置於導電黏著層上且與導電體橫向隔開的半導體晶片、以及設置於導電體和半導體晶片上的重佈線層。半導體晶片包含位於半導體晶片的上表面的第一端點。半導體晶片的第一端點透過重佈線層、導電體和導電黏著層電性連接至半導體晶片的底面。

Description

封裝結構及封裝結構的製造方法
本發明實施例是關於封裝結構及其製造方法，特別是有關於半導體晶片封裝技術。
一般而言，複雜電子系統之積體電路(Integrated circuit，IC)的組件具有大量互相連接之積體電路晶片或晶粒。積體電路晶片的尺寸製作的越來越小且電路密度逐漸升高。當積體電路晶片越來越密集，就單位體積之電消耗功率而言，其產生的熱也會對應的增加。以現有技術狀況的進展來看，充分消散熱量的能力常常侷限於封裝設計上的複雜性、更高的裝置操作速度和功耗。
本發明的一些實施例提供封裝結構，封裝結構包含金屬載板、設置於金屬載板上的導電黏著層、設置於導電黏著層上的導電體、以及設置於導電黏著層上且與導電體橫向隔開的半導體晶片。半導體晶片包含位於半導體晶片的上表面的第一端點。封裝結構還包含設置於導電體和半導體晶片上的重佈線層。半導體晶片的第一端點透過重佈線層、導 電體和導電黏著層電性連接至半導體晶片的底面。
本發明的一些實施例提供封裝結構，封裝結構包含第一導電黏著層和第二導電黏著層、分別設置於第一導電黏著層和第二導電黏著層上的第一導電體和第二導電體、以及分別設置於第一導電黏著層和第二導電黏著層上的第一半導體晶片和第二半導體晶片。第二導電黏著層與第一導電黏著層橫向隔開。第一半導體晶片包含位於第一半導體晶片的上表面的源極端點、汲極端點、和閘極端點。第二半導體晶片包含位於第二半導體晶片的上表面的源極端點、汲極端點、和閘極端點。封裝結構還包含設置於第一和第二導電體、以及第一和第二半導體晶片上的第一重佈線層。第一半導體晶片的源極端點透過第一重佈線層、第一導電體和第一導電黏著層電性連接至第一半導體晶片的底面。第一半導體晶片的源極端點透過第一重佈線層電性連接至第二半導體晶片的汲極端點。
本發明的一些實施例提供封裝結構的製造方法，此方法包含透過第一導電黏著層將第一導電體和第一半導體晶片接合至金屬載板；透過第二導電黏著層將第二導電體和第二半導體晶片接合至金屬載板；在金屬載板上形成第一絕緣層，以包覆第一和第二導電體、以及第一和第二半導體晶片；以及在第一絕緣層上形成重佈線層。第一導電體與第一半導體晶片橫向隔開，且第一半導體晶片包括位於第一半導體晶片的上表面的源極端點、汲極端點、和閘極端點。第二導電體與第二半導體晶片橫向隔開，且第二半導體晶片包括 位於第二半導體晶片的上表面的源極端點、汲極端點、和閘極端點。第一半導體晶片的源極端點透過重佈線層、第一導電體和第一導電黏著層電性連接至第一半導體晶片的底面。第一半導體晶片的源極端點透過重佈線層電性連接至第二半導體晶片的汲極端點。
本發明的封裝結構可應用於各種不同的封裝結構，為讓本發明之特徵和優點能更明顯易懂，下文特舉出一些實施例，並配合所附圖式，作詳細說明如下。
100、300、400、500A‧‧‧封裝結構
102‧‧‧金屬載板
102A‧‧‧第一金屬載板
102B‧‧‧第二金屬載板
102C‧‧‧第三金屬載板
104A‧‧‧第一導電黏著層
104B‧‧‧第二導電黏著層
104C‧‧‧第三導電黏著層
106A‧‧‧第一半導體晶片
106B‧‧‧第二半導體晶片
106A1、106B1‧‧‧源極端點
106A2、106B2‧‧‧汲極端點
106A3、106B3‧‧‧閘極端點
108A‧‧‧第一導電體
108B‧‧‧第二導電體
108C‧‧‧第三導電體
110‧‧‧第一絕緣層
112‧‧‧第二絕緣層
114‧‧‧第一導孔
114-1、114-2、114-3、114-4、114-5、114-6、114-7、114-8、114-9、114-10、114-11、118-1、118-2、118-3、118-4、118-5、118-6‧‧‧導孔
115‧‧‧第一重佈線層
116‧‧‧第一線路
116-1、116-2、116-3、116-4、116-5、116-6、120-1、120-2、120-3、120-4、120-5、120-6‧‧‧線路
117‧‧‧第三絕緣層
118‧‧‧第二導孔
119‧‧‧第二重佈線層
120‧‧‧第二線路
406‧‧‧驅動器
4061、4062、4063、5041、5042‧‧‧端點
502‧‧‧第四導電黏著層
504‧‧‧被動元件
H1、H2‧‧‧高度
藉由以下的詳細描述配合所附圖式，可以更加理解本發明實施例的內容。需強調的是，根據產業上的標準慣例，許多部件(feature)並未按照比例繪製。事實上，為了能清楚地討論，各種部件的尺寸可能被任意地增加或減少。
第1A-1D圖是根據本發明的一些實施例，顯示形成封裝結構於各種中間階段的剖面示意圖。
第2圖是根據本發明的一些實施例之封裝結構的等效電路圖。
第3圖是根據本發明的一些實施例之封裝結構的上視示意圖。
第4、5A和5B圖是根據本發明的一些實施例之封裝結構的剖面示意圖。
以下內容提供了很多不同的實施例或範例，用於實現本發明實施例的不同部件。組件和配置的具體實施例或 範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中若提及第一組件形成於第二組件之上，可能包含形成第一和第二組件直接接觸的實施例，也可能包含額外的組件形成於第一和第二組件之間，使得第一和第二組件不直接接觸的實施例。為了簡潔和明確起見，各種不同的組件可以不同尺寸任意繪示。此外，本發明實施例可能在不同的範例中重複元件符號及/或字母。如此重複是為了簡明和清楚，而非用以表示所討論的不同實施例之間的關係。
以下描述實施例的一些變化。在不同圖式和說明的實施例中，相似的元件符號被用來標示相似的元件。可以理解的是，在方法的前、中、後可以提供額外的步驟，且一些所敘述的步驟可在該方法的其他實施例被取代或刪除。
本揭露的封裝結構利用導電體和重佈線層，以形成半導體晶片之間的內連線(例如，半導體晶片的源極端點連接至其他半導體晶片的汲極端點)、及/或單一晶片內的內連線(例如，半導體晶片的背面連接至此晶片的源極端點)，致使此半導體晶片封裝具有高佈局(layout)彈性。再者，本揭露的封裝結構利用金屬載板、導電體和重佈線層作為散熱器(heat sink)，以消散半導體晶片產生的熱量，進而改善半導體晶片的效能。
第1A-1D圖是根據本發明的一些實施例，顯示形成第1D圖所示之封裝結構100於各種中間階段的剖面示意圖。請參考第1A圖，提供金屬載板102。金屬載板102也可稱為金 屬基板，並且支撐形成於其上的部件。金屬載板102可以是具有高導熱性的金屬載板。在一些實施例中，金屬載板102的材料可以是銅(Cu)、鋁(Al)、金(Au)、銀(Ag)、錫(Sn)、鉑(Pt)、前述之合金、或類似材料。在一些實施例中，金屬載板102的厚度可在約0.1公厘(mm)至約2公分(cm)。
透過第一導電黏著層104A將第一導電體(post)108A和第一半導體晶片106A接合至金屬載板102，其中第一半導體晶片106A與第一導電體108A橫向隔開。在一些實施例中，第一半導體晶片106A可包含積體電路，例如邏輯積體電路、數位積體電路、混合信號積體電路、功率型積體電路、或記憶電路；微機電系統(micro-electro mechanical system，MEMS)；光電裝置；感測器，例如光感測器或指紋感測器；或類似裝置。在一些實施例中，第一半導體晶片106A包含形成於其中的主動元件(未顯示)，例如電晶體、金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor，MOSFET)、金屬絕緣體半導體場效電晶體(metal insulator semiconductor FET，MISFET)、接面場效電晶體(junction field transistor，JFET)、絕緣閘雙極電晶體(insulated gate bipolar transistor，IGBT)、前述之組合、或類似元件。在一實施例中，第一半導體晶片106A可以是會在操作期間產生大量熱量的功率型半導體晶片。功率型半導體晶片可以是或者包含功率型MISFET、功率型MOSFET、高電子遷移率電晶體(high electron mobility transistor，HEMT)、或類似晶片。
第一半導體晶片106A具有多個端點(terminal，也可稱為導電墊(pad))，這些端點位於第一半導體晶片106A的上表面。這些端點包含源極端點106A1、汲極端點106A2、和閘極端點106A3。在一些實施例中，第一半導體晶片106A是橫向型(lateral)晶片，並且在第一半導體晶片106A的底面沒有端點。易言之，第一半導體晶片106A的全部端點僅設置於它的兩個主表面之其中一面，例如在第一半導體晶片106A的上表面。第一半導體晶片之沒有端點的另一主表面(例如，底面)黏合至第一導電黏著層104A。在一實施例中，第一半導體晶片106A是包含氮化鎵(GaN)半導體材料的橫向型晶片。第一半導體晶片106A的主動元件透過內連線結構(未顯示)電性連接至源極、汲極和閘極端點106A1、106A2和106A3。內連線結構可以包含形成於層間介電層(interlayer dielectric，ILD)中的接觸插塞(contact plug)及/或形成於金屬間介電層(inter-metal dielectric，IMD)的導孔(via)和金屬線。在一些實施例中，第一半導體晶片106A的高度H1在約50微米(μm)至約400微米的範圍內。
在一些實施例中，第一導電體108A可具有高導電性和高導熱性。第一導電體108A也可稱為導電板(sheet)。在一些實施例中，第一導電體108A的材料可以是或者包含銅(Cu)、鋁(Al)、金(Au)、銀(Ag)、鉑(Pt)、鉛(Pt)、錫(Sn)、前述之合金、或類似材料。在一些實施例中，第一導電體108A的側壁可以垂直於其底面，如第1A圖所示。在其他一些實施例中，第一導電體108A的側壁可以從它的一個主表面朝著另 一面漸縮。第一導電體108A具有高度H2，高度H2可等於或大於第一半導體晶片106A的高度H1。在一些實施例中，高度H2可以在約100微米至約400微米的範圍內。當從上視角度觀之，第一導電體108A可具有任何形狀，例如圓形、橢圓形、長方形、多邊形或線型輪廓。
在一些實施例中，第一導電黏著層104A可以是具有良好的導電性的膏體(paste)、膠帶或焊料(solder)。第一導電黏著層104A的材料可以是銅(Cu)、鋁(Al)、金(Au)、銀(Ag)、鉑(Pt)、鉛(Pt)、錫(Sn)、前述之合金、或類似材料。在一些實施例中，可透過例如網印製程(screen printing process)、表面黏著技術(surface mount technology，SMT)、或點膠製程(dispensing process)，黏附第一導電黏著層104A至金屬載板102。然後，以第一半導體晶片106A和第一導電體108A的底面面向第一導電黏著層104A的方式，將第一半導體晶片106A和第一導電體108A垂直地放置在第一導電黏著層104A上。在一些實施例中，第一導電體108A的側壁大致上垂直於金屬載板的主表面。舉例而言，第一導電體108A之側壁的延伸線與金屬載板102A之主表面相交的角度範圍在約80°至約100°。
繼續參考第1A圖，透過第二導電黏著層104B將第二導電體108B和第二半導體晶片106B接合至金屬載板102，其中第二半導體晶片106B與第二導電體108B橫向隔開。第二導電黏著層104B與第一導電黏著層104A橫向隔開。
在一些實施例中，第二半導體晶片106B可以相同 或相似於前述的第一半導體晶片106A。舉例而言，第二半導體晶片106B可以是功率型半導體晶片。第二半導體晶片106B具有源極端點106B1、汲極端點106B2、和閘極端點106B3，這些端點106B1、106B2、106B3位於第二半導體晶片106B的上表面。在一些實施例中，第二半導體晶片106B是橫向型晶片，並且在第二半導體晶片106B的底面沒有端點。在一實施例中，第二半導體晶片106B是包含氮化鎵(GaN)半導體材料的橫向型晶片。在一些實施例中，第二導電體108B和第二導電黏著層104B的材料和形成方法可與前述第一導電體108A和第一導電黏著層104A的材料和形成方法相同或相似。
請參考第1B圖，在金屬載板102上形成第一絕緣層110，以包覆(encapsulate)第一和第二導電黏著層104A和104B、第一和第二導電體108A和108B、以及第一和第二半導體晶片106A和106B。形成第一絕緣層110以覆蓋第一和第二導電黏著層104A和104B、第一和第二導電體108A和108B、以及第一和第二半導體晶片106A和106B的全部表面。第一絕緣層110大致上填充第一導電體108A與第一半導體晶片106A之間的間隙、第二導電體108B與第二半導體晶片106B之間的間隙、以及第一導電體108A與第二半導體晶片106B之間的間隙。
在一些實施例中，第一絕緣層110的材料可以是介電材料(例如氧化矽或氮化矽)；模塑材料(molding material)；熱塑性(thermoplastic)材料(例如環氧樹脂(epoxy resin)或丙烯酸樹脂(acrylic resin))；熱固性材料(例如聚醚醯 亞胺(polyetherimide，PEI)、聚醚碸(polyether-sulfone，PES)、聚苯硫醚(polyphenylene-sulfide，PPS)、聚酰胺-酰亞胺(polyamide-imide，PAI)、或聚對苯二甲酸乙二醇酯(polyethylene-terephthalate，PET))；或層壓材料(laminate material)(例如纖維增強高分子層壓材料或具有顆粒填充的纖維增強高分子層壓材料)。在一些實施例中，可透過沉積製程、旋轉塗佈(spin-on coating)製程、層壓製程、模塑製程(例如壓模塑或射出模塑)第一絕緣層110、或類似方法形成第一絕緣層110。
接著，對第一絕緣層110執行平坦化製程，例如機械研磨製程。將第一絕緣層110從其上表面薄化至第一和第二導電體108A和108B的上表面暴露出來。在平坦化製程之後，第一絕緣層110的上表面與第一和第二導電體108A和108B的上表面共平面。在其他一些實施例中，此平坦化製程可甚至執行至第一和第二半導體晶片106A和106B的端點106A1、106A2、106A3、106B1、106B2和106B3暴露出來。
請參考第1C圖，形成第二絕緣層112於第一絕緣層110的上表面上且覆蓋第一和第二導電體108A和108B的上表面。在一些實施例中，第二絕緣層112的材料和形成方法可與前述第一絕緣層110的材料和形成方法相同或相似。
接著，在第二絕緣層112上形成第一重佈線(redistribution)層115。第一重佈線層115包含複數個第一導孔(via)114，這些第一導孔114穿過第二和第一絕緣層112和110，並且落在第一和第二半導體晶片106A和106B的上述多 個端點、以及第一和第二導電體108A和108B上。第一重佈線層115還包含複數個第一線路(trace)116，這些第一線路116設置於第二絕緣層112的上表面上且連接這些第一導孔114。
在一些實施例中，這些第一導孔114包含至少八個導孔114-1、114-2、114-3、114-4、114-5、114-6、114-7和114-8。導孔114-1、114-2和114-3分別落在第一半導體晶片106A的源極、汲極和閘極端點106A1、106A2和106A3上；導孔114-4落在第一導電體108A上；導孔114-5、114-6和114-7分別落在第二半導體晶片106B的源極、汲極和閘極端點106B1、106B2和106B3上；以及導孔114-8落在第二導電體108B上。在一些實施例中，這些第一線路116包含彼此電性隔離的至少五個線路116-1、116-2、116-3、116-4和116-5。導孔114-1、114-4和114-6與線路116-1連接；導孔114-5和114-8與線路116-4連接；以及導孔114-2、114-3和114-7分別與線路116-2、116-3和116-5連接。
在一些實施例中，第一重佈線層115(包含第一導孔114和第一線路116)可以是或者包含銅(Cu)、鋁(Al)、金(Au)、銀(Ag)、鉑(Pt)、鉛(Pt)、錫(Sn)、前述之合金、或類似材料。形成第一重佈線層115的步驟可包含例如透過雷射鑽孔製程穿過第二絕緣層112和第一絕緣層110形成多個導孔開口(未顯示)，以暴露出第一和第二半導體晶片116A和116B的上述多個端點以及第一和第二導電體108A和108B，接著透過鍍製(例如電鍍或無電電鍍)形成複數個第一導孔114於相應的導孔開口中且形成複數個第一線路116於這些第一導孔114和 第二絕緣層112上。
繼續參考第1C圖，形成第三絕緣層117在第二絕緣層112的上表面，且覆蓋這些第一線路116。在一些實施例中，第三絕緣層117的材料和形成方法可與前述第一絕緣層110的材料和形成方法相同或相似。
接著，在第三絕緣層117上形成第二重佈線層119。第二重佈線層119電性連接至第一重佈線層115。第二重佈線層119包含複數個第二導孔118，這些第二導孔118穿過第三絕緣層117，並且落在這些第一線路116上。第二重佈線層119還包含複數個第二線路120，這些第二線路120設置於第三絕緣層117的上表面上且連接這些第二導孔118。在一些實施例中，這些第二線路120作為接腳(pin-out)以連接外部電路(未顯示)。
在一些實施例中，這些第二導孔118包含至少五個導孔118-1、118-2、118-3、118-4和118-5，它們分別落在線路116-1、116-2、116-3、116-4和116-5上。在一些實施例中，這些第二線路120包含彼此電性隔離的至少五個線路120-1、120-2、120-3、120-4和120-5。這些導孔118-1、118-2、118-3、118-4和118-5分別與這些線路120-1、120-2、120-3、120-4和120-5連接。在一些實施例中，第二重佈線層119的材料和形成方法可與前述第一重佈線層115的材料和形成方法相同或相似。
請參考第1D圖，對金屬載板102執行圖案化製程以形成第一金屬載板102A和第二金屬載板102B，其中第二金 屬載板102B與第一金屬載板102A橫向隔開。在一些實施例中，第二金屬載板102B與第一金屬載板102A的間距大於約0.2公厘。第一導電黏著層104A和第二導電黏著層104B分別位於第一金屬載板102A和第二金屬載板102B上。在圖案化製程之後，第一絕緣層110將第一和第二半導體晶片106A和106B的底面彼此電性隔離。在一些實施例中，圖案化製程可包含將第1C圖所示的封裝結構上下翻轉、在金屬載板102的底面上形成圖案化遮罩(未顯示)、通過圖案化遮罩來蝕刻金屬載板102、以及例如透過濕剝除(wet strip)或灰化(ash)製程移除圖案化遮罩。對金屬載板102執行的蝕刻製程可以是濕式蝕刻，其使用化學品例如氯化銅、氯化鐵、HF、NaOH、HNO3、K3Fe(CN)6、KI、或硫酸。在一些實施例中，在圖案化製程之前，第1C圖所示的封裝結構可安裝至臨時載板，在圖案化製程期間，臨時載板支撐此封裝結構，在圖案化製程之後，可移除臨時載板。在圖案化製程之後，製得封裝結構100。
在本發明實施例中，封裝結構100包含第一和第二金屬載板102A和102B、第一和第二導電黏著層104A和104B、第一和第二導電體108A和108B、第一和第二半導體晶片106A和106B、第一絕緣層110、以及第一重佈線層115。
第一和第二導電黏著層104A和104B分別設置於第一和第二金屬載板102A和102B上。第二金屬載板102A與第一金屬載板橫向隔開。第二導電黏著層104B與第一導電黏著層104A被第一絕緣層110橫向隔開。第一導電體108A與第一半導體晶片106A設置於第一導電黏著層104A上，且第二導電體 108B和第二半導體晶片106B設置於第二導電黏著層104B上。第一半導體晶片106A包含設置於第一半導體晶片106A的上表面的源極端點106A1、汲極端點106A2和閘極端點106A3。第二半導體晶片106B包含設置於第二半導體晶片106B的上表面的源極端點106B1、汲極端點106B2和閘極端點106B3。第一絕緣層110包覆第一和第二導電黏著層104A和104B、第一和第二導電體108A和108B、以及第一和第二半導體晶片106A和106B。包含複數個第一導孔114和複數個第一線路116的第一重佈線層115設置於第一絕緣層110上。
第一半導體晶片106A的源極端點106A1透過第一重佈線層115電性連接至第二半導體106B的汲極端點106B2，因此封裝結構100可以包含半橋電路(half-bridge circuitry)。半橋電路可以是用於將直流(DC)或交流(AC)電壓轉換為直流電壓的轉換器。請參考第2圖，第2圖是本發明的一些實施例之封裝結構100的等效電路圖。第一半導體晶片106A和第二半導體晶片106B形成半橋電路。在一些實施例中，第一半導體晶片106A可以是半橋電路的高端(high side)功率開關，而第二半導體晶片106B可以是半橋電路的低端(low side)功率開關。
回頭參考第1D圖，第一半導體晶片106A的源極端點106A1透過第一重佈線層115(導孔114-1和114-4、及線路116-1)、第一導電體108A、和第一導電黏著層104A電性連接至第一半導體106A的底面。因此，源極端點106A1與第一半導體晶片106A的底面可以在相同電位。第二半導體晶片106B的源極端點106B1透過第一重佈線層115(導孔114-5和114-8、 及線路116-4)、第二導電體108B、和第二導電黏著層104B電性連接至第二半導體106B的底面。因此，源極端點106B1與第二半導體晶片106B的底面可以在相同電位。半導體晶片的源極端點具有與半導體晶片底面在相同電位，以改善半導體晶片抗擊穿(breakdown)能力。值得注意的是，第一和第二金屬載板102A和102B彼此隔開，以防止第一半導體晶片106A的源極端點106A1和底面電性連接至第二半導體晶片106B的源極端點106B1和底面。
在本發明實施例中，具有良好的導熱性的第一和第二金屬載板102A和102B作為散熱器，以消散第一和第二半導體晶片106A和106B在操作期間產生的熱量。在一些實施例中，第一和第二金屬載板102A和102B覆蓋等於或大於封裝結構100之底面面積的約20%，這提升封裝基板100的散熱能力。
再者，第一和第二半導體晶片106A和106B僅透過第一和第二導電黏著層104A和104B黏合至第一和第二金屬載板102A和102B，這提升封裝基板100的散熱能力。
再者，在本發明實施例中，第一和第二導電體108A和108B、以及第一和第二重佈線層115和119也作為散熱器，以消散第一和第二半導體晶片106A和106B在操作期間產生的熱量。
本發明實施例利用導電體和重佈線層，以形成半導體晶片之間的內連線(例如，半導體晶片的源極端點連接至其他半導體晶片的汲極端點)、及/或單一晶片內的內連線(例如，半導體晶片的背面連接至此晶片的源極端點)，致使此導 體晶片封裝具有高佈局彈性。再者，本揭露的封裝結構利用金屬載板、導電體和重佈線層作為散熱器，以消散半導體晶片產生的熱量，進而改善半導體晶片的效能。
儘管如第1D圖所示的封裝結構100包含兩個半導體晶片106A和106B，但基於設計需求封裝結構100可包含一或多於兩個半導體晶片、及/或被動元件。
第3圖是根據本發明的一些實施例之封裝結構300的上視示意圖，其中相同於前述第1D圖的實施例的元件或膜層係使用相同的參考符號，並為了簡潔起見省略其說明。封裝結構300包含第一絕緣層110、第一和第二半導體晶片106A和106B、第一和第二導電體108A和108B、第一重佈線層的複數個第一線路116、以及第二重佈線層的複數個第二線路120。為了簡潔明確，第3圖僅顯示以上部件，並且封裝結構300亦可包含如第1D圖所示的金屬載板、導電黏著層和複數個導孔。
如第3圖所示，當從上視角度觀之，第一導電體108A的投影面積完全位於線路116-1的投影面積內，並且第二導電體108B的投影面積完全位於線路116-4的投影面積內。
如第3圖所示，這些第一線路116包含彼此隔離的線路116-1、116-2、116-3、116-4和116-5。在一些實施例中，當從上視角度觀之，這些第一線路116覆蓋等於或大於第二絕緣層112(顯示於第1D圖)投影面積的約50%。較高的投影面積的第一線路116導致封裝結構300之較佳的散熱性。
第4圖是根據本發明的一些實施例之封裝結構400 的剖面示意圖，其中相同於前述第1D圖的實施例的元件或膜層係使用相同的參考符號，並為了簡潔起見省略其說明。第4圖與第1D之實施例的差異在於，封裝結構400更包含第三金屬載板102C、設置於第三金屬載板102C上的第三導電黏著層104C、以及設置於第三導電黏著層104C上的驅動器406。
在一些實施例中，透過第三導電黏著層104C將驅動器406接合至金屬載板102(顯示於第1A圖)。在執行前面關於第1A-1C圖所述的製程之後，對金屬載板102執行前面關於第1D圖所述的圖案化製程，以形成第三金屬載板102C。第三金屬載板102C與第一和第二金屬載板102A和102B橫向隔開。第三導電黏著層104C與第一和第二導電黏著層104A和104B橫向隔開。第一絕緣層110包覆驅動器406。
在一些實施例中，驅動器406配置以提供信號至第一和第二半導體晶片106A和106B的閘極端點106A3和106B3，並且驅動器406可包含形成於其中的主動元件(未顯示)，例如金屬氧化物半導體場效電晶體(MOSFET)、接面場效電晶體(JFET)、絕緣閘雙極電晶體(IGBT)、電晶體、前述之組合、或類似主動元件。驅動器406具有至少三個端點4061、4062和4063。驅動器406的端點4061和4062透過第一重佈線層115電性連接至第一和第二半導體晶片106A和106B的閘極端點106A3和106B3。
複數個第一導孔114還包含導孔114-9、114-10和114-11，它們穿過第二和第一絕緣層112和110，且分別落在驅動器406的端點4061、4062和4063上。複數個第一線路116還 包含線路116-6，線路116-6與第一線路116的其他線路電性隔離。導孔114-9連接線路116-3，使得驅動器406的端點4061電性連接至第一半導體晶片106A的閘極端點106A3。導孔114-10連接線路116-5，使得驅動器406的端點4062電性連接至第二半導體晶片106B的閘極端點106B3。導孔114-11連接線路116-6。複數個第二導孔118還包含導孔118-6，導孔118-6穿過第三絕緣層117，且落在線路116-6上。複數個第二線路120還包含線路120-6，線路120-6與第二線路120的其他線路電性隔離。導孔118-6連接線路120-6。線路120-6作為接腳以連接外部電路(未顯示)。
第5A圖是根據本發明的一些實施例之封裝結構500A的剖面示意圖，其中相同於前述第1D圖的實施例的元件或膜層係使用相同的參考符號，並為了簡潔起見省略其說明。第5A圖與第1D之實施例的差異在於，封裝結構500A更包含設置於第二重佈線層120上的被動元件504。
請參考第5A圖，在第1D圖所示的封裝結構上形成被動元件504。在一些實施例中，被動元件504可以是電容、電感、電阻、或類似被動元件。被動元件504具有兩個端點5041和5042。透過第四導電黏著層502將被動元件504的端點5041和5042分別接合至第二重佈線層119的線路120-2和120-4，因而端點5041和5042電性連接至第一半導體晶片106A的汲極端點106A2和第二半導體晶片106B的源極端點106B1。在一些實施例中，第四導電黏著層502具有良好的導電性的膏體(paste)、膠帶或焊料(solder)。第四導電黏著層502的材料可以 是銅(Cu)、鋁(Al)、金(Au)、銀(Ag)、鉑(Pt)、鉛(Pt)、錫(Sn)、前述之合金、或類似材料。
第5B圖是根據本發明的一些實施例之封裝結構500B的剖面示意圖，其中相同於前述第5A圖的實施例的元件或膜層係使用相同的參考符號，並為了簡潔起見省略其說明。第5A圖與第5B之實施例的差異在於，封裝結構500B的被動元件504設置於第一重佈線層115上且在第三絕緣層117中。
在形成第一重佈線層115之後，在第一重佈線層115上形成被動元件504。被動元件504具有兩個端點5041和5042，且透過第四導電黏著層502分別將端點5041和5042接合至線路116-2和116-4。端點5041和5042電性連接至第一半導體晶片106A的汲極端點106A2和第二半導體晶片106B的源極端點106B1。形成第三絕緣層117以覆蓋被動元件504。導孔118-2和118-4穿過第三絕緣層117，且分別落在被動元件504的端點5041和5042上。導孔118-1、118-3和118-5以虛線繪示是表示導孔118-1、118-3和118-5位於第5B圖的剖面示意圖之後，並未穿過被動元件504。
本揭露的封裝結構利用導電體和重佈線層，以形成半導體晶片之間的內連線(例如，半導體晶片的源極端點連接至其他半導體晶片的汲極端點)、及/或單一晶片內的內連線(例如，半導體晶片的背面連接至此晶片的源極端點)，致使此半導體晶片封裝具有高佈局彈性。再者，本揭露的封裝結構利用金屬載板、導電體和重佈線層作為散熱器，以消散半導體晶片產生的熱量，進而改善半導體晶片的效能。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。

Claims (20)

  1. 一種封裝結構，包括：一金屬載板；一導電黏著層，設置於該金屬載板上；一導電體，設置於該導電黏著層上；一半導體晶片，設置於該導電黏著層上且與該導電體橫向隔開，其中該半導體晶片包括位於該半導體晶片的上表面的一第一端點；以及一重佈線層，設置於該導電體和該半導體晶片上，其中該半導體晶片的該第一端點透過該重佈線層、該導電體和該導電黏著層電性連接至該半導體晶片的底面。
  2. 如申請專利範圍第1項所述之封裝結構，其中該半導體晶片的該第一端點是一源極端點。
  3. 如申請專利範圍第2項所述之封裝結構，其中該半導體晶片更包括位於該半導體晶片的上表面的一汲極端點和一閘極端點。
  4. 如申請專利範圍第3項所述之封裝結構，其中該重佈線層包含彼此電性隔離的一第一線路(trace)、一第二線路、和一第三線路，其中該第一線路、該第二線路、和該第三線路分別電性連接至該源極端點、該汲極端點、和該閘極端點。
  5. 如申請專利範圍第4項所述之封裝結構，其中當從上視角度觀之，該導電體的投影面積完全位於該重佈線層的該第一線路的投影面積內。
  6. 如申請專利範圍第1項所述之封裝結構，更包括：一絕緣層，設置於該金屬載板上且包覆該導電黏著層、該半導體晶片和該導電體，其中該重佈線層設置於該絕緣層上。
  7. 如申請專利範圍第6項所述之封裝結構，其中該絕緣層的上表面與該導電體的上表面共平面。
  8. 如申請專利範圍第1項所述之封裝結構，其中該導電體的側壁垂直於該金屬載板的主表面。
  9. 如申請專利範圍第1項所述之封裝結構，其中該半導體晶片是一橫向型晶片。
  10. 如申請專利範圍第1項所述之封裝結構，其中從上視角度觀之，該導電體具有長方形輪廓。
  11. 一種封裝結構，包括：一第一導電黏著層和一第二導電黏著層，該第二導電黏著層與該第一導電黏著層橫向隔開；一第一導電體和一第二導電體，分別設置於該第一導電黏著層和該第二導電黏著層上；一第一半導體晶片，設置於該第一導電黏著層上，其中該第一半導體晶片包括位於該第一半導體晶片的上表面的一源極端點、一汲極端點、和一閘極端點；一第二半導體晶片，設置於該第二導電黏著層上，其中該第二半導體晶片包括位於該第二半導體晶片的上表面的一源極端點、一汲極端點、和一閘極端點；以及一第一重佈線層，設置於該第一和該第二導電體、以及該第一和該第二半導體晶片上，其中該第一半導體晶片的該源極端點透過該第一重佈線層、該第一導電體和該第一導電黏著層電性連接至該第一半導體晶片的底面，其中該第一半導體晶片的該源極端點透過該第一重佈線層電性連接至該第二半導體晶片的該汲極端點。
  12. 如申請專利範圍第11項所述之封裝結構，更包括：一第一金屬載板和一第二金屬載板，該第一和該第二導電黏著層分別設置於該第一和該第二金屬載板上，且該第二金屬載板與該第一金屬載板橫向隔開。
  13. 如申請專利範圍第11項所述之封裝結構，更包括：一絕緣層，包覆該第一和該第二導電黏著層、該第一和該第二導電體、和該第一和該第二半導體晶片，其中該第一重佈線層設置於該絕緣層上。
  14. 如申請專利範圍第11項所述之封裝結構，其中該第一重佈線層包括：彼此電性隔離的複數個線路，其中該些線路包括：一第一線路，電性連接至該第一半導體晶片的該源極端點、該第一導電體、和該第二半導體晶片的該汲極端點；以及一第二線路，電性連接至該第二半導體晶片的該源極端點和該第二導電體。
  15. 如申請專利範圍第14項所述之封裝結構，更包括：一第二重佈線層，設置於該第一重佈線層上，其中該第二重佈線層包含複數個線路，且該第二重佈線層的該些線路各自對應該第一重佈線層的該些線路。
  16. 如申請專利範圍第11項所述之封裝結構，更包括；一第三導電黏著層，與該第一和該第二導電黏著層橫向隔開；以及一驅動器，設置於該第三導電黏著層上，其中該驅動器包括位於該驅動器之上表面的兩個端點，其中該驅動器的該兩個端點透過該第一重佈線層電性連接至該第一和該第二半導體晶片的該些閘極端點。
  17. 如申請專利範圍第11項所述之封裝結構，更包括：一被動元件，設置於該第一重佈線層上，其中該被動元件包括兩個端點，該被動元件的該兩個端點分別電性連接至該第一半導體晶片的該汲極端點和該第二半導體晶片的該源極端點。
  18. 一種封裝結構的製造方法，包括：透過一第一導電黏著層將一第一導電體和一第一半導體晶片接合至一金屬載板，其中該第一半導體晶片與該第一導電體橫向隔開，且該第一半導體晶片包括位於該第一半導體晶片的上表面的一源極端點、一汲極端點、和一閘極端點；透過一第二導電黏著層將一第二導電體和一第二半導體晶片接合至該金屬載板，其中該第二半導體晶片與該第二導電體橫向隔開，且該第二半導體晶片包括位於該第二半導體晶片的上表面的一源極端點、一汲極端點、和一閘極端點；在該金屬載板上形成一第一絕緣層，以包覆該第一和該第二導電體、以及該第一和該第二半導體晶片；以及在該第一絕緣層上形成一重佈線層，其中該第一半導體晶片的該源極端點透過該重佈線層、該第一導電體和該第一導電黏著層電性連接至該第一半導體晶片的底面，其中該第一半導體晶片的該源極端點透過該重佈線層電性連接至該第二半導體晶片的該汲極端點。
  19. 如申請專利範圍第18項所述之封裝結構的製造方法，更包括：對該金屬載板執行一圖案化製程，以形成彼此隔開的一第一金屬載板和一第二金屬載板，其中該第一和該第二導電黏著層分別位於該第一和該第二金屬載板上。
  20. 如申請專利範圍第18項所述之封裝結構的製造方法，更包括：在形成該重佈線層之前，對該第一絕緣層執行一平坦化製程直到暴露出該第一和該第二導電體的上表面。
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