CN113782455A - 芯片封装及其形成方法 - Google Patents

芯片封装及其形成方法 Download PDF

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Publication number
CN113782455A
CN113782455A CN202111060983.4A CN202111060983A CN113782455A CN 113782455 A CN113782455 A CN 113782455A CN 202111060983 A CN202111060983 A CN 202111060983A CN 113782455 A CN113782455 A CN 113782455A
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China
Prior art keywords
interposer substrate
semiconductor die
substrate
layer
forming
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CN202111060983.4A
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English (en)
Inventor
郑心圃
蔡柏豪
庄博尧
翁得期
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority claimed from CN201810730689.1A external-priority patent/CN109727876A/zh
Publication of CN113782455A publication Critical patent/CN113782455A/zh
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Abstract

提供芯片封装的结构及其形成方法。此方法包含：设置半导体晶粒于载体基板之上。此方法也包含设置中介层基板于此载体基板之上。此中介层基板具有凹槽，此凹槽穿过该中介层基板的相反面。此中介层基板具有围绕半导体晶粒的内部侧壁，并且此半导体晶粒等高于或高于此中介层基板。此方法还包含在中介层基板的凹槽中形成保护层，以围绕半导体晶粒。另外，此方法包含移除载体基板以及堆叠封装结构于该中介层基板之上。

Description

芯片封装及其形成方法
本发明是申请日为：2018年7月5日；申请号为：201810730689.1；发明名称为：芯片封装及其形成方法的发明申请的分案申请。
技术领域
本公开涉及一种半导体装置的结构及其形成方法，且特别有关于一种散出型(Fan-Out)芯片封装的结构及其形成方法。
背景技术
半导体装置用于各种不同的电子应用，例如，个人电脑、手机、数码相机和其他电子设备。半导体装置的制造通常通过在半导体基板上按序沉积绝缘或介电层、导电层和半导体层的材料，并且使用光刻和蚀刻工艺将各种材料层图案化，以形成电路组件以及元件于半导体基底上。
半导体工业通过持续微缩最小部件的尺寸，使得更多组件整合至给定的区域中，以持续改善各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度。在一些应用中，这些较小的电子组件也使用了应用较小面积或较低高度的较小的封装。
新的封装技术，例如：堆叠式封装(package on package，PoP)已经开始发展，在其中具有装置芯片的顶部封装接合至具有另一装置芯片的底部封装。通过采用这些新的封装技术，可将具有不同或相似功能的各种封装整合在一起。这些较新颖的半导体装置的封装技术实施方式面临了工艺的挑战。
发明内容
根据一些实施例提供一种芯片封装的形成方法。此方法包含：设置半导体晶粒于载体基板之上。此方法也包含设置中介层基板于此载体基板之上。此中介层基板具有凹槽，此凹槽穿过该中介层基板的相反面。此中介层基板具有围绕半导体晶粒的内部侧壁，并且此半导体晶粒等高于或高于此中介层基板。此方法还包含在中介层基板的凹槽中形成保护层，以围绕半导体晶粒。另外，此方法包含移除载体基板以及堆叠封装结构于该中介层基板之上。
根据一些实施例提供一种芯片封装的形成方法。此方法包含：形成第一重布结构于载体基板之上，并且接合一半导体晶粒与此第一重布结构。此方法也包含接合中介层基板与此第一重布结构。此中介层基板具有围绕此半导体晶粒的环型结构，并且此半导体晶粒等高于或高于此中介层基板。此方法还包含形成保护层以围绕此半导体晶粒。此保护层的一部分在此中介层基板与此半导体晶粒之间。另外，此方法包含移除此载体基板，以及接合封装结构于此中介层基板之上。此半导体晶粒在此封装结构与此第一重布结构之间。
根据一些实施例提供芯片封装。此芯片封装包含：第一重布结构，以及接合于此第一重布结构之上的半导体装置。此芯片封装也包含接合于此第一重布结构之上的中介层基板。此中介层基板具有围绕此半导体装置的内部侧壁，并且此半导体装置等高于或高于此中介层基板。此芯片封装还包含围绕此半导体装置的保护层。另外，此芯片封装包含第二重布结构于此保护层之上。此第二重布结构的第一导电部件电性连接至此中介层基板的第二导电部件。
附图说明
通过以下的详述配合附图，可以更加理解本公开实施例的观点。应注意的是，依据在业界的标准惯例，各种部件并未按照比例绘制且仅用以说明例示。事实上，为了讨论的明确易懂，各种部件的尺寸可任意增加或减少。
图1A至1K是根据一些实施例示出形成芯片封装的制程的各种阶段的剖面图。
图2A至2D是根据一些实施例示出形成芯片封装的制程的各种阶段的剖面图。
图3A至3E是根据一些实施例示出形成芯片封装的制程的各种阶段的剖面图。
图4A至4B是根据一些实施例示出形成芯片封装的制程的各种阶段的剖面图。
图5A至5F是根据一些实施例示出形成芯片封装的制程的各种阶段的剖面图。
图6A至6B是根据一些实施例示出形成芯片封装的制程的各种阶段的剖面图。
图7A至7I是根据一些实施例示出形成芯片封装的制程的各种阶段的剖面图。
图8是根据一些实施例示出形成芯片封装的工艺阶段的上视图。
图9是根据一些实施例示出形成芯片封装的工艺阶段的上视图。
图10是根据一些实施例示出形成芯片封装的工艺阶段的上视图。
图11是根据一些实施例示出形成芯片封装的工艺阶段的上视图。
图12是根据一些实施例示出芯片封装的剖面图。
图13是根据一些实施例示出芯片封装的剖面图。
附图标记说明：
100～载体基板
102、136、504～互连结构
104、506～绝缘层
106、116、116’、137、508～导电部件
108、108A、108B、134～半导体晶粒、元件
110、122、140、206、540～接合结构
112～中介层基板
114～基座部分
118、120～钝化层
124～内部侧壁
126～凹槽
128、128’、142、208、542～底胶层
130～保护层
131、132、138、502、510～导电元件
133～封装结构
202～粘合层
204～基板
302～开口
702～阻隔元件
H1、H2～高度
W1、W2～距离
具体实施方式
以下提供许多不同的实施例或示范，用于实行本公开的不同部件。以下描述了组件和配置的具体范例，以简化本公开的实施例。当然，这些实施例仅用以例示，并非意图限制本公开的范围。举例而言，在叙述中第一部件形成于第二部件之上，可能包含形成第一和第二部件直接接触的实施例，也可能包含额外的部件形成于第一和第二部件之间，使得第一和第二部件不会直接接触的实施例。另外，本公开的实施例可能在许多范例中重复参考符号及/或字母。这些重复的目的是为了简化和清楚，除非内文中特别说明，其本身并非代表各种实施例及/或所讨论的配置之间有特定的关系。
此外，在以下叙述中可使用空间上相对用语，例如「在……之下」、「在……下方」、「较低的」、「在……上方」、「较高的」和其他类似的用语，以简化附图中一个(些)元件或部件与另一个(些)元件或部件之间的关系的陈述。此空间相对用语除了包含附图所示出的方位，还包含装置在使用或操作中的不同方位。装置亦可转向至其他方位(旋转90度或在其他方位)，且在此使用的空间相对描述亦依转向后的方位相应地解读。
讨论了本公开的一些实施例。在这些实施例中，可在所讨论的阶段之前、过程中、及/或之后提供额外的步骤。可为了不同的实施例而取代或删除所讨论的一些阶段。可增加额外的部件至半导体装置结构中。可为了不同的实施例而取代或删除下文所讨论的一些部件。虽然所讨论的一些实施例以一特定的顺序来执行步骤，但是这些步骤可以其他逻辑性的顺序来执行。
也可包含其他部件或工艺。举例来说，可包含检测结构(testing structure)以支援三维封装(3D packaging)或三维集成电路(3DIC)装置的验证测试(verificationtesting)。此检测结构可包含，例如：形成于重布层中或基板之上的测试垫(test pad)，其可允许使用探针(probe)及/或探针卡(probe card)、以及类似的装置来测试三维封装或三维集成电路装置。可执行此验证测试于中间结构及最终结构。此外，此处所公开的结构与方法可与测试方法结合使用，其可作为芯片良品的中间验证以增加产出并减少成本。
图1A至1K是根据一些实施例示出形成芯片封装的工艺的各种阶段的剖面图。如图1A所示，提供或接收载体基板100。载体基板100可在后续的形成工艺中作为暂时的支撑基板。载体基板100可包含绝缘基板、半导体基板、导电基板、一或多个其他适合的基板、或前述的组合。在一些实施例中，载体基板100为玻璃基板，例如：玻璃晶圆。在一些其他实施例中，载体基板100为半导体基板，例如：硅晶圆。在一些其他实施例中，载体基板100为支撑框(support frame)，例如金属框(metal frame)。
如图1A所示，根据一些实施例，形成互连结构102于载体基板100之上。可使用互连结构102作为用来布线(routing)的重布结构(redistribution structure)。如图1A所示，互连结构102包含了多个绝缘层104及多个导电部件106。在一些实施例中，一些导电部件106在绝缘层104的顶部的顶面曝露出来或者从绝缘层104的顶部的顶面突出。曝露或突出的导电部件106可作为接合垫(bonding pad)，而之后导电凸块(bump)(例如：含锡焊料凸块(tin-containing solder bump))及/或导电柱(例如：铜柱)可形成于此处。
绝缘层104可由或包含一或多种高分子材料所形成。高分子材料可包含聚苯恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide，PI)、一或多种其他适合的高分子材料、或前述的组合。在一些实施例中，高分子材料为感光性(photosensitive)。在一些实施例中，一些或全部的绝缘层104是由或包含除了高分子材料以外的介电材料所形成。介电材料可包含氧化硅、碳化硅、氮化硅、氮氧化硅、一或多种其他适合的材料、或前述的组合。导电部件106可包含提供水平方向电性连接的导电线(conductive line)以及提供垂直方向电性连接的导电通孔(conductive via)。导电部件106可由或包含铜、铝、金、钴、钛、石墨烯、一或多种其他适合的导电材料、或前述的组合所形成。
互连结构102的形成可包含多重沉积或涂布工艺、多重图案化工艺、及/或多重平坦化工艺。可使用沉积或涂布工艺来形成绝缘层及/或导电层。沉积或涂布工艺可包含旋转涂布(spin-on)工艺、电镀(electroplating)工艺、无电镀(electroless plating)工艺、化学气相沉积(Chemical Vapor Deposition，CVD)工艺、物理气相沉积(Physical VaporDeposition，PVD)工艺、一或多种其他可应用的工艺、或前述的组合。可使用图案化工艺来图案化所形成的绝缘层及/或所形成的导电层。图案化工艺可包含光刻(photolithography)工艺、能量束钻孔(energy beam drilling)工艺、蚀刻工艺、机械钻孔工艺、一或多种其他可应用的工艺、或前述的组合。可使用平坦化工艺来提供平坦的顶面给所形成的绝缘层及/或所形成的导电层。平坦化工艺可包含机械研磨(grinding)工艺、化学机械研磨(Chemical Mechanical Polish，CMP)、一或多种其他可应用的工艺、或前述的组合。
然而，可对本公开的实施例进行许多变化及/或改良。在一些其他实施例中，未形成互连结构102。
如图1B所示，根据一些实施例，设置半导体装置(例如：半导体晶粒108)于载体基板100之上。半导体装置可包含一个芯片、多个芯片、或系统集成电路(system-on-integrated-circuit，SoIC)芯片装置。在一些实施例中，设置多个半导体晶粒108于载体基板100之上。半导体晶粒108可具有系统单芯片(system-on-chip，SoC)芯片。在一些其他实施例中，元件108为系统集成电路(system-on-integrated-circuit，SoIC)装置，其包含二或多个具有整合功能的芯片。在这些情况中，使用参考符号「108」来表示半导体装置。在一些实施例中，设置半导体晶粒108于形成于载体基板100之上的互连结构102之上。在一些实施例中，半导体晶粒108通过接合结构100接合至互连结构102的一些导电部件106。
在一些实施例中，接合结构110为导电性。半导体晶粒108中的装置元件与互连结构102的一些导电部件106之间的电性连接，可通过接合结构110来形成。在一些实施例中，接合结构110为或包含焊料凸块，例如：含锡焊料凸块。含锡焊料凸块可还包含铜、银、金、铝、铅、一或多种其他适合的材料、或前述的组合。在一些实施例中，含锡焊料凸块不具有铅。接合结构110的形成可包含一或多道回焊(reflow)工艺及/或一或多道电镀工艺。
在一些实施例中，接合结构110包含金属柱，例如：铜柱。接合结构110的形成可包含电镀(electroplating)工艺或无电镀(electroless plating)工艺。在一些实施例中，可形成含锡焊接材料于接合结构110与互连结构102的一些导电部件106之间。
如图1C所示，根据一些实施例，设置中介层基板112于载体基板100之上。在一些实施例中，设置中介层基板112于形成于载体基板100之上的互连结构102之上。在一些实施例中，中介层基板112通过接合结构122接合至互连结构102的一些导电部件106。接合结构122的材料及形成方法可与接合结构110的材料及形成方法相同或相似。
在一些实施例中，中介层基板112包含基座部分114及多个导电部件116。基座部分114可由或包含一或多种绝缘材料、一或多种半导体材料、一或多种其他适合的材料、或前述的组合所形成。在一些实施例中，基座部分114包含具有填充物分散在其中的高分子材料(例如：环氧基树脂(epoxy-based resin))。在一些实施例中，填充物可包含纤维，例如：玻璃纤维。在一些实施例中，基座部分114为多层绝缘层的堆叠。
在一些实施例中，导电部件116包含导电结构，其穿过基座部分114的相反面。在一些其他实施例中，导电部件116包含多个导电通孔及导电线。在一些其他实施例中，基座部分114是由半导体材料(例如：硅)所形成。在这些情况中，形成绝缘层(未示出)于基座部分114及导电部件116之间。
在一些实施例中，中介层基板112包含形成于基座部分114的相反面之上的钝化层118及120。在一些实施例中，钝化层118及120具有开口，其曝露出一些导电部件116。举例来说，曝露的导电部件116可为导电垫(conductive pad)。在一些实施例中，接合结构122部分覆盖钝化层118。
图8是根据一些实施例示出形成芯片封装的工艺阶段的上视图。在一些实施例中，图8示出图1C所示出的结构的上视图。在一些实施例中，如图1C、图8所示，中介层基板112为具有凹槽126的环形结构。凹槽126穿过中介层基板112的相反面。如图1C、图8所示，中介层基板112具有环形且具有多个内部侧壁124。内部侧壁124围绕凹槽126。内部侧壁124也围绕半导体晶粒108。
在一些实施例中，凹槽126宽于半导体晶粒108。在一些实施例中，凹槽126曝露出互连结构102的一部分。举例来说，绝缘层104的顶面通过凹槽126曝露出来。
如图8所示，半导体晶粒108具有第一边缘(edge)，其距离对应的最靠近的内部侧壁124为距离W1。半导体晶粒108具有第二边缘，其距离所对应的最靠近的内部侧壁124为距离W2。在一些实施例中，距离W1与W2大致上相同。距离W1可在约20微米(μm)至约400微米(μm)的范围。在一些其他实施例中，距离W1可在约400微米(μm)至约1500微米(μm)的范围。在一些其他实施例中，距离W1与W2彼此不相同。
在一些实施例中，如图8所示，凹槽126的上视图具有矩形。在一些其他实施例中，凹槽126的上视图具有除了矩形以外的其他形状。凹槽126的上视图的形状可包含方形、椭圆形、圆形、或其他适合的形状。
在一些实施例中，半导体晶粒108高于中介层基板112。半导体晶粒108的顶面设置在高于中介层基板112的顶面的高度。在一些其他实施例中，半导体晶粒108等高于中介层基板112。半导体晶粒108的顶面设置在与中介层基板112的顶面相同的高度。
可对本公开的实施例进行许多变化及/或改良。虽然在处理半导体晶粒108之后设置中介层基板112于互连结构102之上，但本公开的实施例并不限定于此。在一些其他实施例中，在设置半导体晶粒108之前设置中介层基板112于互连结构102之上。举例来说，中介层基板具有先设置的多个凹槽。然后设置半导体晶粒于互连结构之上。可挑拣及放置每一个半导体晶粒至凹槽所围绕的互连结构的对应区之上。
如图1D所示，根据一些实施例，形成底胶(underfill)层128在半导体晶粒108与互连结构102之间。底胶层128围绕且保护接合结构110。在一些实施例中，底胶层128与接合结构110直接接触。在一些实施例中，底胶层128侧向(laterally)延伸至接合结构122。在一些实施例中，底胶层128也围绕并保护结合结构122。在一些实施例中，底胶层128直接接触接合结构122。
在一些实施例中，底胶层128是由或包含高分子材料所形成。底胶层128可包含环氧基树脂(epoxy-based resin)。在一些实施例中，底胶层128包含填充物分散在环氧基树脂(epoxy-based resin)之中。在一些实施例中，底胶层128较软于中介层基板112的基座部分114。在一些实施例中，基座部分114的填充物浓度较大于底胶层128的填充物浓度。在一些实施例中，基座部分114中每一填充物较长于底胶层128中每一填充物。举例来说，基座部分114中的填充物为纤维(fiber)，而底胶层128中的填充物为颗粒(particle)。在一些实施例中，底胶层128的形成包含射出(injecting)工艺、旋涂工艺、灌胶(dispensing)工艺、薄膜层合(film lamination)工艺、涂敷工艺(application process)、一或多种其他可应用的工艺、或前述的组合。在一些实施例中，在底胶层128的形成过程中使用热固化工艺(thermal curing process)。
如图1E所示，根据一些实施例，形成保护层130于图1D所示的结构之上。在一些实施例中，保护层130延伸至凹槽126中以围绕并保护半导体晶粒108。在一些实施例中，保护层130与半导体晶粒108直接接触。在一些实施例中，保护层130与中介层基板112直接接触。在一些实施例中，保护层130是由或包含成型复合材料(molding compound material)所形成。成型复合材料可包含高分子材料，例如：具有填充物分散在其中的环氧基树脂。在一些实施例中，保护层130较软于中介层基板112的基座部分114。在一些实施例中，基座部分114的填充物浓度较大于保护层130的填充物浓度。在一些实施例中，基座部分114中每一填充物较长于保护层130中每一填充物。举例来说，基座部分114中的填充物为纤维(fiber)，而保护层130中的填充物为颗粒(particle)。
在一些实施例中，应用液态成型复合材料于中介层基板112及半导体晶粒108之上。液态成型复合材料可流进凹槽126内，以封装(encapsulate)半导体晶粒108。之后使用热工艺以固化此液态成型复合材料并且将其转换为保护层130。
如图1F所示，根据一些实施例，薄化保护层130以曝露出导电部件116。在一些实施例中，在薄化保护层130之后也会曝露出钝化层120。可使用机械研磨工艺来薄化保护层130。在一些实施例中，使用曝露的成型工艺(molding process)或灌胶工艺(dispensingprocess)来形成保护层130。在曝露的成型工艺中，在射出成型复合材料以形成保护层130的过程中通过模具(mold)来保护导电部件116。保护层130不会覆盖导电部件116。在这些情况中，因为导电部件116已经曝露出，可不执行薄化工艺。
然后，如图1F所示，根据一些实施例，形成导电元件131于中介层基板112的导电部件116之上。在一些实施例中，导电元件131为焊料凸块。在一些实施例中，导电元件131为或包含含锡焊料凸块。含锡焊料凸块可还包含铜、银、金、铝、铅、一或多种其他适合的材料、或前述的组合。在一些实施例中，含锡焊料凸块不具有铅。在一些实施例中，导电元件131可包含一或多道回焊(reflow)工艺及/或一或多道电镀工艺。
可对本公开的实施例进行许多变化及/或改良。在一些其他实施例中，如图1E所示的保护层130并未薄化而曝露导电部件116。在一些实施例中，之后在保护层130中形成开口以曝露导电部件116。然后，形成导电元件131于曝露的导电部件116之上。导电元件131可完全在形成于保护层130中的开口中。在这些情况中，导电元件131的顶面低于保护层130的顶面。在一些其他实施例中，每一导电元件131具有大于形成于保护层130中的开口深度的高度。在这些情况中，导电元件131从保护层130的顶面突出。
可对本公开的实施例进行许多变化及/或改良。在一些其他实施例中，在设置中介层基板112于互连结构102之上之前形成导电元件131。
如图1G所示，根据一些实施例，由上朝下倒装图1F中所示的结构，然后移除载体基板100。在一些实施例中，在移除载体基板100之前，由上朝下倒装图1F中所示的结构至第二载体基板(未示出)之上。第二载体基板可为承载带框(carrier tape frame)。在一些实施例中，在移除载体基板100之后曝露出中介层基板102的一些导电部件106。在一些实施例中，使用光照射(light irradiation)工艺、研磨工艺、热工艺、一或多种其他可应用的工艺、或前述的组合来移除载体基板100。举例来说，在经过以适合的光线光照后，分离在载体基板100与互连结构102之间的粘合层(未示出)。因此，移除了载体基板100。
如图1H所示，根据一些实施例，形成导电元件132于互连结构102的曝露的导电部件106之上。在一些实施例中，导电元件132为焊料凸块。导电元件132的材料及形成方法可与导电元件131或接合结构122的材料及形成方法相同或相似。
如图1I所示，根据一些实施例，由上朝下倒装图1H所示的结构以接合至封装结构133。在一些实施例中，在接合至封装结构133之前，切开图1I所示的结构以形成多个独立的封装结构。
封装结构133可包含元件134、互连结构136、及导电元件138。在一些实施例中，元件134为半导体晶粒。半导体晶粒可包含多个动态随机存取存储器(dynamic randomaccess memory，DRAM)装置、快闪存储器(flash memory)装置、固态随机存取存储器(static random access memory，SRAM)装置、被动装置、无线电频率模块(radiofrequency module)装置、其他适合的装置、或前述的组合，在一些实施例中，元件134包含半导体晶粒及封装半导体晶粒的封装层。半导体晶粒可包含多个动态随机存取存储器(DRAM)装置、快闪存储器(flash memory)装置、固态随机存取存储器(SRAM)装置、被动装置、无线电频率模块(radio frequency module)装置、其他适合的装置、或前述的组合。
互连结构136的结构、材料、及形成方法可与互连结构102的之结构、材料、及形成方法相同或相似。举例来说，互连结构136包含了多个导电线及/或导电通孔。导电元件138的材料及形成方法可与导电元件132的材料及形成方法相同或相似。
如图1J所示，根据一些实施例，堆叠封装结构133并接合至中介层基板112之上。在一些实施例中，封装结构133延伸越过半导体晶粒108。在一些实施例中，封装结构133延伸越过填充凹槽126的保护层130。
在一些实施例中，通过接合结构140接合封装结构133与中介层基板112。可使用一或多道回焊(reflow)来形成接合结构140。在上述所提的回焊(reflow)工艺中，可将导电元件131与138(如图1I所示)熔融在一起以形成接合结构140。每一接合结构140可包含焊接材料部分以及接合垫。可形成接合垫于焊接材料部分与互连结构136之间。
可对本公开的实施例进行许多变化及/或改良。在一些其他实施例中，未堆叠封装结构133于中介层基板112之上。在一些其他实施例中，未提供封装结构133。
如图1K所示，形成底胶层142以环绕并保护接合结构140。底胶层142的材料及形成方法可与底胶层128的材料及形成方法相同或相似。
可对本公开的实施例进行许多变化及/或改良。在一些其他实施例中，未形成底胶层128。
可对本公开的实施例进行许多变化及/或改良。在一些其他实施例中，未形成底胶层128、保护层130、以及底胶层142。
可对本公开的实施例进行许多变化及/或改良。在一些其他实施例中，在接合封装结构133至中介层基板112之后，形成保护材料层。保护材料层围绕接合结构140、半导体晶粒108、及接合结构122及110。在一些实施例中，形成具有围绕接合结构及半导体晶粒的部分的保护材料层于单一的形成工艺中。围绕接合结构的保护材料层的部分可作为底胶层。围绕半导体晶粒的保护材料层的部分可作为保护层。
图2A至2D是根据一些实施例示出形成芯片封装的工艺的各种阶段的剖面图。如图2A所示，接受或形成类似于图1C所示的结构。在一些实施例中，半导体晶粒108高于中介层基板112。在一些实施例中，设置半导体晶粒108的顶面于高于中介层基板112的顶面的高度。
如图2A所示，中介层基板112具有高度H1，而半导体晶粒具有高度H2。在一些实施例中，高度H2大于高度H1。中介层基板112的高度H1可在20微米(μm)至约300微米(μm)的范围。
如图2B所示，根据一些实施例，形成底胶层128以保护接合结构110及122。图2B所示的底胶层128的材料及形成方法可与图1D所示的底胶层128的材料及形成方法相同或相似。在一些实施例中，如图2B所示，底胶层128向上延伸以部分或完全填充由中介层基板112的内部侧壁124所围绕的凹槽126。在这些情况中，底胶层128也可作为保护半导体晶粒108的保护层。在一些实施例中，如图2B所示，半导体晶粒108的顶面高于底胶层128的顶面。
如图2C所示，相似于图1J所示出的实施例，根据一些实施例，堆叠封装结构113并接合至中介层基板112之上。使用接合结构140以实现在封装结构133与中介层基板112之间的物理性(physical)接合及电性连接。通过中介层基板112及互连结构102来建立封装结构133中的装置元件与半导体晶粒108中的装置元件之间的电性连接。
如图2C所示，根据一些实施例，使用粘合层202以增加半导体晶粒108与封装结构133之间的粘着力(adhesion)。粘合层202可为芯片接合膜(die attachment film，DAF)。在一些实施例中，在封装结构133与中介层基板112通过接合结构140接合之前，形成粘合层202于半导体晶粒108之上。在一些其他实施例中，在接合封装结构133与中介层基板112之前，形成粘合层202于封装结构133之上。
可对本公开的实施例进行许多变化及/或改良。在一些其他实施例中，未形成粘合层202。
如图2D所示，根据一些实施例，通过接合结构206接合图2C中所示的结构至基板204。接合结构206的材料及形成方法可与接合结构122的材料及形成方法相同或相似。在一些实施例中，基板204为印刷电路板。在一些实施例中，基板204为半导体基板，其具有导电部件形成于其之上。
在一些实施例中，如图2D所示，形成底胶层208于基板204之上以围绕并保护接合结构206。底胶层208的材料及形成方法可与底胶层128的材料及形成方法相同或相似。在一些实施例中，底胶层208向上延伸以覆盖互连结构102的侧壁。在一些实施例中，底胶层208向上延伸以覆盖底胶层128的侧壁。在一些实施例中，底胶层208向上延伸以部分覆盖中介层基板112的侧壁。
图3A至3E是根据一些实施例示出形成芯片封装的工艺的各种阶段的剖面图。如图3A所示，接收或提供相似于图1E所示的结构。在一些实施例中，半导体晶粒108与中介层基板112等高。然而，本公开的实施例不限定于此。在一些其他实施例中，相似于图2A所示出的实施例，半导体晶粒108高于中介层基板112。在这些情况中，半导体晶粒108的顶面与互连结构102的距离大于中介层基板112的顶面与互连结构102的距离。
然后，如图3A所示，根据一些实施例，形成开口302在保护层130中以部分曝露导电部件116。可使用能量束钻孔(energy beam drilling)工艺、机械钻孔工艺、光刻(photolithography)工艺、蚀刻工艺、一或多种其他可应用的工艺、或前述的组合来形成开口302。
如图3A所示，根据一些实施例，形成导电元件131于中介层基板112的曝露的导电部件116之上。图3A所示的导电元件131的材料及形成方法可与图1F所示的导电元件131的材料及形成方法相同或相似。在一些其他实施例中，设置每一导电元件131于对应的开口302中。在一些其他实施例中，导电元件302的部分从开口302突出(未示出)。在这些情况中，导电元件302的顶面高于保护层130的顶面。
如图3B所示，根据一些实施例，由上朝下倒装图3A中所示的结构，之后移除载体基板100以曝露出一些导电部件106。在一些实施例中，在移除载体基板100之前，由上朝下倒装图3A中所示的结构至第二载体基板(未示出)之上。第二载体基板可为承载带框(carriertape frame)。之后，如图3C所示，根据一些实施例，形成导电元件132于曝露的导电部件106之上。图3C所示的导电元件132的材料及形成方法可与图1H所示的导电元件132的材料及形成方法相同或相似。
如图3D所示，根据一些实施例，相似于图1I所示出的实施例，由上朝下倒装图3C中所示的结构至封装结构133。
如图3E所示，根据一些实施例，相似于图1J所示出的实施例，通过接合结构140接合封装结构133与中介层基板112。之后，相似于图1K所示出的实施例，如图3E所示，根据一些实施例，形成底胶层142。
可对本公开的实施例进行许多变化及/或改良。在一些其他实施例中，未形成保护层130。在一些实施例中，形成底胶层142以保护接合结构140。底胶层142可填充由中介层基板112的内部侧壁124所围绕的凹槽126。因此，底胶层142也可围绕半导体晶粒108并且作为保护层。
图4A至4B是根据一些实施例示出形成芯片封装的工艺的各种阶段的剖面图。如图4A所示，形成相似于图3E所示出的实施例的结构。在一些实施例中，中介层基板112包含形成于基座部分114中的多个导电部件116’。在一些实施例中，每一导电部件116’未穿过基座部分114的相反面。
在一些实施例中，底胶层128与接合结构110直接接触。在一些实施例中，底胶层128未直接接触接合结构122。在一些实施例中，保护层130与接合结构122直接接触。在一些实施例中，保护层130未直接接触接合结构110。
在一些实施例中，半导体晶粒108高于中介层基板112。设置半导体晶粒108的顶面在高于中介层基板112的高度。如图4A所示，封装结构133的互连结构136包含多个导电部件137。电性连接一些导电部件137至接合结构140。
如图4B所示，相似于图2D所示出的实施例，根据一些实施例，通过接合结构206接合图4A中所示的结构至基板204。在一些实施例中，形成底胶层208以保护接合结构206。
图5A至5F是根据一些实施例示出形成芯片封装的工艺的各种阶段的剖面图。如图5A所示，接收或提供相似于图1E中所示的结构。在一些实施例中，半导体晶粒108等高于中介层基板112。然而，本公开的实施例并不限定于此。在一些其他实施例中，相似于图2A所示出的实施例，半导体晶粒108高于中介层基板112。
之后，如图5A所示，根据一些实施例，形成开口于保护层130中以部分曝露导电部件116。相似于开口302，可使用能量束钻孔(energy beam drilling)工艺、机械钻孔工艺、光刻(photolithography)工艺、蚀刻工艺、一或多种其他可应用的工艺、或前述的组合来形成开口。
之后，如图5A所示，根据一些实施例，形成导电元件502于曝露的导电部件116之上以填充形成于保护层130中的开口。在一些实施例中，导电元件502为导电柱。在一些实施例中，导电元件502的顶面与保护层130的顶面大致上为共平面。在一些实施例中，可使用平坦化工艺以确保导电元件502的顶面与保护层130的顶面大致上为共平面。平坦化工艺可包含机械研磨工艺、化学机械研磨(Chemical Mechanical Polish，CMP)、一或多种其他可应用的工艺、或前述的组合。
导电元件502可由或包含铜、金、钴、铝、铂、石墨烯、一或多种其他适合的导电材料、或前述的组合所形成。可使用电镀(electroplating)工艺、无电镀(electrolessplating)工艺、化学气相沉积(CVD)工艺、物理气相沉积(PVD)工艺、印刷(printing)工艺、一或多种其他可应用的工艺、或前述的组合来形成导电元件502。
如图5B所示，根据一些实施例，形成互连结构504于保护层130及导电元件502之上。互连结构504可包含绝缘层506及多个导电部件508。绝缘层506可包含多层的子层(sub-layer)。互连结构504的材料及形成方法可与互连结构102的材料及形成方法相同或相似。
之后，如图5B所示，根据一些实施例，形成导电元件510于互连结构504的一些导电部件508之上。导电元件510的材料及形成方法可与图1F中所示出的导电元件131的材料及形成方法相同或相似。在一些实施例中，互连结构504的底面的大部分是与相同材料的膜层(即保护层130)直接接触。在一些实施例中，保护层130及绝缘层506两者皆由相同或相似的高分子材料所形成。因此，保护层130及绝缘层506具有相似的热膨胀系数(thermalexpansion coefficient)。因此，互连结构504在后续的热工艺过程中可承受较少的热应力(thermal stress)。可确保互连结构504的品质与可靠度。
如图5C所示，根据一些实施例，由上朝下倒装图5B中所示的结构，并且移除载体基板100以曝露出一些导电部件106。在一些实施例中，在移除载体基板100之前，由上朝下倒装图5B中所示的结构至第二载体基板(未示出)之上。第二载体基板可为承载带框(carriertape frame)。
之后，如图5D所示，根据一些实施例，形成导电元件132于曝露的导电部件106之上。图5D所示的导电元件132的材料及形成方法可与图1H所示的导电元件132的材料及形成方法相同或相似。
如图5E所示，相似于图1I所示出的实施例，根据一些实施例，由上朝下倒装图5D中所示的结构以接合至封装结构133之上。
如图5F所示，相似于图1J所示出的实施例，根据一些实施例，通过接合结构540接合封装结构133与中介层基板112。在一些实施例中，可使用回焊(reflow)工艺将对准的导电元件138及510熔融在一起。因此，形成了接合结构540。接合结构540的材料及形成方法可与图1J所示的接合结构140的材料及形成方法相同或相似。
之后，相似于图1K所示出的实施例，如图5F所示，根据一些实施例，形成底胶层542以保护接合结构540。底胶层542的材料及形成方法可与图1K所示的底胶层142的材料及形成方法相同或相似。
图6A至6B是根据一些实施例示出形成芯片封装的工艺的各种阶段的剖面图。如图6A所示，形成相似于图5F中所示出的实施例的结构。在一些实施例中，中介层基板112包含形成于基座部分114中的多个导电部件116’。在一些实施例中，中介层基板112也包含导电元件502。导电元件502可为导电通孔。在一些实施例中，每一导电部件116’未穿透基座部分114的相反面。
在一些实施例中，底胶层128与接合结构110直接接触。在一些实施例中，底胶层128未直接接触接合结构122。在一些实施例中，保护层130与接合结构122直接接触。在一些实施例中，保护层130未直接接触接合结构110。
在一些实施例中，半导体晶粒108高于中介层基板112。设置半导体晶粒108的顶面在高于中介层基板112的高度。如图6A所示，封装结构133的互连结构136包含多个导电部件137。电性连接一些导电部件137至接合结构540。
在一些实施例中，保护层130覆盖中介层基板112与半导体晶粒108的顶面，并且形成互连结构504于保护层130之上。避免互连结构504与半导体晶粒108及保护层130之间可能具有较高应力的界面直接接触。因此，互连结构504可具有优选的可靠度。避免导电部件506的布线(routing)受到限制。
在一些其他实施例中，互连结构与半导体晶粒及保护层之间的界面直接接触。在一些情况中，互连结构的部分延伸越过此界面可能会承受较高的应力。可能需要远离这些高应力部分(即排除区(kick-out zone))来形成导电部件，以确保可靠的电性连接。导电部件的布线(routing)因而受到限制。
如图6B所示，相似于图2D所示出的实施例，根据一些实施例通过接合结构206接合图6A中所示的结构至基板204。在一些实施例中，形成底胶层208以保护接合结构206。
第7A至7I图是根据一些实施例示出形成芯片封装的工艺的各种阶段的剖面图。如第7A所示，接收或形成相似与图1A中所示的结构。
如图7B所示，根据一些实施例，形成阻隔元件702于互连结构102之上。在一些实施例中，阻隔元件702为环型(ring)结构，其连续围绕接合结构110及半导体晶粒108。阻隔元件702可由绝缘材料、导电材料、半导体材料、或前述的组合所形成。在一些实施例中，阻隔元件702是由或包含感光高分子材料所形成。在一些实施例中，形成感光高分子材料于互连结构102之上。之后，使用光刻(photolithography)工艺以图案化此感光高分子材料层。因此，形成了具有所期望的图案的阻隔元件702。
之后，相似于图1B所示出的实施例，如图7B所示，是根据一些实施例挑拣及放置半导体晶粒108于互连结构102之上。在一些实施例中，通过接合结构110接合半导体晶粒108至互连结构102。
如图7C所示，根据一些实施例，形成底胶层128’于半导体晶粒108与互连结构102之间以保护接合结构110。底胶层128’的材料及形成方法可与图1D所示的底胶层128的材料及形成方法相同或相似。在一些实施例中，因阻隔元件702的缘故，限制了使用于形成底胶层128’的材料(例如：液态高分子材料)在所围绕的区域中。避免一些导电部件106被底胶层128’覆盖，其有利于后续的接合工艺。
如图7D所示，相似于图1C所示出的实施例，根据一些实施例，设置中介层基板112于互连结构102之上。通过接合结构122接合中介层基板112至互连结构102。因为通过阻隔元件702来阻隔底胶层128’而不会覆盖曝露的导电部件106，所以更容易执行接合结构122的形成。
图9是根据一些实施例示出形成芯片封装的工艺阶段的上视图。在一些实施例中，图9示出图7D中所示的结构的上视图。中介层基板112的内部侧壁124围绕凹槽126。凹槽126围绕半导体晶粒108。凹槽126也曝露了底胶层128’、阻隔元件702、及互连结构102。如图9所示，阻隔元件702为环型结构，其围绕半导体晶粒108。将底胶层128’限制在阻隔元件702所围绕的区域中。也可形成阻隔元件702于第1、2、3、4、5、及/或6图所示出的实施例中。
如图7E所示，相似于图1E所示出的实施例，根据一些实施例，形成保护层130。之后，相似于图1F所示出的实施例，如图7F所示，根据一些实施例，薄化保护层130以曝露出导电部件116。在一些其他实施例中，使用曝露的成型工艺(molding process)或灌胶工艺(dispensing process)来形成保护层130。在曝露的成型工艺中，在射出成型复合材料以形成保护层130的过程中通过模具(mold)来保护导电部件116。保护层130不会覆盖导电部件116。在这些情况中，因为已经曝露出导电部件116，可不需要薄化工艺。接着形成导电元件131于曝露的导电部件116之上。
如图7G所示，相似于第1G-1H图所示出的实施例，根据一些实施例，移除载体基板100，并且形成导电元件132。
如图7H所示，相似于第1I及1J图所示出的实施例，根据一些实施例，通过接合结构140接合封装结构133至中介层基板112。在一些实施例中，相似于图2C所示出的实施例，形成粘合层202以改善半导体晶粒108与封装结构133之间的粘着力(adhesion)。在一些实施例中，粘合层202是由或包含一或多种具有高热传导性(thermal conductivity)的材料所形成。在一些实施例中，具有高热传导性的粘合层202具有与半导体晶粒108的顶面相同大小的面积。因此，可更有效率的散出在半导体晶粒108中的装置元件的运行过程中所产生的热。在一些实施例中，具有高热传导性的粘合层202的面积大于半导体晶粒108的顶面。因此，可确保半导体晶粒108的顶面被粘合层202完全地覆盖。
然而，本公开的实施例并不限定于此，在一些实施例中，未形成粘合层202。
如图7I所示，相似于图1K所示出的实施例，形成底胶层142以保护接合结构140。
可对本公开的实施例进行许多变化及/或改良。在一些实施例中，可挑拣及放置多个半导体晶粒至由相同的凹槽126曝露出的导电部件106之上。
图10是根据一些实施例示出形成芯片封装的工艺阶段的上视图。在一些实施例中，图10示出在第1、2、3、4、5、6、及/或7图中所示出的实施例的上视图。在一些实施例中，二或多个半导体晶粒(例如：半导体晶粒108A及108B)是由中介层基板112的内部侧壁所围绕。在一些其他实施例中，元件108A及108B之一或每一个为半导体装置，其包含一个芯片、多个芯片、或系统集成电路(system-on-integrated-circuit，SoIC)芯片装置。因此，参考符号「108A及108B」也可用来表示半导体装置。
可对本公开的实施例进行许多变化及/或改良。图11是根据一些实施例示出形成芯片封装的工艺阶段的上视图。在一些实施例中，中介层基板112的内部侧壁124围绕一椭圆区域。在一些其他实施例中，由中介层基板112的内部侧壁124所围绕的区域可为方形、圆形、或其他类似的形状。在一些实施例中，图11示出在第1、2、3、4、5、6、及/或7图中所示出的实施例的上视图。
可对本公开的实施例进行许多变化及/或改良。举例来说，中介层基板112的内部侧壁124可为倾斜(inclined)的侧壁。
图12是根据一些实施例示出芯片封装的剖面图。如图12所示，形成相似于图4B中所示的结构。在一些实施例中，如图12所示，内部侧壁124为倾斜的侧壁。凹槽126沿着从中介层基板112的底部朝向顶部的方向变宽。在第1至7图中所示出的每一实施例的内部侧壁124可改良为倾斜的侧壁。
图13是根据一些实施例示出芯片封装的剖面图。如图13所示，形成相似于图4B中所示的结构。在一些实施例中，如图13所示，内部侧壁124为倾斜的侧壁。凹槽126沿着从中介层基板112的底部朝向顶部的方向变窄。
本公开的实施例形成具有中介层基板的芯片封装。接合中介层基板及半导体晶粒至重布结构(redistribution structure)之上。中介层基板为一环型结构，其围绕半导体晶粒。半导体晶粒等高于或高于中介层基板。未堆叠半导体晶粒于中介层基板之上，并且半导体晶粒被中介层基板部分围绕。减少芯片封装的总高度，其可利于后续与其他封装结构的接合。
根据一些实施例提供一种芯片封装的形成方法。此方法包含：设置半导体晶粒于载体基板之上。此方法也包含设置中介层基板于此载体基板之上。此中介层基板具有凹槽，此凹槽穿过该中介层基板的相反面。此中介层基板具有围绕半导体晶粒的内部侧壁，并且此半导体晶粒等高于或高于此中介层基板。此方法还包含在中介层基板的凹槽中形成保护层，以围绕半导体晶粒。另外，此方法包含移除载体基板以及堆叠封装结构于该中介层基板之上。在一些实施例中，其中此保护层覆盖此中介层基板以及此半导体晶粒，且此方法还包含：形成开口于此保护层中，以曝露出此中介层基板的导电部件；以及形成导电元件于此中介层基板的此导电部件之上。在一些实施例中，此方法还包含：在设置此半导体晶粒以及此中介层基板于此载体基板之上之前，形成互连结构于此载体基板之上。在一些实施例中，其中此保护层过度填充此凹槽以覆盖此半导体晶粒，且此方法还包含：在堆叠此封装结构于此中介层基板之上之前，形成第二互连结构于此保护层之上；以及接合此封装结构至此第二互连结构。在一些实施例中，其中此第二互连结构未直接接触在此半导体晶粒与此保护层之间的界面。在一些实施例中，其中在设置此中介层基板于此互连结构之上之前，设置此半导体晶粒于此互连结构之上。在一些实施例中，此方法还包含：在移除此载体基板之后，形成复数导电凸块于此互连结构的表面之上，其中此互连结构的此表面起初(originally)面向此载体基板。在一些实施例中，其中此封装结构延伸越过此半导体晶粒。在一些实施例中，此方法还包含设置第二半导体晶粒于此载体基板之上，其中此中介层基板的内部侧壁围绕此第二半导体晶粒。在一些实施例中，其中此中介层基板为印刷电路板。
根据一些实施例提供一种芯片封装的形成方法。此方法包含：形成第一重布结构于载体基板之上，并且接合一半导体晶粒与此第一重布结构。此方法也包含接合中介层基板与此第一重布结构。此中介层基板具有围绕此半导体晶粒的环型结构，并且此半导体晶粒等高于或高于此中介层基板。此方法还包含形成保护层以围绕此半导体晶粒。此保护层的一部分在此中介层基板与此半导体晶粒之间。另外，此方法包含移除此载体基板，以及接合封装结构于此中介层基板之上。此半导体晶粒在此封装结构与此第一重布结构之间。在一些实施例中，此方法还包含：在移除此载体基板之后且在接合此封装结构于此中介层基板之上之前，形成复数导电凸块于此第一重布结构之上，其中此第一重布结构在此些导电凸块与此半导体晶粒之间。在一些实施例中，此方法还包含：在接合此封装结构于此中介层基板之上之前，薄化此保护层以曝露此中介层基板。在一些实施例中，此方法还包含：形成导电元件于此保护层中，其中此导电元件电性连接至此中介层基板的导电部件。在一些实施例中，此方法还包含：形成第二重布结构于此保护层之上，其中此保护层的一部分在此第二重布结构与此半导体晶粒之间。
根据一些实施例提供芯片封装。此芯片封装包含：第一重布结构，以及接合于此第一重布结构之上的半导体装置。此芯片封装也包含接合于此第一重布结构之上的中介层基板。此中介层基板具有围绕此半导体装置的内部侧壁，并且此半导体装置等高于或高于此中介层基板。此芯片封装还包含围绕此半导体装置的保护层。另外，此芯片封装包含第二重布结构于此保护层之上。此第二重布结构的第一导电部件电性连接至此中介层基板的第二导电部件。在一些实施例中，其中此保护层的一部分位于此第二重布结构与此半导体装置之间。在一些实施例中，此芯片封装还包含：第二半导体装置，接合于此第一重布结构之上，其中此中介层基板的内部侧壁围绕此第二半导体装置。在一些实施例中，此芯片封装还包含：封装结构，接合至此第二重布结构。在一些实施例中，其中此中介层结构的内部侧壁为倾斜的侧壁。
根据一些实施例提供芯片封装。此芯片封装包含：第一重布结构，以及接合于此第一重布结构之上的半导体装置。芯片封装也包含接合于此第一重布结构之上的中介层基板。此中介层基板具有围绕此半导体装置的内部侧壁，并且此半导体装置等高于或高于此中介层基板。此芯片封装还包含围绕此半导体装置及在保护层之上的第二重布结构的保护层。此第二重布结构的第一导电部件电性连接至此中介层基板的第二导电部件。
前述概述了一些实施例的部件，使得本公开所属技术领域中技术人员可以更加理解本公开实施例的观点。本公开所属技术领域中技术人员应可理解，他们可以轻易使用本公开实施例作为基础，设计或修改其他的工艺或是结构，以达到与在此介绍的实施例相同的目的及/或优点。本公开所属技术领域中技术人员也应理解，此类等效的结构并不悖离本公开实施例的构思与范围，并且在不悖离本公开实施例的构思与范围的情况下，在此可以做各种的改变、取代和替换。因此，本公开的保护范围当视权利要求所界定为准。

Claims (20)

1.一种芯片封装的形成方法，包括：
设置一半导体晶粒于一载体基板之上；
设置一中介层基板于该载体基板之上，其中该中介层基板具有一凹槽，该凹槽穿过该中介层基板的相反面，该中介层基板具有围绕该半导体晶粒的内部侧壁，并且该半导体晶粒等高于或高于该中介层基板；
在该中介层基板的该凹槽中形成一保护层，以围绕该半导体晶粒；
移除该载体基板；
堆叠一封装结构于该中介层基板之上；以及
形成一粘合层于该半导体晶粒以及该封装结构之间，其中在该粘合层的法线方向上，该封装结构比该粘合层宽。
2.如权利要求1所述的芯片封装的形成方法，
其中该保护层覆盖该中介层基板以及该半导体晶粒，且该方法还包括：
形成一开口于该保护层中，以曝露出该中介层基板的一导电部件；以及
形成一导电元件于该中介层基板的该导电部件之上。
3.如权利要求1所述的芯片封装的形成方法，
还包括：在设置该半导体晶粒以及该中介层基板于该载体基板之上之前，形成一互连结构于该载体基板之上。
4.如权利要求3所述的芯片封装的形成方法，其中该保护层过度填充该凹槽以覆盖该半导体晶粒，且该方法还包括：
在堆叠该封装结构于该中介层基板之上之前，形成一第二互连结构于该保护层之上；以及
接合该封装结构至该第二互连结构。
5.如权利要求4所述的芯片封装的形成方法，其中该第二互连结构未直接接触在该半导体晶粒与该保护层之间的一界面。
6.如权利要求3所述的芯片封装的形成方法，其中在设置该中介层基板于该互连结构之上之前，设置该半导体晶粒于该互连结构之上。
7.如权利要求3所述的芯片封装的形成方法，还包括：在移除该载体基板之后，形成复数导电凸块于该互连结构的一表面之上，其中该互连结构的该表面起初(originally)面向该载体基板。
8.如权利要求1所述的芯片封装的形成方法，其中该封装结构延伸越过该半导体晶粒。
9.如权利要求1所述的芯片封装的形成方法，还包括设置一第二半导体晶粒于该载体基板之上，其中该中介层基板的内部侧壁围绕该第二半导体晶粒。
10.如权利要求1所述的芯片封装的形成方法，其中该中介层基板为一印刷电路板。
11.一种芯片封装的形成方法，包括：
形成一第一重布结构于一载体基板之上；
接合一半导体晶粒与该第一重布结构；
接合一中介层基板与该第一重布结构，其中该中介层基板具有围绕该半导体晶粒的一环型结构，并且该半导体晶粒等高于或高于该中介层基板；
形成一保护层以围绕该半导体晶粒，其中该保护层的一部分在该中介层基板与该半导体晶粒之间；
移除该载体基板；
接合一封装结构于该中介层基板之上，其中该半导体晶粒在该封装结构与该第一重布结构之间；以及
形成一粘合层于该半导体晶粒以及该封装结构之间，其中在该粘合层的法线方向上，该封装结构比该粘合层宽。
12.如权利要求11所述的芯片封装的形成方法，还包括：在移除该载体基板之后且在接合该封装结构于该中介层基板之上之前，形成复数导电凸块于该第一重布结构之上，其中该第一重布结构在该些导电凸块与该半导体晶粒之间。
13.如权利要求11所述的芯片封装的形成方法，还包括：在接合该封装结构于该中介层基板之上之前，薄化该保护层以曝露该中介层基板。
14.如权利要求11所述的芯片封装的形成方法，还包括：形成一导电元件于该保护层中，其中该导电元件电性连接至该中介层基板的一导电部件。
15.如权利要求11所述的芯片封装的形成方法，还包括：形成一第二重布结构于该保护层之上，其中该保护层的一部分在该第二重布结构与该半导体晶粒之间。
16.一种芯片封装，包括：
一第一重布结构；
一半导体装置，接合于该第一重布结构之上；
一中介层基板，接合于该第一重布结构之上，其中该中介层基板具有围绕该半导体装置的内部侧壁，并且该半导体装置等高于或高于该中介层基板；
一保护层，围绕该半导体装置；
一第二重布结构，于该保护层之上，其中该第二重布结构的一第一导电部件电性连接至该中介层基板的一第二导电部件；
一封装结构，位于该中介层基板之上；以及
一粘合层，位于该半导体装置以及该封装结构之间，其中在该粘合层的法线方向上，该封装结构比该粘合层宽。
17.如权利要求16所述的芯片封装，其中该保护层的一部分位于该第二重布结构与该半导体装置之间。
18.如权利要求16所述的芯片封装，还包括：一第二半导体装置，接合于该第一重布结构之上，其中该中介层基板的内部侧壁围绕该第二半导体装置。
19.如权利要求16所述的芯片封装，其中该封装结构接合至该第二重布结构。
20.如权利要求16所述的芯片封装，其中该中介层基板的内部侧壁为倾斜的侧壁。
CN202111060983.4A 2017-10-31 2018-07-05 芯片封装及其形成方法 Pending CN113782455A (zh)

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