CN112420684A - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
CN112420684A
CN112420684A CN202010848754.8A CN202010848754A CN112420684A CN 112420684 A CN112420684 A CN 112420684A CN 202010848754 A CN202010848754 A CN 202010848754A CN 112420684 A CN112420684 A CN 112420684A
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China
Prior art keywords
interposer
layer
redistribution structure
conductive
molding compound
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Pending
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CN202010848754.8A
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English (en)
Inventor
张进传
卢思维
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112420684A publication Critical patent/CN112420684A/zh
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    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

本公开提供一种封装结构，包括一第一重分布结构和在第一重分布结构上的一中介层。封装结构还包括围绕中介层的一模塑料层，以及在中介层上方的一第二重分布结构。模塑料层在第一重分布结构和第二重分布结构之间。封装结构还包括在第二重分布结构上方的一第一半导体裸片和一第二半导体裸片。

Description

封装结构
技术领域
本公开实施例涉及一种封装结构及其形成方法。
背景技术
在各种电子应用，例如个人电脑、手机、数字相机和其他电子装置中使用了半导体装置。通常是通过在半导体基板上依序沉积绝缘层或介电层、导电层和半导体层，并使用光刻工艺和蚀刻工艺图案化各种材料层，以在材料层上形成电路部件和元件来制造半导体装置。
半导体工业通过不断减小最小特征尺寸来继续提高各种电子部件(例如，晶体管，二极管，电阻器，电容器等)的整合密度，这允许将更多的部件整合到给定区域中。在某些应用中，这些较小的电子组件还使用较小的封装，而这封装是使用较小的面积或较低的高度。
一些新式封装技术已开展以进一步提高半导体裸片的密度和功能。例如，已经发展了三维集成电路(3D-IC)封装。这些用于半导体裸片的较新类型的封装技术面临制造挑战，且它们并未在所有方面均完全令人满意。
发明内容
本公开实施例的目的在于提供一种封装结构，以解决上述至少一个问题。
根据一些实施例，提供了一种封装结构。封装结构包括一第一重分布结构和在第一重分布结构上的一中介层。封装结构还包括围绕中介层的一模塑料层，以及中介层上的一第二重分布结构。模塑料层在第一重分布结构和第二重分布结构之间。封装结构还包括在第二重分布结构上方的一第一半导体裸片和第二半导体裸片。
根据一些实施例，提供了一种封装结构。封装结构包括一第一重分布结构和在第一重分布结构上的一中介层。中介层包含在一基板上方的一导电垫和在导电垫上方的一导电柱。封装结构还包括中介层上的一第二重分布结构。封装结构还包括一第一半导体裸片、一第二半导体裸片以及在第二重分布结构上方的一表面安装器件(surface-mountdevice，SMD)。第一半导体裸片通过第二重分布结构电性连接到导电柱。
根据一些实施例，提供了封装结构的形成方法。形成方法包括形成围绕一第一中介层的一第一模塑料层；在第一中介层的一第一侧和第一模塑料层上形成一第一重分布结构；通过多个第一连接件将一第一半导体裸片和一第二半导体裸片接合到第一重分布结构；在与第一中介层的第一侧相对的第一中介层的一第二侧上形成一第二重分布结构。
附图说明
以下将配合所附附图详述本公开的实施例。应注意的是，依据在业界的标准做法，多种特征并未按照比例示出且仅用以说明例示。事实上，可能任意地放大或缩小元件的尺寸，以清楚地表现出本公开的特征。
图1A至图1L是根据本公开一些实施例的形成封装结构的工艺的各个阶段的剖面图。
图2A至图2D是根据本公开一些实施例的形成封装结构的工艺的各个阶段的剖面图。
附图标记如下：
100,200:封装结构
101:基板
103:通孔
105:导电垫
107:钝化层
108:中介层晶片
109:导电柱
111:聚合物层
113,115:中介层
113a:第一表面
113b:第二表面
115a:第一表面
115b:第二表面
121:第一载体基板
123:粘合层
125:模塑料层
127:介电结构
129:导电结构
129a:堆叠通孔
129b:导线
131:重分布结构
133,135:连接件
137a:第一半导体裸片
137b:第二半导体裸片
139:表面安装器件
141:底部填充层
143:模塑料层
151:第二载体基板
153:黏合层
157:介电结构
159:导电结构
161:重分布结构
161a:第一表面
161b:第二表面
163:凸块下金属结构
165,167:连接件
169:电容器
H1,H2:高度
I-I’、II-II’:划线
L1,L2:长度
T1,T2,T3,T4:厚度
具体实施方式
下文提供多个不同的实施例或示范例，以实现本发明的不同特征。为了能简化本案说明书，下文将叙述元件与配置的多个具体例子。当然，这些例子仅为示范例而并不被限制于此。举例来说，在说明书中，第一特征在第二特征上方或在第二特征之上的构成可包括第一与第二特征是以直接接触方式来形成的实施例，也可包括在第一与第二特征之间形成其他特征而使第一与第二特征无法直接接触的实施例。此外，本说明书在不同示范例中可能重复使用参考数字以及/或字母。此重复是为了说明书的简洁与清楚，其本身并非指定在所讨论的不同实施例以及/或配置之间的关系。
此外，空间相对术语(Spatially Relative Terms)，例如“向...下面”、“在...之下”、“低于”、“在...之上”、“上面的”等等类似术语，在这里是出于描述简便而用来描述一元件或特征相对于其它元件或特征的如图中所示的关系。装置可定向在其他方位(旋转90度或在其它方位)，因此这里使用的空间相对描述词据此解释。
本公开描述了一些实施例。在这些实施例中描述的阶段之前、之中和/或之后提供附加操作。对于不同的实施例，可替换或减少所描述的某些阶段。可将附加特征加入到半导体器件结构中。对于不同的实施例，以下描述的一些特征可被替换或消除。尽管以特定顺序执行的操作讨论了一些实施例，但是可以以另一种逻辑顺序执行这些操作。
本公开的实施例可以涉及3D封装或3D-IC设备。也可以包括其他特征和过程。例如，可以包括测试结构以帮助对3D封装或3D-IC设备进行验证测试。测试结构可以包括例如形成在重分布层中或基板上的测试垫，此测试垫允许测试3D封装或3D-IC，使用探针和/或探针卡等。验证测试可以在中间结构以及最终结构上执行。另外，本文公开的结构和方法可以与结合了已知良好裸片的中间验证的测试方法结合使用，以增加产量并降低成本。
本公开的实施例提供了封装结构及其形成方法。封装结构可以包括第一重分布结构和在第一重分布结构上的中介层。封装结构还可包括围绕中介层的模塑料层，以及中介层上方的第二重分布结构。通过将第一重分布结构和第二重分布结构设置在中介层的两侧，可以将其他电子组件(例如，表面安装器件)整合到封装结构中，而无需任何其他基板，例如印刷电路板(printed circuit board，PCB)。
图1A至图1L，是根据本公开的一些实施例的用于形成一封装结构100的工艺的各个阶段的剖面图。
如图1A所示，根据一些实施例，一中介层晶片(interposer wafer)108被接收。在一些实施例中，中介层晶片108具有一基板101、在基板101中的多个通孔(through via)103以及在基板101上方的多个导电垫105和一钝化层107。中介层晶片108的基板101可为例如掺杂或未掺杂的硅基板，或绝缘体上覆硅(silicon-on-insulator，SOI)基板的一有源层，用于为中介层晶片108提供支撑。然而，基板101可以是玻璃基板、陶瓷基板、聚合物基板或任何其他可以提供适当保护和/或互连功能的基板。
前述通孔103可作为导电通孔，以在垂直方向上提供电连接。在一些实施例中，通孔103是通过在基板101上施加和显影光刻胶，然后蚀刻基板101以产生开口而形成的。之后，可以用一阻挡层(未示出)和一导电层填充通孔103的开口。
前述阻挡层可以包括例如氮化钛(titanium nitride)的导电材料，但是也可以替代地利用诸如氮化钽(tantalum nitride)、钛、电介质等的其他材料。可以通过使用化学气相沉积(CVD)制成(例如，等离子体增强化学气相沉积)形成阻挡层。然而，可以替代地使用诸如溅射(sputtering)或金属有机化学气相沉积(metal organic chemical vapordeposition，MOCVD)等的其他替代方法。可形成阻挡层以便与通孔103的开口的下面的形状相匹配。
通孔103的导电层可以由铜、钴、钛、铝、钨、金、铂、镍，一种或多种其他适用材料或它们的组合制成。可以通过沉积籽晶层(seed layer)，然后将导电层电镀到籽晶层上，填充和过度填充通孔103的开口来形成导电层。一旦已经填充了通孔103的开口，可通过平坦化工艺以去除通孔103的开口之外的多余的阻挡层和多余的导电层。
平坦化工艺可包含磨削工艺(grinding process)、化学机械研磨(chemicalmechanical polishing，CMP)工艺、干式研磨工艺、蚀刻工艺、切割工艺，一个或多个其他适用工艺或其组合。在平坦化工艺之后，通孔103的表面与基板101的表面基本上齐平。在本说明书的上下文中，词语“基本上”优选地是指至少90％。
如图1所示，根据一些实施例，多个导电垫105形成在通孔103上方。多个导电垫105可用于在一些通孔103之间形成多个电连接。导电垫105可由铝、铜、另一种适用材料或其组合制成。可通过诸如溅射的沉积工艺来形成导电垫105，以在基板101上形成导电材料层(未示出)，然后可通过适用的工艺去除导电材料层的一部分，例如进行光刻(photolithography)和蚀刻，以形成导电垫105。
如图1A所示，根据一些实施例，钝化层(passivation layer)107形成在通孔103和基板101之上。在一些实施例中，每个导电垫105被钝化层107部分地覆盖。钝化层107可以包含暴露导电垫105的开口。
钝化层107可由以下材料制成或包含：聚酰亚胺(PI)，聚对苯撑苯并双恶唑纤维(poly-p-phenylenebenzobisthiazole，PBO)、氮化硅、氮氧化硅，一种或多种其他可应用的材料或它们的组合。钝化层107可以通过旋涂工艺(spin coating process)、CVD工艺，喷涂工艺(spray coating process)，一种或多种其他适用工艺或其组合来形成。可以使用图案化工艺来制造期望图案的钝化层107。
如图1A所示，根据一些实施例，在形成具有被钝化层107部分暴露的导电垫105的中介层晶片108之后，在导电垫105上形成多个导电柱109。导电柱109可用于在导电垫105和随后形成的多个上层半导体裸片(overlying semiconductor dies)之间形成多个电连接。在一些实施例中，每个导电柱109具有一垂直侧壁。
在一些实施例中，导电柱109由铜、钛、钴、铝、钨、金、铂、镍、一种或多种其他适用材料或其组合制成。在一些实施例中，导电柱109通过使用电镀方法形成。此外，在一些实施例中，导电柱109的厚度(即，导电柱109的顶表面至导电柱109与导电垫105之间的界面之间的距离)在大约15μm(微米)至大约25μm的范围内。
之后，如图1A所示，根据一些实施例，在钝化层107和导电柱109上形成一聚合物层111。在一些实施例中，导电柱109的顶表面被聚合物层111覆盖，且导电柱109的侧壁邻接聚合物层111和钝化层107。
在一些实施例中，聚合物层111由环氧基树脂或另一种适用的聚合物材料制成，并且聚合物层111通过使用旋涂工艺、喷涂工艺、一个或多个其他适用工艺来形成，或其组合。在一些实施例中，聚合物层111由基于环氧树脂的树脂制成，其中填充有分散的填料。填料可包括绝缘纤维、绝缘颗粒、其他合适的元素或其组合。此外，中介层晶片108和聚合物层111可以具有一总厚度T1。在一些实施例中，总厚度T1在从大约750μm到大约800μm的范围内。
如图1B所示，根据一些实施例，在形成聚合物层111之后，执行切割工艺，以将图1A中的中介层晶片108切割成多个中介层，如中介层113、115。具体而言，根据一些实施例，沿着划线(scribe line)I-I’切割中介层晶片108，且聚合物层111也随着中介层晶片108一起被切割。因此，聚合物层111的边缘与中介层113和115的相应边缘对齐。
应当注意的是，尽管在图1B中的每个中介层113和115中示出了导电柱109中的四个、导电垫105中的四个以及通孔103中的十三个，中介层113和115中的导电柱109的数量、导电垫105的数量以及通孔103的数量不限于此。
如图1C所示，根据一些实施例，在切割过程之后，将中介层113和115放置在第一载体基板121上。在一些实施例中，中介层113和115通过粘合层123附接到第一载体基板121。粘合层123可以用于固定中介层113和115。
在一些实施例中，第一载体基板121当作一临时基板。临时基板在随后的处理步骤中提供机械和结构支撑，稍后将更详细描述。在一些实施例中，第一载体基板121由半导体材料、陶瓷材料、聚合物材料、金属材料、另一种适用材料或其组合制成。在一些实施例中，第一载体基板121是玻璃基板。
根据一些实施例，黏合层123用作临时黏合层。黏合层123可以是胶水或胶带。在一些实施例中，黏合层123是光敏层(photosensitive layer)，且容易通过光照射而与第一载体基板121分离。例如，在第一载体基板121上照射紫外线(UV)或激光用以分离黏合层123。在一些实施例中，粘合层123是光热转换(light-to-heat-conversion，LTHC)涂层。在一些实施例中，粘合层123是热敏的，且当其暴露于热时，容易从第一载体基板121分离。
此外，根据一些实施例，形成一覆盖中介层113、115的模塑料材料(未示出)，然后通过使用平坦化工艺使模塑料材料、中介层113和115变薄，以形成围绕并暴露中介层113和115的一模塑料层125。更具体地，在一些实施例中，去除中介层113和115中的聚合物层111的上部分，使得中介层113和115的导电柱109被模塑料层125暴露。
用于形成模塑料层125的模塑料材料的形成方法可包括注入工艺、旋涂工艺、喷涂工艺、一种或多种其他适用工艺或其组合。平坦化工艺可以包括磨削工艺、CMP工艺、干式研磨工艺、蚀刻工艺、切割工艺、一个或多个其他适用工艺或其组合。在平坦化工艺之后，导电柱109的顶表面与模塑料层125的顶表面基本上齐平。
如图1D所示，根据一些实施例，在形成模塑料层125之后，在模塑料层125以及中介层113和115上形成一重分布结构131。重分布结构131可以包括由多个介电层构成的一介电结构127。一导电结构129可在介电结构127中形成。
在一些实施例中，导电结构129包括多个堆叠通孔129a和多条导线129b。特别地，堆叠通孔129a可以用于形成下面的中介层113和115与随后形成的上层半导体裸片之间的多个电连接，而导线129b可用于形成下层的中介层113和115与随后形成的上层的多个表面安装器件(surface-mount devices，SMDs)之间的多个电连接。在一些实施例中，每个堆叠通孔129a包括至少两个彼此部分重叠的导电通孔。
虽然在图1D中示出了介电结构127中的三层介电层，但介电结构127中的介电层数量不限于此。例如，根据一些实施例，电介质结构127具有二至三个介电层。
在一些实施例中，前述介电结构127的介电层由氧化硅、氮化硅、碳化硅、氮氧化硅或其组合制成，且介电层通过诸如CVD工艺、旋涂工艺或其组合的沉积工艺形成。在一些实施例中，导电结构129的堆叠通孔129a和导线129b由铜、钴、钛、铝、钨、金、铂、镍或它们的组合制成，且堆叠通孔129a和导线129b导电结构129的一部分通过一个或多个蚀刻工艺和沉积工艺形成。
如图1E所示，根据一些实施例，在形成重分布结构131之后，多个第一半导体裸片137a和多个第二半导体裸片137b通过多个连接件(connectors)133结合到重分布结构131。在一些实施例中，第一半导体裸片137a和第二半导体裸片137b是逻辑裸片(logic dies)、系统芯片(system-on-chip，SoC)裸片、记忆裸片或其他适用的裸片。记忆裸片可以包括多个记忆装置，诸如静态随机存取存储器(static random access memory，SRAM)装置、动态随机存取存储器(dynamic random access memory，DRAM)装置、其他合适的装置或其组合。
在一些实施例中，第一半导体裸片137a是SoC裸片，而第二半导体裸片137b是用作高带宽存储器(high bandwidth memories，HBM)的记忆裸片。在一些实施例中，第一半导体裸片137a和第二半导体裸片137b是SoC裸片。
在一些实施例中，连接件133是直径小于约50μm的微型凸块。在一些实施例中，连接件133的直径在约30μm至约50μm的范围内。连接件133用于形成第一半导体裸片137a与堆叠通孔129a之间的电连接，并且用于形成第二半导体裸片137b与堆叠通孔129a之间的电连接。
如图1E所示，根据一些实施例，在通过连接件133将第一半导体裸片137a和第二半导体裸片137b接合到重分布结构131之后，在第一半导体裸片137a、第二半导体裸片137b、连接件133和重分布结构131之间的间隙中形成一底部填充层(underfill layer)141。如此一来，连接件133可被嵌入在底部填充层141中并由底部填充层141保护。
底部填充层141可以包括液体环氧树脂、可变形凝胶、硅橡胶、另一种合适的材料或其组合。另外，通过使用分配针(dispensing needle)或其他适用的分配工具执行分配工艺以形成底部填充层141，然后将底部填充层141的材料固化以硬化。
此外，如图1E所示，根据一些实施例，多个表面安装器件(surface-mountdevices，SMDs)139通过多个连接件135结合到重分布结构131。在一些实施例中，SMD 139是无源元件(例如，电阻器、电感器、电容器)或有源元件(例如，晶体管)。在一些实施例中，连接件135是直径范围从大约50μm到大约120μm的C4接合(controlled collapse chipconnection)凸块。连接件135用于形成SMD 139和导线129b之间的电连接。
此外，连接件135的尺寸可以大于连接件133的尺寸。在一些实施例中，如图1E所示，根据一些实施例，连接件133具有第一高度H1，连接件135具有第二高度H2，的第一高度H1大于第一高度H1。应当注意的是，根据一些实施例，在第一半导体裸片137、第二半导体裸片137b和SMDs 139被接合到重分布结构131之后，第一半导体裸片137a的底表面和第二半导体裸片137b的底表面是低于SMD 139的底表面。
此外，在一些实施例中，SMD 139设置在模塑料层125的一部分正上方。更具体地，每个SMD 139设置在模塑料层125和中介层113(或115)之间的任何界面上。在一些实施例中，用于在SMD 139与中介层113和115之间形成电连接的导线129b延伸穿过模塑料层125与中介层113或115之间的前述界面。在一些实施例中，中介层113和115没有位于SMD 139正下方的部分(未示出)。
连接件133和135可以由铜、钴、钛、铝、金、钨、铂、镍、钽、铟、锡、一种或多种其他适用的焊料材料或它们的组合制成。连接件133和135的形成方法可以包括电镀工艺，化学镀工艺，溅射工艺，物理气相沉积(PVD)工艺、一种或多种其他适用工艺或其组合。
之后，如图1F所示，根据一些实施例，形成一模塑料层143覆盖第一半导体裸片137a、第二半导体裸片137b和SMD 139。用于形成模塑料层143的一些材料和工艺可以与用于形成上述模塑料层125的材料相似或相同，在此不再赘述。此外，模塑料层125、重分布结构131和模塑料层143可以具有一总厚度T2。在一些实施例中，前述总厚度T2在大约2150μm至大约2250μm的范围内。
如图1G所示，根据一些实施例，在形成模塑料层143之后，将接合在一起(bondedtogether)的模塑料层125、重分布结构131和模塑料层143倒置并放置在第二载体基板151上。第二载体基板151可以用作一临时基板，且临时基板可以在后续处理步骤期间提供机械和结构支撑。在一些实施例中，于图1F中的结构的模塑料层143通过粘合层153附接到第二载体基板151。
用于形成第二载体基板151和黏合层153的一些材料和工艺可以与用于形成第一载体基板121和黏合层123的材料相似或相同，于此不再重复叙述。另外，如图1G所示，根据一些实施例，去除第一载体基板121和黏合层123，以暴露出模塑料层125的表面。
接着，如图1H所示，根据一些实施例，通过使用平坦化工艺，使模塑料层125、中介层113和115从它们的暴露表面变薄。平坦化工艺可以包括磨削工艺、CMP工艺、干式研磨工艺、蚀刻工艺、切割工艺、一个或多个其他适用工艺或其组合。根据一些实施例，在平坦化工艺之后，模塑料层125的一部分和基板101的一部分被去除，且通孔103被暴露并穿过基板101。
之后，如图1I所示，根据一些实施例，在模塑料层125和中介层113、115上形成一重分布结构161。重分布结构161可以包括由多个介电层构成的一介电结构157。可以在介电结构157中形成一导电结构159。
在一些实施例中，导电结构159包含多个导电通孔及/或导电层，其用于在中介层113、115和连接件之间形成电连接，这些电连接随后将形成在重分布结构161上方。此外，如图1I所示，根据一些实施例，重分布结构161的导电结构159被介电结构157中的多个开口部分地暴露，且多个凸块下金属(under bump metallurgy，UBM)结构163填充这些开口并在重分布结构161上延伸。
每个UBM结构163可以包含一个或多个层，诸如阻隔层和籽晶层。在一些实施例中，本文将包括单个层的每个UBM结构163描绘为示例。UBM结构163可以由钛、氮化钛、钽、氮化钽、钨、钛钨、镍、金、铬、铜、铜合金、另一种适用材料或其组合制成。另外，可以通过使用电镀方法来形成UBM结构163。
在图1I中，虽然示出导电结构159有六层，但导电结构159中的层数并不限于此。例如，根据一些实施例，导电结构159具有四至七层。在一些实施例中，重分布结构131具有一厚度T3，重分布结构161具有一厚度T4，其中厚度T4大于厚度T3。
前述中介层113具有一第一表面113a和与第一表面113a相对的一第二表面113b，且中介层115具有一第一表面115a和与第一表面115a相对的一第二表面115b。应当注意的是，根据一些实施例，重分布结构131、161在中介层113、115的两个相对表面上。
更具体地，在一些实施例中，重分布结构131在中介层113的第一表面113a和中介层115的第一表面115a之上，且重分布结构161在中介层113的第二表面113b之上和在中介层115的第二表面113b之上。在一些实施例中，模塑料层125被夹在重分布结构131、161之间并与之直接接触。
如图1J所示，根据一些实施例，在形成UBM结构163之后，在UBM结构163上形成多个连接件165，并通过多个连接件167将多个电容器169接合到重分布结构161。在一些实施例中，UBM结构163用于在连接件165和重分布结构161之间形成电连接，且电容器169通过连接件167和连接件167下方的UBM结构163电连接到重分布结构161。
在一些实施例中，连接件165是直径在大约150μm至大约250μm的范围内的球栅阵列(ball grid array，BGA)凸块。类似于连接件135，连接件167可为C4接合凸块。在一些实施例中，连接件165的尺寸大于连接件167、135、133的尺寸。用于形成连接件165和167的一些材料和工艺可以与用于形成上述连接件133和135的材料相似或相同，在此不再赘述。
此外，重分布结构161具有面对中介层113和115的一第一表面161a，且重分布结构161具有与第一表面161a相对的一第二表面161b。在一些实施例中，电容器169被安装在再布结构161的第二表面161b上，且连接器165被结合到重分布结构161的第二表面161b。应注意的是，完成的封装结构的性能(例如，图1L中的封装结构100)可以通过电容器169来改善。
之后，如图1K所示，根据一些实施例，将结合在一起的模塑料层143、重分布结构131、模塑料层125和重分布结构161颠倒过来，去除第二载体基板151和黏合层153，并通过使用平坦化工艺来使模塑料层143的一部分变薄。
平坦化工艺可以包括磨削工艺、CMP工艺、干式研磨工艺、蚀刻工艺、切割工艺、一个或多个其他适用工艺或其组合。在平坦化工艺之后，暴露出第一半导体裸片137a和第二半导体裸片137b，借以增强第一半导体裸片137a和第二半导体裸片137b的散热。
根据一些实施例，在平坦化工艺之后，将结合在一起的模塑料层143、重分布结构131、模塑料层125和重分布结构161放置在一支撑框架结构(未示出)上，并进行切割工艺，以沿着划线II-II’切割模塑料层143、重分布结构131、模塑料层125和重分布结构161。
如图1L所示，据一些实施例，切割模塑料层143、重分布结构131、模塑料层125和重分布结构161以形成多个封装结构100。重分布结构131具有一第一长度L1，中介层113具有一第二长度L2。在一些实施例中，重分布结构161的长度与第一长度L1基本上相同，且第一长度L1大于第二长度L2。此外，应当注意的是，重分布结构131、中介层113、模塑料层125和重分布结构161可以形成一混合中介层结构(hybrid interposer structure)。
在封装结构100中，SMD 139可以安装在混合中介层结构上，并通过混合中介层结构的重分布结构131电连接到中介层113。由于可以将SMD 139整合(be integrated)到封装结构100中，所以不需要将封装结构100结合到另外的基板(例如，印刷电路板)以在SMD 139和中介层113之间提供电连接。
尽管封装结构100是晶片上芯片(chip-on-wafer，CoW)结构，但由于两个重分布结构131和161位在中介层113的相对侧上，封装结构100可以用作基板上晶片上芯片(chip-on-wafer-on-substrate，CoWoS)结构。前述的混合中介层基板(包括重分布结构131、中介层113、模塑料层125和重分布结构161)可以通过降低相关成本、缩小封装结构的整体尺寸并允许形成大于32mm x 26mm的超大型封装结构来提供好处。
图2A至图2D是根据本公开一些实施例的用于形成封装结构200的工艺的各个阶段的剖面示意图。用于形成图2A1至图2D中所示的封装结构200的一些工艺可以与用于形成图1F至图1L所示的封装结构100的那些工艺相似或相同。
如图2A所示，根据一些实施例，与图1F所示的结构类似的一结构通过粘合层123附着在第一载体基板121上。根据一些实施例，图1F的结构和图2A的结构之间的区别之一是在图2A中未形成底部填充层141。因此，在一些实施例中，连接件133受到保护并与模塑料层143直接接触。
此外，在一些实施例中，图1F的结构和图2A的结构之间的另一个区别在于，在将第二载体基板151通过粘合层153附接到模塑料层143之前，先对模塑料层143执行平坦化工艺以暴露第一半导体裸片137a和第二半导体裸片137b。平坦化工艺可以包括磨削工艺、CMP工艺、干式研磨工艺、蚀刻工艺、切割工艺、一个或多个其他适用工艺或其组合。
接着，在一些实施例中，在图2A的结构上执行与图1G所示的工艺类似的工艺，将接合在一起的模塑料层125、重分布结构131和模塑料层143倒置，并通过黏合层153连接到第二载体基板151。
在一些实施例中，由于第一半导体裸片137a和第二半导体裸片137b已经被模塑料层143暴露，所以第一半导体裸片137a和第二半导体裸片137b直接与黏合层153接触，或者，如果未形成黏合层153，则与第二载体基板151直接接触。
之后，如图2B所示，根据一些实施例，与图1H所示的工艺相似，通过使用平坦化工艺来使模塑料层125、中介层113和115变薄。根据一些实施例，在平坦化工艺之后，模塑料层125的一部分和基板101的一部分被去除，且通孔103被暴露出并穿透基板101。
根据一些实施例，在暴露出通孔103之后，在图2B的结构上执行与图1I至图1J所示的工艺类似的工艺。具体而言，根据一些实施例，如图2C所示，重分布结构161形成在模塑料层125和中介层113、115的暴露通孔103上方。另外，根据一些实施例，UBM结构163和连接件165形成在重分布结构161上。
接着，在一些实施例中，对图2C的结构切割以形成多个封装结构200，且重分布结构131、模塑料层125和重分布结构161在封装结构200中形成一混合中介层结构，如图2D所示。
在封装结构100和200的实施例中，SMD 139可以安装在混合中介层结构上，并通过混合中介层结构的重分布结构131电连接到中介层113。由于可以将SMD 139整合到封装结构100和200中，因此无需将封装结构100接合到额外基板(例如，印刷电路板)以提供SMD139与中介层113之间的电连接。
虽然封装结构100和200是晶片上芯片(CoW)结构，但由于两个重分布结构131、161位在中介层的两侧，使封装结构100和200可以用作基板上晶片上芯片(CoWoS)结构。混合中介层基板(包含重分布结构131、中介层113、模塑料层125和重分布结构161)可通过降低相关成本、缩小封装结构的整体尺寸并允许形成超大型封装结构，借以提供益处。
于一些实施例中，提供了封装结构的实施方式及其形成方法。封装结构可以包括一第一重分布结构和在第一重分布结构上的一中介层。封装结构还可包括围绕中介层的一模塑料层以及中介层上的一第二重分布结构。第一和第二重分布结构设置在中介层的两侧上，且一混合中介层结构可以由第一和第二重分布结构、中介层和模塑料层形成。由于可以将电子组件(例如，表面安装器件)整合到封装结构中，因此有利的是，降低了相关成本，并减小了整体尺寸。另外，允许形成超大型封装结构。
在一些实施例中，提供了一种封装结构。封装结构包括一第一重分布结构和在第一重分布结构上的一中介层。封装结构还包括围绕中介层的一模塑料层，以及中介层上的一第二重分布结构。模塑料层在第一重分布结构和第二重分布结构之间。封装结构还包括在第二重分布结构上方的一第一半导体裸片和第二半导体裸片。
在一些实施例中，封装结构还包括在第二重分布结构上方的一表面安装器件(surface-mount device，SMD)。
在一些实施例中，封装结构还包括：一第一连接件，位于第一半导体裸片和第二再重分布结构之间；一第二连接件，位于表面安装器件和第二重分布结构之间，其中第二连接件的高度大于第一连接件的高度。
在一些实施例中，中介层还包括：一通孔，位于基板中；一导电垫，位于通孔上方；一钝化层，部分地覆盖导电垫；一聚合物层，位于钝化层上方；与在导电垫上的一导电柱，其中导电柱被聚合物层和钝化层围绕。
在一些实施例中，导电柱的表面与模塑料层的表面基本上齐平。
在一些实施例中，第一重分布结构的厚度大于第二重分布结构的厚度。
在一些实施例中，封装结构还包括：一电容器，其通过第一重分布结构电连接到中介层，其中第一重分布结构具有面对中介层的一第一表面和与第一表面相对的一第二表面，且电容器安装在第二表面上。
在一些实施例中，提供了一种封装结构。封装结构包括一第一重分布结构和在第一重分布结构上的一中介层。中介层包含在一基板上方的一导电垫和在导电垫上方的一导电柱。封装结构还包括中介层上的一第二重分布结构。封装结构还包括一第一半导体裸片、一第二半导体裸片以及在第二重分布结构上方的一表面安装器件(surface-mountdevice，SMD)。第一半导体裸片通过第二重分布结构电性连接到导电柱。
在一些实施例中，第一半导体裸片的底表面和第二半导体裸片的底表面低于表面安装器件的底表面。
在一些实施例中，第一重分布结构的长度和第二重分布结构的长度大于中介层的长度。
在一些实施例中，封装结构还包括：一模塑料层，围绕中介层，其中模塑料层的一部分在表面安装器件的正下方，且中介层被第一重分布结构、模塑料层和第二重分布结构包围。
在一些实施例中，中介层还包含：在基板上的一通孔，被导电垫覆盖；一钝化层，部分覆盖导电垫；与在钝化层上方并围绕导电柱的一聚合物层。
在一些实施例中，封装结构还包括：一连接件，位于第一半导体裸片和第二重分布结构之间，其中第一半导体裸片通过第二重分布结构中的一堆叠通孔电性连接到中介层的导电柱。
在一些实施例中，提供了一种用于形成封装结构的方法。用于形成封装结构的方法包括：形成围绕一第一中介层的一第一模塑料层，以及在第一中介层的一第一侧和第一模塑料层上形成一第一重分布结构。用于形成封装结构的方法还包括：通过多个第一连接件将一第一半导体裸片和一第二半导体裸片结合到第一重分布结构，以及在与第一中介层的第一侧相对的第一中介层的一第二侧上形成一第二重分布结构。
在一些实施例中，用于形成封装结构的方法还包括：通过一第二连接件将一表面安装器件(surface-mount device，SMD)接合到第一重分布结构，其中第二连接件的高度大于多个第一连接件的高度。
在一些实施例中，表面安装器件通过第一重分布结构的导线电连接到第一中介层，且导线延伸穿过第一模塑料层和第一中介层之间的一界面。
在一些实施例中，用于形成封装结构的方法还包括：形成覆盖第一半导体裸片和第二半导体裸片的一第二模塑料层，其中第一重分布结构在第一模塑料层和第二模塑料层之间延伸。
在一些实施例中，第二重分布结构从第一中介层的第二侧延伸到第一模塑料层的一表面，其中用于形成封装结构的方法还包括：在形成第二重分布结构之前，将第二模塑料层附接到一第二载体基板上。
在一些实施例中，用于形成封装结构的方法还包括：在一中介晶片上形成一第一导电柱和一第二导电柱，其中，中介晶片包括在一基板上方的多个导电垫和部分覆盖导电垫的一钝化层，其中第一导电柱和第二导电柱在导电垫上形成；形成覆盖钝化层、第一导电柱和第二导电柱的一聚合物层；切割基板、聚合物层和钝化层以形成第一中介层和一第二中介层，其中第二导电柱在第二中介层中。
在一些实施例中，用于形成封装结构的方法还包括：将第一中介层和第二中介层放置在一第一载体基板上；形成覆盖第一中介层和第二中介层的一第一模塑料材料；以及薄化第一中介层、第二中介层和第一模塑料材料，以形成暴露第一导电柱和第二导电柱的第一模塑料层。
上述内容概述许多实施例的特征，因此本领域技术人员可更加理解本公开的各面向。本领域技术人员可能无困难地以本公开为基础，设计或修改其他工艺及结构，以达到与本公开实施例相同的目的及/或得到相同的优点。任何所属技术领域中技术人员也应了解，在不脱离本公开的精神和范围内做不同改变、代替及修改，如此等效的创造并没有超出本公开的精神及范围。

Claims (1)

1.一种封装结构，包括：
一第一重分布结构；
一中介层，在该第一重分布结构上；
一模塑料层，围绕该中介层；
一第二重分布结构，在该中介层上，其中该模塑料层在该第一重分布结构与该第二重分布结构之间；以及
一第一半导体裸片与一第二半导体裸片，在该第二重分布结构上。
CN202010848754.8A 2019-08-22 2020-08-21 封装结构 Pending CN112420684A (zh)

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11462418B2 (en) * 2020-01-17 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
WO2023034738A1 (en) * 2021-09-01 2023-03-09 Adeia Semiconductor Technologies Llc Stacked structure with interposer

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007034629A1 (ja) * 2005-09-20 2007-03-29 Murata Manufacturing Co., Ltd. 部品内蔵モジュールの製造方法および部品内蔵モジュール
US9048233B2 (en) * 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8338945B2 (en) 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
US20120152606A1 (en) * 2010-12-16 2012-06-21 Ibiden Co., Ltd. Printed wiring board
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
TWI473218B (zh) * 2012-07-26 2015-02-11 Unimicron Technology Corp 穿孔中介板及其製法與封裝基板及其製法
US8810006B2 (en) 2012-08-10 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer system and method
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9633869B2 (en) 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9607967B1 (en) * 2015-11-04 2017-03-28 Inotera Memories, Inc. Multi-chip semiconductor package with via components and method for manufacturing the same
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10784220B2 (en) * 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
US10461023B2 (en) * 2017-10-30 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and methods of forming the same

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