CN112447527A - 封装结构及其形成方法 - Google Patents

封装结构及其形成方法 Download PDF

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Publication number
CN112447527A
CN112447527A CN202010869961.1A CN202010869961A CN112447527A CN 112447527 A CN112447527 A CN 112447527A CN 202010869961 A CN202010869961 A CN 202010869961A CN 112447527 A CN112447527 A CN 112447527A
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conductive
layer
forming
insulating layer
conductive layer
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CN202010869961.1A
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李苓玮
张容华
黄震麟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112447527A publication Critical patent/CN112447527A/zh
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Abstract

提供封装结构和封装结构的形成方法，此方法包含形成导电结构于承载基板之上以及设置半导体晶粒于承载基板之上。此方法也包含形成保护层以围绕导电结构与半导体晶粒。此方法也包含形成绝缘层于保护层之上。绝缘层具有开口暴露出导电结构的一部分。开口的宽度大于25微米。此外，此方法也包含形成导电层于绝缘层之上。导电层过量填充开口，且导电层具有大致平坦的顶面。导电层的一部分延伸横跨导电结构的侧壁。

Description

封装结构及其形成方法
技术领域
本公开实施例涉及一种封装结构及其形成方法，且特别涉及具有扇出(fan-out)部件的封装结构及其形成方法。
背景技术
半导体集成电路(integrated circuit，IC)产业已经经历了快速的增长。半导体制造工艺的持续进步已经导致具有更精细部件和/或更高整合度的半导体装置。功能密度(即，每单位芯片(chip)面积的互连装置的数量)已普遍增加，同时特征尺寸(即，可使用制造工艺产生的最小组件)已减小。这种微缩过程通常可通过提高生产效率和降低相关成本来提供益处。
芯片封装不仅为半导体装置提供免于受到环境污染的保护，而且还为封装于其中的半导体装置提供连接接口(connection interface)。已经开发出利用较小面积或较低高度的较小封装结构来封装半导体装置。
已经开发了新的封装技术以进一步改善半导体晶粒(die)的密度和功能。这些相对新颖的半导体晶粒封装技术面临了制造挑战。
发明内容
本公开实施例提供封装结构的形成方法，此方法包含形成导电结构于承载基板之上以及设置半导体晶粒于承载基板之上。此方法也包含形成保护层以围绕导电结构与半导体晶粒。此方法也包含形成绝缘层于保护层之上。绝缘层具有开口暴露出导电结构的一部分。开口的宽度大于25微米。此外，此方法也包含形成导电层于绝缘层之上。导电层过量填充开口，且导电层具有大致平坦的顶面。导电层的一部分延伸横跨导电结构的侧壁。
本公开实施例提供封装结构的形成方法，此方法包含设置保护层以围绕导电结构和半导体晶粒。此方法也包含形成第一绝缘层于保护层之上。第一绝缘层具有第一开口暴露出导电结构的一部分。此方法也包含使用由下而上沉积工艺，形成导电层于第一绝缘层之上，以过量填充第一开口。导电层的一部分延伸于开口之外，且延伸横跨导电结构的侧壁。此方法也包含形成第二绝缘层于导电层之上。第二绝缘层具有第二开口暴露出导电层的一部分。此方法也包含形成导电柱于导电层自第二开口暴露出来的部分之上。
本公开实施例提供封装结构，此封装结构包含彼此横向隔开的导电结构与半导体晶粒。此封装结构也包含围绕导电结构和半导体晶粒的保护层。此封装结构也包含位于保护层之上的绝缘层。此封装结构也包含位于绝缘层之上且电性连接至导电结构的导电层。导电层具有大致平坦的顶面。导电层埋入绝缘层中的部分具有大于约25微米的宽度。
附图说明
通过以下的详细描述配合说明书附图，可以更加理解本公开实施例的内容。需强调的是，根据产业上的标准惯例，许多部件(feature)仅用于说明目的，并未按照比例绘制。事实上，为了能清楚地讨论，各种部件的尺寸可能被任意地增加或减少。
图1A至图1I是根据一些实施例显示形成封装结构的工艺的各种阶段的剖面示意图。
图2A至图2I是根据一些实施例显示形成封装结构的工艺的各种阶段的剖面示意图。
图3是根据一些实施例显示封装结构的剖面示意图。
附图标记说明：
100：承载基板
102：粘着层
104：晶粒贴合膜
106A：半导体晶粒
106B：半导体晶粒
108：半导体基底
109：内连线结构
110：钝化层
112：导电垫
114：保护层
115：重布线结构
116：绝缘层
118：导电部件
120：导电垫
122：导电结构
124：半导体晶粒
126：半导体基底
128：内连线结构
130：导电垫
132：导电垫
134：导电凸块
136：底部填充元件
138：基底贯孔
140：保护层
142a：绝缘层
142b：绝缘层
144：导电层
144s：顶面
146：导电柱
148：导电凸块
150：胶带载板
152：电路板
154：导电垫
202：开口
204：晶种层
206：遮罩元件
208：开口
212：开口
214：晶种层
216：遮罩元件
218：开口
H：高度差
P1：第一部分
P2：第二部分
T：厚度
t1：第一厚度
t2：第二厚度
具体实施方式
以下内容提供了多个不同的实施例或范例，用于实现本公开实施例的不同部件。组件和配置的具体范例描述如下，以简化本公开实施例。当然，这些仅仅是范例，并非用以限定本公开实施例。举例来说，叙述中若提及第一部件形成于第二部件或之上，可能包含形成第一和第二部件直接接触的实施例，也可能包含额外的部件设置于第一和第二部件之间，使得第一和第二部件不直接接触的实施例。另外，本公开实施例可能在许多范例中重复元件符号及/或字母。这些重复是为了简化和清楚的目的，他们本身并非代表所讨论各种实施例及/或配置之间有特定的关系。
此外，此处可能使用空间上的相关用语，例如“在…之下”、“在…下方”、“下方的”、“在…上方”、“上方的”和其他类似的用语可用于此，以便描述如图所示的一元件或部件与其他元件或部件之间的关系。此空间上的相关用语除了包含附图示出的方位外，也包含使用或操作中的装置的不同方位。当装置被转至其他方位时(旋转90度或其他方位)，则在此所使用的空间相对描述可同样依旋转后的方位来解读。
在叙述中，用语“大致上(substantially)”，例如“大致上平坦”或“大致上共平面”等，将被本领域中的通常知识者所理解。在一些实施例中，大致上将形容词移除。在适用的情况下，用语“大致上”也可包含具有“完整地(entirely)”、“完全地(completely)”、“所有地(all)”等情况的实施例。在适用的情况下，用语“大致上”也可涉及90％或更多，例如95％或更多，尤其是99％或更多，或包含100％的情况。再者，用语“大致平行”或“大致垂直”被解读为不排除与特定排列的微小偏差，并且可包含，例如高达10°的偏差。用语“大致上”不排除“完全地”，例如，“大致上不含(substantially free)”Y的组成，可以是完全地不含Y。
例如“大约(about)”的用语，与特定距离或尺寸连用时，被解读为不排除与特定距离或尺寸的微小偏差，并且可包含，例如高达10％的偏差。用语“大约”与数值x的关系可以表示x±5或10％。
本文讨论一些实施例。在这些实施例所提及的阶段之前、期间、或之后可提供额外的步骤。对于不同的实施例，可以置换或删减所述的一些阶段。可增加额外的部件至封装结构。对于不同的实施例，可以置换或删减以下所述的一些部件。尽管一些实施例是以特定顺序进行的步骤来讨论，但这些步骤可以其他符合逻辑的顺序来进行。
本文的实施例可涉及三维(3D)封装或三维集成电路(3D-IC)装置。也可包含其他部件或工艺。举例而言，可以包含测试结构，以帮助3D封装或3D-IC装置进行验证测试。可以包含测试结构，例如，形成于重布线(redistribution)层或基板上的测试垫(testingpad)，其使3D封装或3D-IC能进行测试、探针(probe)或探针卡(probe card)得以使用等等。可对中间结构和最终结构进行验证测试。另外，本文公开的结构和方法可与测试方法(testing methodology)结合使用，这整合识别良品晶粒(good die)的中间验证，以提高良率并降低成本。
图1A至图1I是根据一些实施例显示形成封装结构的工艺的各种阶段的剖面示意图。提供或接收承载基板(carrier substrate)100，如图1A所示。在一些实施例中，承载基板100是作为暂时的支撑基板，后续会将承载基板100移除。承载基板100可包含或者由半导体材料、陶瓷材料、聚合物材料、金属材料、一或多其他适合材料、或前述的组合形成。在一些实施例中，承载基板100是玻璃基板，例如玻璃晶圆(wafer)。在其他一些实施例中，承载基板100是半导体基板，例如硅晶圆。
根据一些实施例，之后，形成或贴附粘着层(adhesive layer)102于承载基板100之上，如图1A所示。粘着层102可以包含或者由粘胶(glue)、层压材料(laminationmaterial)、一或多其他适合材料、或前述的组合形成。在一些实施例中，粘着层102对于能量束照射敏感。在一些实施例中，粘着层102是包含或者由光热转换(light-to-heatconversion，LTHC)材料形成的释放层(release layer)。举例而言，使用激光束及/或紫外光(UV light)照射粘着层102。在照射之后，粘着层102可轻易自承载基板100脱离(detach)。在其他一些实施例中，粘着层102是热敏感的。可使用热处理使粘着层102脱离。
在一些实施例中，粘着层102是单层。然而，本公开实施例不限于此。可以对发明实施例进行各种变化及/或修改。在其他一些实施例中，粘着层102包含多个子层。在一些实施例中，这些子层包含胶粘层、基于聚合物(polymer base)的层、及光热转换(LTHC)层。
根据一些实施例，之后，贴附晶粒贴合膜(die attach film，DAF)至粘着层102上，如图1A所示。晶粒贴合膜104可包含或者由一或多基于酚醛材料(phenolic basematerial)、一或多基于环氧基材料(epoxy base material)、一或多其他适合材料、前述的组合形成。
可以对发明实施例进行各种变化及/或修改。在其他一些实施例中，并未形成或贴附晶粒贴合膜104至粘着层102之上。
根据一些实施例，设置半导体晶粒(semiconductor die)106A和106B于晶粒贴合膜104之上，如图1B所示。在一些实施例中，半导体晶粒106A和106B可各自包含芯片(chip)，例如，系统单芯片(system-on-chip，SoC)芯片，其包含一或多个期望的功能。在一些实施例中，半导体晶粒106A和106B的背侧(back side)面向晶粒贴合膜104，并且半导体晶粒106A和106B的前侧(front side)面上。可使用取放(pick and place)操作，设置半导体晶粒106A和106B。在一些实施例中，使用机械手臂拾取半导体晶粒106A，接着机械手臂将半导体晶粒106A放置于晶粒贴合膜104的对应位置上。之后，使用机械手臂拾取半导体晶粒106B，接着将半导体晶粒106B放置于晶粒贴合膜104的对应位置上。在其他一些实施例中，使用两支或更多的机械手臂来同时取放和放置半导体晶粒106A和106B。可替代地，在其它一些实施例中，半导体晶粒106A和106B的前侧面向晶粒贴合膜104，并且半导体晶粒106A和106B的背侧面上。
半导体晶粒106A和106B可各自包含半导体基底108、内连线结构(interconnection structure)109、位于半导体晶粒前侧的导电垫(conductive pad)112、以及围绕导电垫112的钝化层(passivation layer)110。在一些实施例中，形成各种装置元件于半导体基底108内或半导体基底108上。示例的各种装置元件包含晶体管(transistor)，例如，金属氧化物半导体场效晶体管(metal oxide semiconductor fieldeffect transistors，MOSFET)、互补式金属氧化物半导体(complementary metal oxidesemiconductor，CMOS)晶体管、双极接面晶体管(bipolar junction transistors，BJT)、高压晶体管、高频晶体管、p型通道及/或n型通道场效晶体管(pFET/nFET)、二极管(diodes)、或其他适合元件。
通过形成于内连线结构109中的导电部件，可互连装置元件以形成集成电路(integrated circuit)装置。内连线结构109可包含多个介电层和多个导电部件。导电部件可包含多个导线(line)、导电接触件(contact)、以及导电通孔(via)。集成电路装置包含逻辑装置、存储器装置(例如，静态随机存取存储器(SRAM))、射频(RF)装置、输入/输出(I/O)装置、系统单芯片(SoC)装置、一或多其他适用种类的装置、或前述的组合。在一些实施例中，半导体晶粒106A或106B是包含多种功能的SoC芯片。
导电垫112可以是形成于内连线结构109上的一些导线的较宽部分。导电垫112可以部分埋入于钝化层110中。每一个导电垫112通过内连线结构109中的一些导电部件，电性连接至一或多个装置元件。因此，半导体基底108中及/或上的装置元件可通过导电垫112电性连接至其他元件。
根据一些实施例，形成保护层114于承载基板100之上，以围绕且保护半导体晶粒106A和106B，如图1C所示。一部分的保护层114可形成于半导体晶粒106A与106B之间。在一些实施例中，保护层114与半导体晶粒106A和106B直接接触。在一些实施例中，保护层114包含或者由绝缘材料形成，例如模制材料(molding material)。
模制材料可包含聚合物材料，例如具有一或多个填充物散布于其内的环氧基树脂(epoxy-based resin)。填充物可包含绝缘颗粒，绝缘纤维、一或多其他元件、或前述的组合。举例而言，填充物包含氧化硅(silica)颗粒、氧化硅纤维、含碳颗粒、含碳纤维、一或多其他适合填充物、或前述的组合。
在一些实施例中，导入或射出模制材料(例如，液体模制材料)，以覆盖半导体晶粒106A和106B。在一些实施例中，接着使用热操作以固化(cure)液体模制材料，并且将其转变为保护层114。
在一些实施例中，使用平坦化工艺以降低保护层114的厚度。在一些实施例中，平坦化保护层114，以暴露出半导体晶粒106A和106B的导电垫112。可使用机械研磨(mechanical grinding)工艺、化学机械研磨(chemical mechanical polish，CMP)工艺、干式研磨工艺、蚀刻工艺、一或多其他适用工艺、或前述的组合，实现保护层114的平坦化。
根据一些实施例，之后，形成重布线结构115于保护层114和半导体晶粒106A和106B之上，如图1C所示。重布线结构115用于绕线(routing)，这使具有扇出(fan-out)部件的封装结构得以形成。在一些实施例中，重布线结构115延伸横跨半导体晶粒106A(或106B)与保护层114之间的界面。
在一些实施例中，重布线结构115包含一或多个绝缘层116和多个导电部件118。导电部件118被一或多个绝缘层116围绕。导电部件118可包含导线、导电通孔、及/或导电垫。
重布线结构115的绝缘层116可包含或者由一或多个聚合物(polymer)材料形成。聚合物材料可包含聚酰亚胺(polyimide，PI)、聚苯并恶唑(polybenzoxazole，PBO)、环氧基树脂(epoxy-based resin)、一或多其他适合聚合物材料、或前述的组合。在一些实施例中，聚合物材料具有光敏感性。因此，可使用光刻(photolithography)工艺，形成具有期望图案的开口于绝缘层中。这些开口用于容纳导电部件。
导电部件118可包含在水平方向上提供电连接的导线、以及在垂直方向上提供电连接的导电通孔。在一些实施例中，一些导电通孔彼此堆叠。较高导电通孔与较低导电通孔大致对准。在一些实施例中，一些导电通孔是错开的导电通孔。较高导电通孔与较低导电通孔未对准。在一些实施例中，导电部件118是贯孔(through vias)，其贯穿绝缘层116。在一些实施例中，每一个导电部件118与其下方对应的导电垫112对准。
重布线结构115的导电部件118可包含或者由铜、铝、金、钴、钛、镍、银、石墨烯、一或多其他适合导电材料、或前述的组合形成。在一些实施例中，导电部件118包含多个子层。举例而言，每一个导电部件118含有多个子层，这些子层包含钛/铜(Ti/Cu)、钛/镍/铜(Ti/Ni/Cu)、钛/铜/钛(Ti/Cu/Ti)、铝/钛/镍/银(Al/Ti/Ni/Ag)、其他适合子层、或前述的组合。
重布线结构115的形成可涉及多道沉积或涂布(coating)工艺、多道图案化工艺、及/或多道平坦化工艺。
可使用沉积或涂布工艺，以形成绝缘层及/或导电层。沉积或涂布工艺可包含旋转涂布(spin-on coating)工艺、喷雾涂布(spray coating)工艺、电镀(electroplating)工艺、无电(electroless)工艺、化学气相沉积(chemical vapor deposition，CVD)工艺、物理气相沉积(physical vapor deposition，PVD)工艺、原子层沉积(atomic layerdeposition，ALD)工艺、一或多其他适用工艺、或前述的组合。
可使用图案化工艺，将形成的绝缘层及/或形成的导电层图案化。图案化工艺可包含光刻工艺、能量束钻孔工艺(例如，激光束钻孔工艺、离子束钻孔工艺、或电子束钻孔工艺)、蚀刻工艺、机械钻孔工艺、一或多其他适用工艺、或前述的组合。
可使用平坦化工艺，提供形成的绝缘层及/或形成的导电层具有平坦的顶面，以利于后续工艺。平坦化工艺可包含机械研磨工艺、化学机械研磨(CMP)工艺、干式研磨工艺、蚀刻工艺、一或多其他适用工艺、或前述的组合。
根据一些实施例，形成导电垫120和132于重布线结构115之上，如图1D所示。每一个导电垫120和132电性连接至其下方对应的导电部件118。可使用导电垫120支撑或接收导电部件，例如导电柱(pillar)及/或导电凸块(bump)。可使用导电垫132支撑或接收一或多个半导体晶粒或其他元件。在一些实施例中，导电垫120和132的功能是作为凸块下金属(under bump metallization，UBM)垫。导电垫120和132的形成涉及一或多道沉积工艺以及一或多道图案化工艺。
根据一些实施例，之后，形成导电结构122于导电垫120之上，如图1D所示。在一些实施例中，导电结构122是导电柱。导电结构122的功能是作为贯孔(through vias)。在一些实施例中，每一个导电结构122具有大致垂直的侧壁，其大致垂直于导电结构122的顶面。导电结构122可包含或者由铜、钴、锡、钛、金、一或多其他适合材料、或前述的组合形成。可使用电镀工艺、无电镀制工艺(electroless plating process)、一或多其他适用工艺、或前述的组合，形成导电结构122
可以对发明实施例进行各种变化及/或修改。在其他一些实施例中，拾取导电结构122且将其放置于导电垫120上。在一些实施例中，使用焊料元件或焊料(例如，含锡焊料)来粘贴(affix)导电结构122于导电垫120上。在一些实施例中，使用遮罩元件来辅助导电结构122的放置。
根据一些实施例，设置半导体晶粒124于重布线结构105之上，如图1E所示。在一些实施例中，半导体晶粒124的前侧面向重布线结构105，且半导体晶粒124的背侧面上。可使用取放操作，设置半导体晶粒124。
半导体晶粒124可包含半导体基底126、内连线结构128、以及位于半导体晶粒前侧的导电垫130。在一些实施例中，形成各种装置元件于半导体晶粒126中或半导体晶粒126上。示例的各种装置元件包含晶体管，例如，金属氧化物半导体场效晶体管(MOSFET)、互补式金属氧化物半导体(CMOS)晶体管、双极接面晶体管(BJT)、高压晶体管、高频晶体管、p型通道及/或n型通道场效晶体管(pFET/nFET)、二极管、或其他适合元件。
通过形成于内连线结构128中的导电部件，互连装置元件以形成集成电路装置。内连线结构128可包含多个介电层和多个导电部件。导电部件可包含多个导线、导电接触件、以及导电通孔。集成电路装置包含逻辑装置、存储器装置(例如，静态随机存取存储器(SRAM))、射频(RF)装置、输入/输出(I/O)装置、系统单芯片(SoC)装置、一或多其他适用种类的装置、或前述的组合。在一些实施例中，半导体晶粒124是包含多种功能的SoC芯片。
然而，本公开实施例不限于此。可以对发明实施例进行各种变化及/或修改。在其他一些实施例中，半导体晶粒124的功能是作为互联晶粒(interconnection die)，其用以形成半导体晶粒106A和106B的装置元件之间的电性连接。在一些实施例中，没有装置元件形成于半导体晶粒124中。在一些实施例中，半导体晶粒124包含基底贯孔(throughsubstrate hole)138。基底贯孔138可穿过半导体基底126，并且电性连接至内线结构128中的一或多个导电部件。
导电垫130可以是形成于内连线结构128上的一些导线的较宽部分。一些导电垫130可通过内连线结构128中的一些导电部件，电性连接至一或多个装置元件。可替代地，一些导电垫130可通过内连线结构128中的一些导电部件，电性连接至基底贯孔138。因此，半导体基底126中及/或上的装置元件可通过导电垫130电性连接至其他元件。
在一些实施例中，半导体晶粒124的导电垫130通过导电凸块134接合至导电垫132，如图1E所示。在一些实施例中，导电凸块134是含锡焊料凸块。含锡焊料凸块可进一步包含铜、银、金、铝、铅、一或多其他适合材料、或前述的组合。在其它一些实施例中，导电凸块134是无铅的(lead-free)。在一些实施例中，形成底部填充(underfill)元件136，以围绕且保护包含导电凸块134以及导电垫130和132的接合结构，如图1E所示。
根据一些实施例，形成保护层140于重布线结构105之上，以围绕且保护半导体晶粒124和导电结构122，如图1F所示。在一些实施例中，保护层140、导电结构122与半导体晶粒124的基底贯孔138的顶面彼此大致齐平。保护层140的材料与形成方法可与保护层114相同或相似。
根据一些实施例，形成绝缘层142a和142b、导电层144和导电柱146于图1F所示的结构之上，如图1G所示。
图2A至图2I是根据一些实施例显示形成封装结构的工艺的各种阶段的剖面示意图。在一些实施例中，图2A至图2I是放大的剖面示意图，其显示图1G中示出的绝缘层142a和142b、其中一个导电层144、以及其中一个导电柱146的形成。
根据一些实施例，形成绝缘层142a于保护层140、导电结构122、以及半导体晶粒124之上，如第2A及/或1G图所示。绝缘层142a可包含或者由一或多聚合物材料形成。聚合物材料可包含聚酰亚胺(PI)、聚苯并恶唑(pPBO)、环氧基树脂、一或多其他适合聚合物材料、或前述的组合。可使用旋转涂布工艺、喷雾涂布工艺、一或多其他适用工艺、或前述的组合，形成绝缘层142a。
在一些实施例中，聚合物材料具有光敏感性。因此，使用光刻工艺以形成具有期望图案的开口于绝缘层中。根据一些实施例，形成开口202于绝缘层142a中，以暴露出其中一个导电结构122，如图2A所示。可使用光刻工艺形成开口202。在一些实施例中，开口202的宽度大于约25微米(μm)。
根据一些实施例，之后，形成导电层144。图2B至图2E和图1G是根据一些实施例显示形成其中一个导电层144。根据一些实施例，沉积晶种层204于绝缘层142a和导电结构122之上，如图2B所示。晶种层204延伸于开口202的侧壁和底面之上。在一些实施例中，晶种层204以大致顺应(conformal)方式延伸于开口202的侧壁和底面之上。
晶种层204可以包含或者由金属材料形成。晶种层204可包含或者由钛、钛合金、铜、铜合金、一或多其他适合材料、或前述的组合形成。钛合金或铜合金可进一步含有银、铬、镍、锡、金、钨、一或多其他适合元素、或前述的组合。在一些实施例中，晶种层204是单层。在其他一些实施例中，晶种层204包含多个子层。可使用物理气相沉积(PVD)工艺、化学气相沉积(CVD)工艺、旋转涂布工艺、原子层沉积(ALD)工艺、一或多其他适用工艺、或前述的组合，沉积晶种层204。
根据一些实施例，形成遮罩元件206于晶种层204之上，如图2C所示。遮罩元件206具有开口208，开口208暴露出上方将形成导电层的晶种层204的一部分。在一些实施例中，遮罩元件206是光敏感层。遮罩元件206可以包含或者由光刻胶材料形成。因此，使用光刻工艺以形成遮罩元件206的开口208，光刻工艺包含曝光步骤和显影步骤。
根据一些实施例，沉积导电层144于晶种层204被开口208暴露出来的部分之上，如图2D所示。在一些实施例中，导电层144过量填充绝缘层142a的开口202。在一些实施例中，导电层144具有第一部分P1和第二部分P2。第二部分P2覆盖开口202。在一些实施例中，第二部分P2完全覆盖开口202，并且具有第二厚度t2。第一部分P1延伸于晶种层204覆盖绝缘层142a的部分之上。第一部分P1具有第一厚度t1。第一厚度t1可以范围在约2微米至约7微米。第二厚度t2对第一厚度t1的比值(t2/t1)可以范围在约1.5至约3。具有第二厚度t2的第二部分P2比具有第一厚度t1的第一部分P1厚，如图2D所示。在这样的情况下，导电层144可呈现大致平坦的顶面144s，如图2D所示。在一些实施例中，导电层144的整个顶面是大致平坦的。
导电层144可包含或者由铜、钴、锡、钛、金、镍、铂、一或多其他适合材料、或前述的组合形成。在一些实施例中，使用由下而上(bottom-up)沉积工艺沉积导电层144。也就是说，选择性沉积或成长用于形成导电层144下部的导电材料于晶种层204表面上，并且沉积或成长用于形成导电层144上部的更多导电材料于已沉积或成长的导电材料。由下而上沉积工艺可以是电化学工艺。由下而上沉积工艺可包含电镀工艺、无电镀制工艺、一或多其他适用工艺、或前述的组合。在一些实施例中，由下而上沉积工艺是原子层沉积(ALD)工艺。
在一些实施例中，导电层144由铜形成，并且使用电镀工艺沉积。用于电镀铜的电解液可含有硫酸铜(CuSO4)以及硫酸(H2SO4)。硫酸自硫酸铜解离出铜离子，使得硫酸铜迁移至晶种层204表面，并形成导电层144。
电解液可进一步包含添加物，例如加速剂(accelerator)、整平剂(leveler)、以及抑制剂(suppressor)。将可作为示例添加物的有机化合物加入电镀浴(electroplatingbath)以作为整平剂，来增加在晶种层204的不同区域上的金属沉积均匀性。这些区域包含晶种层204延伸于开口202侧壁与底部之上的部分、以及晶种层204在开口202之外的部分。整平剂可以是含氮分子。例如聚乙二醇(polyethylene glycol，PEG)，或者可替代的聚烯烃基二醇(Polyalkylene glycol，PAG)，可以做为抑制剂，并且双(3-磺丙基)-二磺酸钠(Bis(3-sulfopropyl)-disodium-sulfonate，C6H12Na2O6S4，SPS)的有机化合物可以作为加速剂。可使用抑制剂来抑制在开口202的侧壁上的镀制。可使用加速剂来加速在开口202底端处的沉积。
在一些实施例中，在导电层144电化学电镀期间，使用大量的整平剂。因此，导电层144可呈现大致平坦顶面、或者至少覆盖开口202的大致平坦顶面。大致平坦顶面延伸横跨开口202边缘，如图2D所示。这可改善导电层144的可靠性，后续将详细说明。
在特定情况下，开口202的宽度大于约25微米，如果整平剂的量不够，则可能以顺应(conformal)的方式沉积导电层。导电层可能无法过量填充开口202，特别是当开口202的宽度大于约25微米。结果，可能于导电层在导电结构122正上方的部分处形成凹陷(recess)。在后续热压缩工艺(例如，与电路板的接合工艺)期间，凹陷可能会成为弱点。导电层可能会在此弱点处裂开，这对于封装结构的性能和可靠性有不利的影响。
相反地，在形成导电层144具有大致平坦上表面的一些实施例中，没有弱点(例如，凹陷或凹形(concave)轮廓)形成。导电层144能支撑后续热压缩工艺造成的应力。这提升封装结构的性能和可靠性。
根据一些实施例，移除遮罩元件206，如图2E所示。可使用剥除(stripping)步骤及/或灰化(ashing)步骤，以移除遮罩元件206。
根据一些实施例，之后，移除晶种层204未被导电层144覆盖的部分，以暴露出绝缘层142a，如图2E所示。可使用蚀刻工艺(例如，湿蚀刻工艺)部分移除晶种层204，以暴露出绝缘层142a。在蚀刻工艺期间，也可些许蚀刻导电层144的表面部分。
第2F-2I和1G图是根据一些实施例，显示形成绝缘层142b和其中一个导电柱146。跟据一些实施例，形成绝缘层142b于绝缘层142a以及导电层144之上，如图2F所示。绝缘层142b可包含或者由一或多聚合物材料形成。聚合物材料可包含聚酰亚胺(PI)、聚苯并恶唑(PBO)、环氧基树脂(epoxy-based resin)、一或多其他适合聚合物材料、或前述的组合。可使用旋转涂布工艺、喷雾涂布工艺、一或多其他适用工艺、或前述的组合，形成绝缘层142b。
在一些实施例中，聚合物材料是光敏感的。因此可使用光刻工艺来形成具有期望图案的开口于绝缘层中。根据一些实施例，形成开口212于绝缘层142b中，以暴露出一部分的导电层144，如图2F所示。可使用光刻工艺形成开口212。在一些实施例中，开口212与开口202未对准。根据一些实施例，开口212与202彼此侧向隔开，而在垂直方向上彼此未重叠，如图2F所示。
根据一些实施例，沉积晶种层214于绝缘层142b和导电层144之上，如图2G所示。晶种层214延伸于开口212的侧壁和底面之上。在一些实施例中，晶种层214以大致顺应方式延伸于开口212的侧壁和底面之上。
晶种层214可以包含或者由金属材料形成。晶种层214可包含或者由钛、钛合金、铜、铜合金、一或多其他适合材料、或前述的组合形成。钛合金或铜合金可进一步含有银、铬、镍、锡、金、钨、一或多其他适合元素、或前述的组合。在一些实施例中，晶种层214是单层。在其他一些实施例中，晶种层214包含多个子层。可使用物理气相沉积(PVD)工艺、化学气相沉积(CVD)工艺、旋转涂布工艺、原子层沉积(ALD)工艺、一或多其他适用工艺、或前述的组合，沉积晶种层204。
根据一些实施例，形成遮罩元件216于晶种层214之上，如图2G所示。遮罩元件216具有开口218，开口218暴露出上方将形成导电柱的晶种层214的一部分。在一些实施例中，遮罩元件216是光敏感层。因此，使用光刻工艺以形成遮罩元件216的开口218，光刻工艺包含曝光步骤和显影步骤。
根据一些实施例，形成导电柱146于开口218中，如图2H所示。导电柱146可包含或者由铜、钴、锡、钛、金、一或多其他适合材料、或前述的组合形成。可使用电镀工艺、无电镀制工艺、一或多其他适用工艺、或前述的组合，形成导电柱146。将导电材料镀在晶种层214的暴露部分上，以形成电性连接至导电层144的导电柱146。
根据一些实施例，移除遮罩元件216，如图2I所示。可以使用剥除步骤及/或灰化步骤，以移除遮罩元件216。
根据一些实施例，之后，移除晶种层214未被导电柱146覆盖的部分，以暴露出绝缘层142b，如图2I所示。可使用蚀刻工艺(例如，湿式蚀刻工艺)部分移除晶种层204，以暴露出绝缘层142b。在蚀刻工艺期间，也可些许蚀刻导电柱146的表面部分。留下的晶种层214与导电柱146共同作为延伸至导电层142b中的导电柱，以与导电层144电性接触。
在一些实施例中，绝缘层142b围绕导电柱146的下部。然而，可对本公开实施例进行许多变化及/或修改。在其它一些实施例中，整个导电柱146放置于绝缘层142b的顶面上方。
在一些实施例中，导电柱146和导电结构122彼此横向隔开，如图2I所示。在一些实施例中，导电柱146和导电结构122彼此未对准。在一些实施例中，导电柱146和导电结构122在导电柱146的垂直延伸方向上彼此未重叠。
根据一些实施例，回头参考图1G，形成导电凸块148于导电柱146之上。在一些实施例中，导电凸块148是焊料凸块。在一些实施例中，导电凸块148包含球栅阵列(ball gridarray，BGA)连接件、焊球、控制倒塌芯片连接件(controlled collapse chip connector)凸块、微凸块(micro bump)、无电镀镍无电镀钯浸镀金(electroless nickel electrolesspalladium immersion gold，ENEPIG)形成的凸块、一或多其他适和连接件、或前述的组合。在一些实施例中，导电凸块148是含锡焊料凸块。含锡焊料凸块可进一步包含铜、银、金、铝、铅、一或多其他适合材料、或前述的组合。在其它一些实施例中，导电凸块148是无铅的。在一些实施例中，可使用焊球放置工艺和热回流(thermal reflow)工艺形成导电凸块148。
可替代地，可施加或电镀含锡材料于导电柱146上。之后，使用热工艺以回流含锡材料，从而形成导电凸块148。在一些实施例中，在移除图2H所示的遮罩元件216之前，施加或电镀含锡材料于导电柱146上。
根据一些实施，上下翻转图1G所示的结构，并将其贴合至胶带载板(tapecarrier)150上，如图1H所示。在一些实施例中，移除晶粒贴合膜、粘着层102和承载基板100。
之后，可使用切割工艺，切穿图1H所示的结构，以成为多个分离的封装结构。在一些实施例中，拾取其中一个封装结构，并放置于电路板152上，如图1I所示。在一些实施例中，电路板152是印刷电路板。在其他一些实施例中，电路板152是接合至其他基板的中介(interposer)基板。在一些实施例中，通过导电凸块148，将封装结构接合至电路板152的导电垫154。
封装结构与电路板152之间的结合可涉及热压缩工艺。在一些实施例中，于高温下，抵靠着电路板施加压应力于封装结构。在一些实施例中，此高温可高于120℃并且低于导电凸块148的熔点。在一些实施例中，此高温可以范围在约120℃至约200℃。在其它一些实施例中，此高温可以范围在约150℃至约180℃。接合工艺所造成的应力可能扩张至导电层144。因为形成导电层144具有大致平坦的顶面，没有弱点(例如凹陷或凹形轮廓)形成。导电层144能支撑结合工艺所造成的应力，而不会损伤。这提升了封装结构的性能和可靠性。
如前所述，在一些实施例中，形成导电层144以具有大致平坦的顶面，以增强导电层144的强度。然而，本公开实施例并不限于此。可以对发明实施例进行各种变化及/或修改。
图3是根据一些实施例显示封装结构的剖面示意图。形成与图2I所示相似的结构。导电层144具有第一部分P1和第二部分P2，如图3所示。第一部分P1-位于导电柱146正下方，而第二部分P2位于导电结构122正上方。在一些实施例中，第二部分P2的顶端高于第一部分P1的顶端。
在一些实施例中，导电层144的第二部分P2具有突出表面。此突出表面可以是曲面。在一些实施例中，此突出表面可以是面上的凸形表面。通过微调形成导电层144的电化学电镀工艺，可形成第二部分P2具有上述轮廓，以增强导电层144的第二部分P2的强度。这可提升导电层144的抗裂能力。
第二部分P2顶端的水平高度比第一部分P1顶端的水平高度(以虚线表示)高出一段高度差H，如图3所示。在一些实施例中，高度差H范围在约0.1微米至约2微米。第一部分P1具有厚度T。厚度T可以范围在约2微米至约7微米。在一些实施例中，高度差H对厚度T的比值(H/T)可以范围在约0.1至约0.5。
可以对发明实施例进行各种变化及/或修改。在其他一些实施例中，第一部分P1与第二部分P2-的水平高度之间没有高度差。在这样的情况下，导电层144可具有大致平坦的顶面。高度差H对厚度T的比值(H/T)大致等于0。
本公开实施例形成封装结构，此封装结构包含导电结构(例如，被保护层围绕的贯孔)以及导电柱。封装结构也包含导电层，导电层形成导电结构与导电柱之间的电连接。通过微调形成导电层的由下而上沉积工艺，形成导电层在导电结构正上方的部分具有大致平坦的顶面或突起表面。因为形成导电层具有上述轮廓，没有弱点(例如凹陷)形成。因此，提升导电层的抗裂能力。导电层能支撑后续工艺(例如，结合工艺)所造成的应力。这改善了封装结构的性能和可靠性。
根据一些实施例，提供封装结构的形成方法。此方法包含形成导电结构于承载基板之上以及设置半导体晶粒于承载基板之上。此方法也包含形成保护层以围绕导电结构与半导体晶粒。此方法也包含形成绝缘层于保护层之上。绝缘层具有开口暴露出导电结构的一部分。开口的宽度大于25微米。此外，此方法也包含形成导电层于绝缘层之上。导电层过量填充开口，且导电层具有大致平坦的顶面。导电层的一部分延伸横跨导电结构的侧壁。在一些实施例中，导电层是使用由下而上沉积工艺形成。在一些实施例中，由下而上沉积工艺是电化学电镀工艺。在一些实施例中，此方法也包含形成导电柱于导电层之上。导电柱电性连接至导电层在一些实施例中，导电柱与导电结构彼此横向隔开，且在导电柱的垂直延伸方向上彼此未重叠。在一些实施例中，使用电化学电镀工艺，形成导电柱于导电层正上方。在一些实施例中，此方法也包含形成含锡焊料元件于导电柱正上方。在一些实施例中，此方法也包含在形成导电柱之前，形成第二绝缘层于导电层之上。导电柱延伸至第二绝缘层中，以与导电层电性接触。在一些实施例中，此方法也包含在形成导电结构之后且在设置半导体晶粒之前，形成重布线结构于承载基板之上。在一些实施例中，此方法也包含设置第二半导体晶粒于承载基板之上、以及在形成重布线结构之前，形成第二保护层于承载基板之上，以围绕第二半导体晶粒。重布线结构延伸横跨第二半导体晶粒与第二保护层之间的界面。
根据一些实施例，提供封装结构的形成方法。此方法包含设置保护层以围绕导电结构和半导体晶粒。此方法也包含形成第一绝缘层于保护层之上。第一绝缘层具有第一开口暴露出导电结构的一部分。此方法也包含使用由下而上沉积工艺，形成导电层于第一绝缘层之上，以过量填充第一开口。导电层的一部分延伸于开口之外，且延伸横跨导电结构的侧壁。此方法也包含形成第二绝缘层于导电层之上。第二绝缘层具有第二开口暴露出导电层的一部分。此方法也包含形成导电柱于导电层自第二开口暴露出来的部分之上。在一些实施例中，此方法也包含在形成导电层之前，形成晶种层于第一开口的侧壁和底面。在一些实施例中，由下而上沉积工艺是电化学电镀工艺。在一些实施例中，此方法也包含形成焊料元件于导电柱之上。在一些实施例中，第一开口与第二开口彼此未对准。
根据一些实施例，提供封装结构。此封装结构包含彼此横向隔开的导电结构与半导体晶粒。此封装结构也包含围绕导电结构和半导体晶粒的保护层。此封装结构也包含位于保护层之上的绝缘层。此封装结构也包含位于绝缘层之上且电性连接至导电结构的导电层。导电层具有大致平坦的顶面。导电层埋入绝缘层中的部分具有大于约25微米的宽度。在一些实施例中，此封装结构也包含位于导电层之上的导电柱。导电柱电性连接至导电层。在一些实施例中，导电柱与导电结构彼此未对准，且在导电柱的垂直延伸方向上彼此未重叠。在一些实施例中，此封装结构也包含位于导电层之上的第二绝缘层。第二绝缘层围绕导电柱的下部。在一些实施例中，此封装结构也包含位于导电柱之上的焊料凸块。
以上概述数个实施例的部件，以便在本公开所属技术领域中技术人员可以更加理解本公开实施例的观点。在本公开所属技术领域中技术人员应理解，他们能轻易地以本公开实施例为基础，设计或修改其他工艺和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本公开所属技术领域中技术人员也应理解，此类等效的结构并无悖离本公开的构思与范围，且他们能在不违背本公开的构思和范围下，做各式各样的改变、取代和替换。因此，本公开的保护范围当视权利要求所界定为准。

Claims (10)

1.一种封装结构的形成方法，包括：
形成一导电结构于一承载基板之上；
设置一半导体晶粒于该承载基板之上；
形成一保护层以围绕该导电结构与该半导体晶粒；
形成一绝缘层于该保护层之上，其中该绝缘层具有一开口暴露出该导电结构的一部分，且该开口的宽度大于25微米；以及
形成一导电层于该绝缘层之上，其中该导电层过量填充该开口，使得该导电层的一部分延伸横跨该导电结构的一侧壁，且该导电层具有大致平坦的一顶面。
2.如权利要求1所述的封装结构的形成方法，其中该导电层是使用一由下而上沉积工艺形成。
3.如权利要求1所述的封装结构的形成方法，还包括：形成一导电柱于该导电层之上，其中该导电柱电性连接至该导电层。
4.如权利要求1所述的封装结构的形成方法，还包括：在形成该导电结构之后且在设置该半导体晶粒之前，形成一重布线结构于该承载基板之上。
5.如权利要求4所述的封装结构的形成方法，还包括：
设置一第二半导体晶粒于该承载基板之上；以及
在形成该重布线结构之前，形成一第二保护层于该承载基板之上，以围绕该第二半导体晶粒，其中该重布线结构延伸横跨该第二半导体晶粒与该第二保护层之间的一界面。
6.一种封装结构的形成方法，包括：
设置一保护层以围绕一导电结构和一半导体晶粒；
形成一第一绝缘层于该保护层之上，其中该第一绝缘层具有一第一开口暴露出该导电结构的一部分；
使用一由下而上沉积工艺，形成一导电层于该第一绝缘层之上，以过量填充该第一开口，其中该导电层的一部分延伸于该开口之外，且延伸横跨该导电结构的一侧壁；
形成一第二绝缘层于该导电层之上，其中该第二绝缘层具有一第二开口暴露出该导电层的一部分；以及
形成一导电柱于该导电层自该第二开口暴露出来的该部分之上。
7.如权利要求6所述的封装结构的形成方法，还包括：在形成该导电层之前，形成一晶种层于该第一开口的侧壁和底面。
8.一种封装结构，包括：
一导电结构与一半导体晶粒，彼此横向隔开；
一保护层，围绕该导电结构和该半导体晶粒；
一绝缘层，位于该保护层之上；以及
一导电层，位于该绝缘层之上且电性连接至该导电结构，其中该导电层具有大致平坦的一顶面，且该导电层埋入该绝缘层中的一部分具有大于约25微米的宽度。
9.如权利要求8所述的封装结构，还包括：一导电柱，位于该导电层之上，其中该导电柱电性连接至该导电层。
10.如权利要求9所述的封装结构，其中该导电柱与该导电结构彼此未对准，且在该导电柱的垂直延伸方向上彼此未重叠。
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