JP2017135237A - Cu配線の製造方法およびCu配線製造システム - Google Patents
Cu配線の製造方法およびCu配線製造システム Download PDFInfo
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- JP2017135237A JP2017135237A JP2016013283A JP2016013283A JP2017135237A JP 2017135237 A JP2017135237 A JP 2017135237A JP 2016013283 A JP2016013283 A JP 2016013283A JP 2016013283 A JP2016013283 A JP 2016013283A JP 2017135237 A JP2017135237 A JP 2017135237A
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
Abstract
Description
最初に、本発明のCu配線の製造方法の一実施形態について図1のフローチャートおよび図2の工程断面図を参照して説明する。
なお、以下の説明において、酸化マンガンはMnO、Mn3O4、Mn2O3、MnO2等の複数の形態をとり得るため、これら全てを総称してMnOxで表す。また、酸化銅もCu2O、CuO等の複数の形態を取り得るため、これらを総称してCuOxで表す。
最初に、バリア膜であるMnOx膜205を形成する工程について説明する。
MnOx膜205は、上述のようにALDにより成膜される。具体的には、マンガン化合物含有ガスおよび酸素含有ガスを用い、処理容器内のパージを挟んで、これらを交互に処理容器内に供給することにより成膜される。
次に、ライナー膜であるCuOx膜206を形成する工程について説明する。
CuOx膜206は、上述のようにCVDまたはALDにより成膜される。具体的には、銅化合物含有ガスおよび酸素含有ガスを用い、CVDの場合はこれらを同時に処理容器内に供給し、ALDの場合は、処理容器内のパージを挟んで、これらを交互に処理容器内に供給することにより成膜される。このように、CuOx膜をCVDまたはALDにより成膜することで、良好なステップカバレッジでライナー膜を形成することができる。また、金属状態のCuを堆積する場合は、凝集の問題が生じやすいが、堆積物が酸化物であるため、スムースな表面とすることができる。
CuOx膜を形成した後、アニール処理を行うことにより、MnOx膜とCuOx膜とが酸化還元反応する。これにより、MnOx膜とCuOx膜との密着性が良好なものとなり、従来のRu膜をライナー膜として用いていた場合のようにMnOx膜をH2ラジカル等で還元する必要なない。また、この酸化還元反応の過程で、CuOxはCuに還元され、配線の一部となる。このため、従来のようなライナー膜であるRu膜が残ることによる配線抵抗の上昇を抑制することができる。このときCuOxの全てがCuに還元されることが好ましいが、必ずしもCuOxの全てが還元されなくてもよい。また、ビアホールの底にライナー膜であるCuOx膜が堆積しても、アニールによってCuに還元されることから、ビア抵抗の上昇を回避することができる。
・ MnO[sl]+0.67CuO[s]=0.33Mn3O4[s]+0.33Cu2O[sl]−27.2(kJ/Mn−mol)・・・反応式1
・ MnO[sl]+0.33Cu2O[sl]=0.33Mn3O4[s]+0.67Cu[sl]−16.1(kJ/Mn−mol)・・・反応式2
・ MnO[sl]+0.33CuO[s]=0.33Mn3O4[s]+0.33Cu[sl]−21.7(kJ/Mn−mol)・・・反応式3
以上のように反応式1〜3のいずれも、ギブスの自由エネルギー変化量はマイナスの値となっており、酸化還元反応が進行し得ることを示しており、この反応によりCuOがCuに還元され得ることを示している。
(1)還元後の膜表面は金属Cuとなることから、その後PVDによって形成されるCuシードとの間に良好な濡れ性を確保することができる。
(2) 還元後の膜表面は金属Cuとなることから、従来のRu膜上と同様に、PVDによるCuドライフィルプロセスを行うことができる。
(3)元のCuOxと、還元されたCuとの境界があいまいになることから、Cu膜の密着性が良好となる。
次に、Cu系膜208を成膜する工程について説明する。
Cu系膜208は、上述したように、ドライプロセスであるPVDにより成膜する。このとき、ウエハにイオンを引き込みながら成膜するiPVDを用いることが好ましい。
次に、本発明の実験例について説明する。
まず、ArアニールまたはH2ラジカル処理によってCuOx/MnOx積層構造のCuOxがCuに還元されるかどうかについて確認した。
図5はArアニールを行ったサンプルのスパッタ時間(深さ方向距離)による各元素の定量値を示す図、図6はArアニールを行ったサンプルのCu/CuOx/MnOx/SiO2積層構造におけるCu2p3/2およびCu LMMのXPSスペクトルを示す図、図7はArアニールを行ったサンプルのCu/CuOx/MnOx/SiO2積層構造におけるMn2pおよびMn3pのXPSスペクトルを示す図、図8はArアニールを行ったサンプルのCu/CuOx/MnOx/SiO2積層構造におけるO1sおよびSi2pのXPSスペクトルを示す図である。
図9はH2ラジカル処理を行ったサンプルのスパッタ時間(深さ方向距離)による各元素の定量値を示す図、図10はH2ラジカル処理を行ったサンプルのCu/CuOx/MnOx/SiO2積層構造におけるCu2p3/2およびCu LMMのXPSスペクトルを示す図、図11はH2ラジカル処理を行ったサンプルのCu/CuOx/MnOx/SiO2積層構造におけるMn2pおよびMn3pのXPSスペクトルを示す図、図12はH2ラジカル処理を行ったサンプルのCu/CuOx/MnOx/SiO2積層構造におけるO1sおよびSi2pのXPSスペクトルを示す図である。
次に、実験例1で用いた2種類(ArアニールおよびH2ラジカル処理)のサンプル、および比較のためライナー膜として従来のCVD−Ru膜(厚さ2.5nm)を形成後にiPVD−Cu膜(厚さ600nm)を形成したサンプルについて、テープテストを行った。
次に、本発明の実施形態に係るCu配線の製造方法の実施に好適な成膜システムについて説明する。図13は本発明の実施形態に係るCu配線の製造方法の実施に好適なCu配線製造システムの概略構成を示すブロック図、図14は図13の成膜システムの主要部となるドライ成膜処理部101の一例を示す平面図、図15は図13の成膜システムの制御部104を示すブロック図である。
エッチングおよびアッシング後のウエハが収容されたキャリアCがドライ成膜処理部101に搬送され、所定位置にセットされる。そしてキャリアCから大気搬送用搬送機構36によりトレンチやビアなどの凹部を有する所定パターンが形成されたウエハWを取り出し、アライメント室34でアライメントを行った後、ロードロック室24aまたは24bに搬送する。そのロードロック室を第2の真空搬送室21と同程度の真空度に減圧した後、第2の搬送機構27によりロードロック室のウエハWを取り出し、第2の真空搬送室21を介してデガス・プリクリーン処理装置14aまたは14bに搬送し、ウエハWのデガス処理またはプリクリーン処理を行う。その後、第1の搬送機構17によりデガス・プリクリーン処理装置14aまたは14bのウエハWを取り出し、第1の真空搬送室11を介してMnOx膜成膜装置12に搬入し、上述したように、ALDによりMnOx膜を成膜し、自己形成バリア膜を形成する。
次に、上記Cu配線製造システム100においてCu系膜成膜装置22およびCuシード形成装置15に好適に用いることができるiPVD装置についてICP(Inductively Coupled Plasma)型プラズマスパッタ装置を例にとって説明する。図16は、ICP型プラズマスパッタ装置を示す断面図である。
次に、上記Cu配線製造システム100に用いられるMnOx膜成膜装置12に好適に用いることができるALD装置について説明する。図17は、ALD装置の一例を示す断面図であり、ALDによりMnOx膜を成膜するものである。なお、このALD装置は、ガス供給系を変更し、圧力調整を行うスロットルバルブを排気管に追加することにより、CVDまたはALDによりCuOx膜を成膜するCuOx膜成膜装置13に用いることも可能である。
次に、上記Cu配線製造システム100に用いられるアニール・H2ラジカル処理装置の例について説明する。
上述したように、アニール・H2ラジカル処理装置は、CuOx膜成膜後のアニール処理を行うものである。単純にアニール処理を行うアニール処理装置、または、アニール処理の際にH2ラジカルによる還元を行うH2ラジカル処理装置からなる。CuOx膜の膜厚が比較的薄い場合にはアニール処理装置を、CuOx膜の膜厚が比較的厚い場合にはH2ラジカル処理装置を用いるなど、適宜使い分けることが可能である。
以上、本発明の実施形態について説明したが、本発明は上記実施形態に限定されることなく種々変形可能である。例えば、ドライ成膜処理部としては、Cu系膜成膜までを図14のような一体となった処理部で行うものに限らず、デガス処理またはプリクリーン処理からMnOx膜成膜処理までの部分と、CuOx膜成膜処理からCu系膜成膜処理に至るまでの処理部に分かれていてもよい。MnOx膜成膜後にウエハを大気に開放したとしても、その後のCuOx膜成膜処理およびアニール処理(H2ラジカル処理)によりその影響をリセットすることが可能なためである。
13;CuOx膜成膜装置
14;アニール・H2ラジカル処理装置
15;Cuシード成膜装置
22;Cu系膜成膜装置
100;Cu配線製造システム
101;ドライ成膜処理部
102;Cuめっき処理部
103;CMP処理部
104;制御部
201;下部構造
202;層間絶縁膜
203;トレンチ
204;ビア
205;MnOx膜
206;CuOx膜
207;Cu膜
208;Cu系膜
209;積み増しCu層
210;Cu配線
W;半導体ウエハ(基板)
Claims (21)
- 表面に所定パターンの凹部が形成された層間絶縁膜を有する基板に対し、前記凹部を埋めてCu配線を製造するCu配線の製造方法であって、
少なくとも前記凹部の表面に、前記層間絶縁膜との反応で自己形成バリア膜となるMnOx膜をALDにより形成する工程と、
前記MnOx膜の表面にライナー膜となるCuOx膜をCVDまたはALDにより形成する工程と、
その後、CuOx膜が形成された基板に対してアニール処理を施し、前記MnOx膜と前記CuOx膜との間で酸化還元反応を生じさせ、前記CuOx膜をCu膜に還元する工程と、
前記CuOxが還元されて形成された前記Cu膜上にCu系膜をPVDにより形成して前記凹部内に前記Cu系膜を埋め込む工程とを有することを特徴とするCu配線の製造方法。 - 前記アニール処理は、前記CuOx膜の還元処理をともなうものであることを特徴とする請求項1に記載のCu配線の製造方法。
- 前記アニール処理の際の前記還元処理は、前記CuOx膜の表面をH2ラジカルで処理するH2ラジカル処理であることを特徴とする請求項2に記載のCu配線の製造方法。
- 前記アニール処理は、100〜400℃の範囲で行われることを特徴とする請求項1から請求項3のいずれか1項に記載のCu配線の製造方法。
- 前記MnOx膜の膜厚は、1〜5nmであることを特徴とする請求項1から請求項4のいずれか1項に記載のCu配線の製造方法。
- 前記CuOx膜の膜厚は、1〜15nmであることを特徴とする請求項1から請求項5のいずれか1項に記載のCu配線の製造方法。
- 前記MnOx膜と、前記CuOx膜とは、同一の処理容器内でALDにより連続して形成されることを特徴とする請求項1から請求項6のいずれか1項に記載のCu配線の製造方法。
- 前記MnOx膜と前記CuOxとの間に、ミキシング層としてCuMnOx膜を形成することを特徴とする請求項7に記載のCu配線の製造方法。
- 前記Cu系膜は、イオン化PVDにより基板温度を230〜350℃にして形成されることを特徴とする請求項1から請求項8のいずれか1項に記載のCu配線の製造方法。
- 前記Cu系膜を形成する工程の後、めっきまたはPVDにより積み増しCu層を形成し、続いて全面を研磨して前記凹部以外の表面の前記Cu系膜および前記MnOx膜を除去する工程をさらに有することを特徴とする請求項1から請求項9のいずれか1項に記載のCu配線の製造方法。
- 表面に所定パターンの凹部が形成された層間絶縁膜を有する基板に対し、前記凹部を埋めてCu配線を製造するCu配線製造システムであって、
少なくとも前記凹部の表面に、前記層間絶縁膜との反応で自己形成バリア膜となるMnOx膜をALDにより形成するMnOx膜成膜装置と、
前記MnOx膜の表面にライナー膜となるCuOx膜をCVDまたはALDにより形成するCuOx膜成膜装置と、
CuOx膜が形成された基板に対してアニール処理を施し、前記MnOx膜と前記CuOx膜との間で酸化還元反応を生じさせ、前記CuOx膜をCu膜に還元するアニール処理装置と、
前記CuOxが還元されて形成された前記Cu膜上にCu系膜をPVDにより形成して前記凹部内に前記Cu系膜を埋め込むCu系膜成膜装置と
を有することを特徴とするCu配線製造システム。 - 前記アニール処理装置は、前記CuOx膜を還元する機能を有するものであることを特徴とする請求項11に記載のCu配線製造システム。
- 前記アニール処理装置の前記還元機能は、前記CuOx膜の表面をH2ラジカルで処理するものであることを特徴とする請求項12に記載のCu配線製造システム。
- 前記アニール処理装置は、アニール処理を100〜400℃の範囲で行うことを特徴とする請求項11から請求項13のいずれか1項に記載のCu配線製造システム。
- 前記MnOx膜成膜装置と前記CuOx膜成膜装置は、共通の処理容器を有する成膜装置として構成され、前記処理容器内の載置台に基板を載置した状態で、前記MnOx膜の成膜と前記CuOx膜の成膜をALDにより連続して行うことを特徴とする請求項11から請求項14のいずれか1項に記載のCu配線製造システム。
- 前記共通の処理容器内で、前記MnOx膜と前記CuOxとの間に、CuMnOx膜を形成することを特徴とする請求項15に記載のCu配線製造システム。
- 前記Cu系膜成膜装置は、イオン化PVDにより基板温度を230〜350℃にして前記Cu系膜を形成することを特徴とする請求項11から請求項16のいずれか1項に記載のCu配線製造システム。
- 前記MnOx膜成膜装置によるMnOx膜の成膜と、前記CuOx膜成膜装置によるCuOx膜の成膜と、前記アニール処理装置によるアニール処理と、前記Cu系膜成膜装置による前記Cu系膜の成膜とを真空を破ることなく実施することを特徴とする請求項11から請求項17のいずれか1項に記載のCu配線製造システム。
- 前記Cu系膜を形成した後、積み増しCu層を形成するCuめっき装置またはCu−PVD装置をさらに有することを特徴とする請求項11から請求項18のいずれか1項に記載のCu配線製造システム。
- 前記積み増しCu層を形成した後、全面を研磨して前記凹部以外の表面の前記Cu系膜および前記MnOx膜を除去する研磨装置をさらに有することを特徴とする請求項19に記載のCu配線製造システム。
- コンピュータ上で動作し、Cu配線製造システムを制御するためのプログラムが記憶された記憶媒体であって、前記プログラムは、実行時に、請求項1から請求項10のいずれかのCu配線の製造方法が行われるように、コンピュータに前記Cu配線製造システムを制御させることを特徴とする記憶媒体。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008124275A (ja) * | 2006-11-13 | 2008-05-29 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2011525697A (ja) * | 2008-03-21 | 2011-09-22 | プレジデント アンド フェロウズ オブ ハーバード カレッジ | 配線用セルフアライン(自己整合)バリア層 |
JP2014036109A (ja) * | 2012-08-08 | 2014-02-24 | Tokyo Electron Ltd | Cu配線の形成方法 |
JP2015177119A (ja) * | 2014-03-17 | 2015-10-05 | 東京エレクトロン株式会社 | Cu配線の製造方法 |
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---|---|---|---|---|
KR20020043464A (ko) * | 2002-03-21 | 2002-06-10 | 김도형 | 반도체소자의 금속배선 형성방법 |
JP5196467B2 (ja) * | 2007-05-30 | 2013-05-15 | 東京エレクトロン株式会社 | 半導体装置の製造方法、半導体製造装置及び記憶媒体 |
JP5417754B2 (ja) | 2008-07-11 | 2014-02-19 | 東京エレクトロン株式会社 | 成膜方法及び処理システム |
JP5429078B2 (ja) * | 2010-06-28 | 2014-02-26 | 東京エレクトロン株式会社 | 成膜方法及び処理システム |
KR101659469B1 (ko) | 2011-06-16 | 2016-09-23 | 도쿄엘렉트론가부시키가이샤 | 반도체 장치의 제조 방법, 반도체 장치, 반도체 장치의 제조 장치 및 기억 매체 |
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2017
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008124275A (ja) * | 2006-11-13 | 2008-05-29 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2011525697A (ja) * | 2008-03-21 | 2011-09-22 | プレジデント アンド フェロウズ オブ ハーバード カレッジ | 配線用セルフアライン(自己整合)バリア層 |
JP2014036109A (ja) * | 2012-08-08 | 2014-02-24 | Tokyo Electron Ltd | Cu配線の形成方法 |
JP2015177119A (ja) * | 2014-03-17 | 2015-10-05 | 東京エレクトロン株式会社 | Cu配線の製造方法 |
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US20170213763A1 (en) | 2017-07-27 |
KR20170089774A (ko) | 2017-08-04 |
US9892965B2 (en) | 2018-02-13 |
KR20180117575A (ko) | 2018-10-29 |
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