CN1452786A - 晶片背面的晶粒黏接材料的预先使用方法及封装组件 - Google Patents

晶片背面的晶粒黏接材料的预先使用方法及封装组件 Download PDF

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CN1452786A
CN1452786A CN00819423A CN00819423A CN1452786A CN 1452786 A CN1452786 A CN 1452786A CN 00819423 A CN00819423 A CN 00819423A CN 00819423 A CN00819423 A CN 00819423A CN 1452786 A CN1452786 A CN 1452786A
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crystal grain
adhesive material
die
wafer
zone
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S·Y·L洪
K·K·何
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Advanced Micro Devices Inc
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Abstract

一种将叠晶晶粒(stacked die)结构的上方晶粒黏接到下方晶粒的方法，此方法不会污染下方晶粒打线垫片，且提供一致的黏接线厚度。本发明的实施例包含将晶粒黏接材料层涂覆于覆晶晶粒封装结构的上方晶粒中，而上方晶粒仍为晶片的型式，且经由将黏滞状态的环氧树脂以旋转或幕涂于晶片的背面，或者是将环氧树脂薄膜叠层于晶片的背面。然后将晶片置于锯带上，而切割该晶粒，其中包含上方晶粒。然后将上方晶粒置于下方晶粒的上方，而熟化环氧树脂。因为在下方晶粒上不会沉积黏滞性的晶粒黏接材料层，晶粒黏接材料不会流入下方晶粒的黏接垫片上。因此，可以减少下方晶粒的尺寸，使得当上方晶粒连接到下方晶粒的上表面时，只曝露出下方晶粒的黏接区域，因此使得叠晶的晶粒尺寸达到最小。另外，经由将上方晶粒的整个晶粒连结区域中覆盖上预定数量的晶粒黏接材料，所以可以小心地控制在上方晶粒及下方晶粒之间的黏接线厚度，而改进可靠度。

Description

晶片背面的晶粒黏接材料的预先使用方法及封装组件
技术领域
本发明涉及在半导体封装中的晶粒黏接，本发明尤其可以应用于制造叠晶晶粒(stacked die)封装结构。
背景技术
由于愈来愈必需将电子组件的尺寸缩小，所以已发展出一般熟知为“叠晶晶粒”(stacked die)的封装结构。在传统的叠晶晶粒封装中，将第一裸半导体芯片称为“晶粒”，如闪存装置，用环氧树脂黏剂黏接到如电路板或导线架的基体上。同样地将如DRAM的第二晶粒黏接于第一晶粒的上表面，由此减少所需要的晶粒表面积。两种晶粒均经附装于各晶粒的曝露周边区域的黏接垫片的连接线(wire bond)而电连接到基体上。
在传统的叠晶晶粒组装技术中，将某一数量的经测量的晶粒黏接材料层，基本上为环氧树脂膏，涂覆于第一晶粒的上表面，而将第二晶粒黏接到第一晶粒的上表面。然后使用一传统的晶粒黏接器将第二晶粒置于该第一晶粒上，使第一晶粒的周边黏接垫片(bonding bad)不为该第二晶粒所覆盖。理想上，该环氧树脂不应涂布超过该第二晶粒的足迹(foot print)之外，以避免污染该第一晶粒的黏接垫片，而确定一预定晶粒黏接材料层的厚度(称为“黏接线厚度”)。黏接线厚度不足将降低成品的可靠度。因此，必需准确地放置环氧树脂，且必需小心地控制所施加的环氧树脂的量。
不理想的是，由于黏滞性的特性，尽管小心地控制，环氧树脂膏仍倾向于涂覆超过第一晶粒的黏接线垫片上的第二晶粒的足迹之外，因此无法适当地黏接。而且，往往各装置各有不同的黏接线的厚度，即基本上黏接线厚度的变化大于1mil时将导致产生可靠度的问题。传统上解决此问题包含方法包含增加下方晶粒的尺寸以允许环氧树脂流动，以防止妨碍黏接垫片，如使第一晶粒上表面上的空间加倍或成为3倍。但是，这是所不希望的，因为增加第一晶粒上表面空间将增加叠晶组件所占据的有价值的“实质”量亦即体积的缘故。另一种方法为在将第二晶粒黏接于第一晶粒前，将环氧树脂涂覆于第二晶粒的背面。但是，这必需增加对于第二晶粒的处理，这将很容易地破坏第二晶粒的上侧，而导致成品的失败及/或产生可靠度的问题。
因此有必要提出一种可以防止晶粒黏接材料层污染到黏接线垫片的组装叠晶封装结构的方法，而提供一方法以改进黏接线厚度的控制，由此提高制造产率及成品的可靠度。
发明内容
本发明的优点为提供一种将叠晶晶粒结构的上方晶粒以晶粒黏接方式连接到下方晶粒的方法，而提供一致的黏接线厚度。
下文的说明可以使本领域普通技术人员了解本发明的其它特征及优点，而可以学习到的实际事项。由所附的权利要求可以更进一步了解及得到本发明的优点。
依据本发明，将上述的优点与其它优点以本发明提出的用于将上半导体晶粒连接到晶粒的方法来实现，其中该方法包含下列步骤：将一晶粒黏接材料层涂覆于一半导体晶片的背面；将一锯带附贴到该晶粒黏接材料层上；切割该晶片及晶粒黏接材料层，以形成多个晶粒，该多个晶粒包含上方晶粒；将上方晶粒置于该基体上；以及熟化该晶粒黏接材料层。
本发明的另一特征为提供一种依据上述方法所产生的半导体封装组件。
本领域熟练技术人员可以由下文中的说明了解本发明其它的优点，但是文中只有说明本发明较佳实施例，而且以示范本发明的最佳模式说明之。但是本发明可以由不同的实施例或在多种不同的关连方面修改实现本发明，因此下文中的附图及说明仅用于说明本发明的范例，而非用于限制本发明。
附图说明
各附图中相同的标示表示相同的组件。
图1A至图1F为依据本发明实施例的方法的各个不同的状态。
图2A为依据本发明实施例的半导体封装组件的侧视图。
图2B为依据本发明实施例的半导体封装组件的顶视图。
具体实施方式
传统上组装叠晶的晶粒封装方法为将用于黏接上方晶粒的黏滞性晶粒连结材料涂覆于下方晶粒上，此方法必需使下方晶粒的面积比上方晶粒的面积大很多，以防止污染到下方晶粒的黏接线垫片，因此限制封装组件小型化的程度。而且，传统技术导致黏接线的不足且厚度不一致，所以对于成品的可靠度产生不良效果。本发明可以解决此类由传统技术所产生的问题。
依据本发明的工艺，将晶粒黏接材料涂覆到叠晶晶粒封装的上方晶粒，而上方晶粒仍为晶片的型式，如将黏滞状态的环氧树脂以旋涂或幕印刷的方式涂覆于晶片的背面，或者是以环氧树脂膜的状态附贴于晶片的背面。然后将晶片安装于锯带上，而切割成为晶粒，其中包含上方晶粒。然后将上方晶粒置于下方晶粒的上方，而熟化环氧树脂以完成该叠晶的晶粒组件。经由将晶粒黏接材料涂覆于上方晶粒上，其中该上方晶粒仍呈晶片的型式，可以避免对于上方晶粒进行额外的处理而破坏上方晶粒的上侧。而且，因为在下方晶粒上不会沉积具有黏滞性的晶粒黏接材料，本发明不会产生晶粒黏接材料层流入下方晶粒的黏接垫片上的问题。所以，可以减少下方晶粒的尺寸，使当上方晶粒连接到下方晶粒的上表面时，只有下方晶粒的线区域曝露出来，因此可以更进一步缩小覆晶的晶粒组件。而且，因为上方晶粒的整个晶粒连结区域被预定量的晶粒黏接材料覆盖，在上方晶粒及下方晶粒之间的黏接线厚度可以被相当细心地控制，而改进产品的可靠度。
下文中将说明本发明技术的实施例，请参考附图1A至图1F。如图1A所示，将一层预定厚度为t的晶粒黏接材料层110，如厚度约0.5mil或更细的环氧树脂，涂覆到半导体晶片100的背面100a。最好晶粒黏接材料层110呈薄膜的型式，如商用的B阶环氧树脂，为日本的Hitachi化学公司或Sumitomo公司所生产。应用传统的成层装置，将环氧树脂薄膜晶粒黏接材料层110以手工或自动成薄层的方式涂覆到晶片100的背面100a，而将该晶片置于与背面100a接触处，然后应用一滚筒进行加热及加压，使之附着到晶片100上，而空气不会陷入薄膜及晶片100之间。在成层后，修剪晶粒黏接材料层110为晶片100的大小。
在本发明的一个替换实施例中，将黏滞状态的晶粒黏接材料经由旋转涂覆方法涂覆于背面110a而形成层110。该旋转涂覆方法包含使用传统方式的旋转型夹头固定晶片100，如在传统的晶片处理技术中，以真空夹头将一Pi覆层涂覆于晶片上表面者。将黏滞性晶粒黏接材料层，如加州Rancho Dominquiez的Ablestic Laboratories所生产的RP598-3B，沉积在晶片100的背面100a的中心，而以旋转该夹头将晶粒黏接材料涂覆到晶片100的边缘。旋转速度，沉积的晶粒黏接材料层的数量及晶粒黏接材料的型式决定晶粒黏接材料层110的厚度t。
在本发明的另一个替换实施例中，将黏滞性晶粒黏接材料经由网版涂覆于背面100a而形成晶粒黏接材料层110。在该网版涂覆方法中，将如加州Rancho Dominquiez的Ablestic Laboratories所生产的RP598-3B置于一细的网版上，如在传统的网版涂覆技术中所使用的。将该网版置于与晶片100的背面100a接触处，而“挤压”晶粒黏接材料将该材料涂覆过背面100a，而形成具有预定厚度t的晶粒黏接材料层110。
现在参考图1B，在将晶粒黏接材料层110涂覆形成后，将传统上使用的锯带120使用传统的技术连接到晶粒黏接材料层110上。然后以传统的方式切割晶片100及晶粒黏接材料层110以形成多个晶粒D，各具有一表面区域a1(参见图1D)，使的锯带120完整如图1C所示。接着，将切割的晶片100带至传统的晶粒黏接器上，从锯带120下方将一针往上推而将晶粒D从锯带120上顶出。然后应用真空夹头捡起晶粒D，而置于如在一叠晶晶粒封装结构中的下方晶粒130(参见图1E)等基体上。
接着参考图1F，最好下方晶粒130中包含周边黏接区130a及中心表面区域130b的表面区域约等于晶粒D的表面区域a1。最好将晶粒D置于下方晶粒130上，使上方晶粒表面区域a1与中心表面区域130b基本上对齐。因此，当将晶粒D置于下方晶粒130的上方时，只曝露出黏接区域130a。在将晶粒D置于下方晶粒之后，熟化晶粒黏接材料层110，最好是在晶粒黏接器处由加热下方晶粒130及晶粒D，由加热器块先部分熟化晶粒黏接材料层110，然后在传统熟化炉中完成熟化晶粒黏接材料层110的操作。
本发明中，经由先涂覆晶粒黏接材料110到晶片100而形成一薄膜，或者是经由网版涂覆作业或旋转操作，而免除晶粒黏接材料层110流入黏接区域130a的可能性，因而可提高产量，且使得下方晶粒130的尺寸可以达到最适化(如最小化)。换言之，下方晶粒的尺寸可设计成使得当上及下方晶粒叠层时，下方晶粒黏接区域130a曝露出来。而且，因为相当小心地控制先涂覆的晶粒黏接材料层110的厚度，所以达到相当一致的预定的黏接线厚度t。(参见图1E)，所以改进成品叠晶晶粒封装结构的可靠度。而且，在晶片100型式时，即先将晶粒黏接材料涂覆于该装置中可以增加产量，且减少成本。
依据本发明实施例生产的半导体封装组件可以参见图2A及图2B。将下半导体晶粒220经由如环氧树脂的晶粒黏接材料层210的第一层连接到基体200上，如一印刷电路板上。该上半导体晶粒240由具有预定厚度t的环氧树脂晶粒黏接材料层230的第二层连接到下方晶粒220的上表面。上半导体晶粒240有一表面区域a1，且下半导体晶粒220有一包含周边黏接区域a2及中心表面区域a3大体上对齐且大体上只曝露出周边黏接区域a2。从而，使下方晶粒220的尺寸达到最小。
本发明可以应用在各种不同类型的半导体封装结构的生产中。本发明的工艺可以使用于任何考虑到空间及/或黏接线的厚度的晶粒黏接应用中，例如本发明可以用于一叠晶的晶粒封装的下方晶粒连接到电路板上，以及将上方晶粒连接到下方晶粒上。
本发明可以使用传统的材料、工艺及装置实现。因此，此材料、装置及工艺在此不予细述。在以前的说明中已提出多种特定的细节，如特定的材料、结构、化学试剂、程序等，以使得本领域普通技术人员可以完全了解本发明。但是，必须了解本发明，而不必一定遵循特定细节即可实现。另一方面，在文中并没有说明熟知的处理结构，其目的在于使本说明书不会对本发明产生不必要的混淆。
上文中仅说明本发明的较佳实施例，而且也只提出少数的例子。虽然文中已应较佳实施例说明本发明，但需要了解的是，本发明可以应用于各种组合及环境中，而且，在不偏离本发明权利要求的范围及精神的情况下，可以对上述实施例加以各种更改及变更。

Claims (12)

1.一种用于连接上半导体晶粒到一基体的方法，该方法包含下列步骤：
将一晶粒黏接材料涂覆于一半导体晶片的背面；
将一锯带附贴于该晶粒黏接材料上；
切割该晶片及晶粒黏接材料层，以形成多个晶粒，该多个晶粒包含上方晶粒；
将上方晶粒置于该基体上；以及
熟化该晶粒黏接材料。
2.如权利要求1所述的方法，其中涂覆晶粒黏接材料层的步骤包含将该晶粒黏接材料的薄膜叠层于该晶片的背面。
3.如权利要求2所述的方法，其中该叠层步骤包含：
配置该薄膜以与该晶片的背面相接触；
加热该薄膜；以及
对该薄膜加压。
4.如权利要求2所述的方法，其中包含在叠层化后，在晶片的周边切割该薄膜。
5.如权利要求1所述的方法，其中的涂覆该晶粒黏接材料的步骤包含在晶片的背面旋转涂覆该晶粒黏接材料。
6.如权利要求1所述的方法，其中的涂覆该晶粒黏接材料层的步骤包含在晶片的背面以网版涂覆该晶粒黏接材料层。
7.如权利要求1所述的方法，其中该上方晶粒具有一表面区域，该基体为一下半导体晶粒，该下半导体晶粒具有一包含周边黏接区域及中心表面区域的表面区域，该中心表面区域约等于该上方晶粒表面区域，该方法包含将该上方晶粒置于该下方晶粒上，使得上方晶粒表面区域及中心表面区域大致上相对齐，且曝露出该周边黏接区域。
8.如权利要求7所述的方法所生产出来的产品。
9.如权利要求1所述的方法，其中将上方晶粒置于在晶粒黏接器处的基体，且该熟化步骤包含：
在晶粒黏接器处加热该基体及上方晶粒以部分熟化该晶粒黏接材料层；以及
在熟化炉中加热该基体及上方晶粒以完全熟化该晶粒黏接材料层。
10.一种半导体封装组件包含：
具有表面区域的上半导体晶粒；以及
下半导体晶粒，具有一表面区域，此表面区域包含周边黏接区域及中心表面区域，该中心表面区域约等于该上方晶粒表面区域；
其中上方晶粒连接到该下方晶粒中，使得上方晶粒表面区域及中心表面区域大致上相互相对齐，且曝露出该周边黏接区域。
11.如权利要求10所述的封装组件，还包含一基体，其中该下方晶粒连接该基体。
12.如权利要求10所述的封装组件，在该上方晶粒及下方晶粒之间包含具有一预定厚度的晶粒黏接材料层。
CN00819423A 2000-04-17 2000-11-17 晶片背面的晶粒黏接材料的预先使用方法及封装组件 Pending CN1452786A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100437990C (zh) * 2005-03-17 2008-11-26 台湾积体电路制造股份有限公司 半导体元件封装构造与晶片接合至封装基板的方法

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JP5019154B2 (ja) * 2006-05-22 2012-09-05 住友ベークライト株式会社 半導体素子の製造方法および半導体パッケージの製造方法
US7422707B2 (en) 2007-01-10 2008-09-09 National Starch And Chemical Investment Holding Corporation Highly conductive composition for wafer coating
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Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
US4688075A (en) * 1983-07-22 1987-08-18 Fairchild Semiconductor Corporation Integrated circuit having a pre-attached conductive mounting media and method of making the same
US4687693A (en) * 1985-06-13 1987-08-18 Stauffer Chemical Company Adhesively mountable die attach film
JPH04247640A (ja) * 1991-02-04 1992-09-03 Matsushita Electron Corp 半導体装置の製造方法
AU4242693A (en) * 1992-05-11 1993-12-13 Nchip, Inc. Stacked devices for multichip modules
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
EP0736225A1 (en) * 1994-10-20 1996-10-09 National Semiconductor Corporation Method of attaching integrated circuit dies by rolling adhesives onto semiconductor wafers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100437990C (zh) * 2005-03-17 2008-11-26 台湾积体电路制造股份有限公司 半导体元件封装构造与晶片接合至封装基板的方法

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