CN100437990C - 半导体元件封装构造与晶片接合至封装基板的方法 - Google Patents

半导体元件封装构造与晶片接合至封装基板的方法 Download PDF

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CN100437990C
CN100437990C CNB2006100653516A CN200610065351A CN100437990C CN 100437990 C CN100437990 C CN 100437990C CN B2006100653516 A CNB2006100653516 A CN B2006100653516A CN 200610065351 A CN200610065351 A CN 200610065351A CN 100437990 C CN100437990 C CN 100437990C
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packaging
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semiconductor element
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CN1848413A (zh
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李新辉
甘万达
李建勋
卢思维
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明是有关于一种用于较佳半导体元件封装的方法与系统。在一例子中，一半导体元件封装构造包括一封装基板；至少一具有晶向(100)的晶片，其设于该基板上并且该封装基板与该晶片之间有电性连接；以及底层填胶，其用来将该晶片接合至该封装基板，该底层填胶的胶层高度小于该晶片至少一边厚度的百分之六十。本发明所提供的这种改善FCBGA工艺的方法，其引入一种新颖的硅晶圆晶体晶向作为集成电路晶片基板，使得FCBGA半导体元件制造可以低成本增进电性、机械与热效能的更佳元件封装设计。

Description

半导体元件封装构造与晶片接合至封装基板的方法
技术领域
本发明涉及一种半导体元件，特别是涉及一种半导体元件封装构造与晶片接合至封装基板的方法。
背景技术
消费性电子产品，例如手机、个人数字助理、数字摄影机等，变得越来越小、越来越快并且越来越聪敏。因此，电子封装与组装的能力必须齐步并进。材料、设备效能与工艺控管的改善正使得更多的公司由标准的表面接着技术(SMT)提升至先进封装技术。大型集成电路的进展使封装技术朝更小尺寸、更高接脚数与更高效能的封装构造发展。对于这些需求，倒装芯片球栅阵列封装构造(FCBGAs)优越的解决方案。FCBGAs的一种利用倒装芯片以及球栅阵列技术的表面接着封装构造。倒装芯片技术用来将半导体晶片接合至封装构造内部的封装基板，而球栅阵列技术的用来将整个封装构造接合至印刷电路板。该封装基板一般包括双马来酰亚胺-三嗪(Bismaleimide-Triazine；BT)树脂、高分子薄片、印刷电路板、陶瓷、玻璃或金属导线架。
该倒装芯片技术的利用倒装芯片微电子组装，其的通过设于倒装芯片晶片焊垫上的导电焊锡突块将面朝下(因此是“翻转的(flipped)”，相较于习用打线接合技术的配置)的电子元件直接电性连接至基板。该些导电焊锡突块(替代焊线)提供电性连接至基板，并且在该晶片与该基板之间提供实际的直立高度(standoff)。相对于其他封装方法，倒装芯片封装具有尺寸降低、效能增加、弹性、可靠以及制造成本低的优点，因此被广泛使用。去除焊线最高可减少95％的必需板面积。倒装芯片技术提供所有封装技术最高速的电性效能。去除焊线可连接的电感与电容降低为十分之一。结果是高速晶片外连接。
此外，倒装芯片提供最大的输入/输出弹性。习用的打线连接受限于晶片的周长。因此，随着连接数的增加，晶片尺寸可能也必须增加用来容许额外的连接。然而，倒装芯片可利用晶片下面的整个区域而在一较小的晶片上容置更多的连接。倒装芯片技术是所有连接方法中最坚固的。倒装芯片连接方法一般是用于自动量产成本最低的连接方法。倒装芯片封装有三个阶段：晶片突块化，将已突块化晶片接合至基板，以及将晶片至基板之间的空间以一不导电材料填满。
球栅阵列技术是用来将半导体元件封装构造接合至一印刷电路板表面(通过设在该半导体元件封装构造底部的锡球)的习用接着连接方案。该导体元件封装构造的外部连接配置成在该封装构造底部的导电接垫。该些导电接垫设有小锡球用来提供连接至一印刷电路板。此种SMT封装有许多优点，例如成本低、高密度输入/输出、使用较小的板面积以及增进的电性、机械与热特性。
这些工艺技术一般需要整体考量硅晶体晶向。特定元件特性视晶体晶格结构而定。每一种晶体晶向具有不同的化学、机械与电子特性，例如氧化、速率、介面密度、结合强度、结合温度、电容与电流。因此，特定工艺技术必须考虑该晶体晶格结构的晶向。
一般用于现有习知FCBGA封装构造的集成电路晶片基板为在(110)平面晶向切割的硅晶晶圆。可被使用的硅晶中有多个晶向平面。这些平面是以米勒指数方法界定，其提供一种用来具体指明硅晶中平面与方向的现有习知方法。以米勒指数分类的常见晶向为(100)、(011)、(110)以及(111)。该晶圆的晶向是通过与晶圆表面平行的晶向平面分类。该表面可能并非精确平行而是有点差异，该差异称为相移角(displacement angle)或分离角(offangle)晶向。晶体晶向与半径之间的关系是以凹口(notch)或平切口(flatcut)标示，并且现代半导体工艺必须考虑技术所附着的晶向。
FCBGA半导体元件制造所要的是可以低成本增进电性、机械与热效能的更佳元件封装设计。
由此可见，上述现有的封装构造在产品结构、制造方法与使用上，显然仍存在有不便与缺陷，而亟待加以进一步改进。为了解决封装构造存在的问题，相关厂商莫不费尽心思来谋求解决之道，但长久以来一直未见适用的设计被发展完成，而一般产品又没有适切的结构能够解决上述问题，此显然是相关业者急欲解决的问题。因此如何能创设一种新的倒装芯片球栅阵列封装构造，便成了当前业界极需改进的目标。
有鉴于上述现有的封装构造存在的缺陷，本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识，并配合学理的运用，积极加以研究创新，以期创设一种新的倒装芯片球栅阵列封装构造中具有晶体晶向(100)的应变硅晶圆，能够改进一般现有的封装构造，使其更具有实用性。经过不断的研究、设计，并经反复试作样品及改进后，终于创设出确具实用价值的本发明。
发明内容
本发明的主要目的在于，克服现有的封装构造存在的缺陷，而提供一种新型结构的倒装芯片球栅阵列封装构造中具有晶体晶向(100)的应变硅晶圆，所要解决的技术问题是使其提供一种改善FCBGA工艺的方法，其引入一种新颖的硅晶圆晶体晶向作为集成电路晶片基板，从而更加适于实用。
本发明的目的及解决其技术问题是采用来下技术方案来实现的。依据本发明提出的一种半导体元件封装构造，其包括：一封装基板；至少一具有晶向(100)的晶片，其设于该封装基板上并且该封装基板与该晶片之间有电性连接；以及底层填胶(underfillfillet)，其是用来将该晶片接合至该封装基板，其中在该晶片的至少一边上，该底层填胶的胶层高度(fillet height)小于该晶片的厚度的百分之六十。
本发明的目的及解决其技术问题还可采用来下技术措施进一步实现。
前述的半导体元件封装构造，其中在该晶片的至少一边上，用来将该晶片接合至该封装基板的底层填胶的胶层高度为该晶片的厚度的百分之三十至百分之六十。
前述的半导体元件封装构造，其中在该晶片的至少一边上，用来将该晶片接合至该封装基板的底层填胶的胶层高度为该晶片的厚度的百分之零点一至百分之四十五。
前述的半导体元件封装构造，其中所述的底层填胶的胶层角度(filletangle)是介于零度与四十五度之间。
前述的半导体元件封装构造，其中所述的底层填胶的胶层角度(filletangle)是介于三十度与六十度之间。
前述的半导体元件封装构造，其中所述的底层填胶是环氧树脂(epoxy)。
前述的半导体元件封装构造，其中所述的底层填胶是环氧树脂-酸酐。
前述的半导体元件封装构造，其中所述的底层填胶是银胶。
前述的半导体元件封装构造，其中所述的底层填胶是由粘附高分子(adhesive polymer)所组成。
前述的半导体元件封装构造，其中所述的底层填胶至少包覆该晶片的一角。
前述的半导体元件封装构造，其中所述的晶片的厚度小于50密耳(千分之一英寸)。
前述的半导体元件封装构造，其中所述的封装基板是选自由高分子薄片、印刷电路板、陶瓷和玻璃材料所组成的一族群。
前述的半导体元件封装构造，其中所述的封装构造为一倒装芯片封装构造或一打线接合封装构造。
本发明的目的及解决其技术问题还采用来下技术方案来实现。依据本发明提出的一种半导体元件封装构造，其包括：一封装基板；至少一具有晶向(100)的晶片，其设于该封装基板上并且该封装基板与该晶片之间有电性连接；及底层填胶，其是用来将该晶片接合至该封装基板，其中在该晶片的该至少一边上，该底层填胶的胶层高度至少为该晶片的厚度的百分之零点一，但不超过该晶片的厚度的百分之六十，其中该底层填胶的胶层角度是介于零度与六十度之间。
本发明的目的及解决其技术问题还可采用来下技术措施进一步实现。
前述的半导体元件封装构造，其中所述的底层填胶至少包覆该晶片的一角。
前述的半导体元件封装构造，其中所述的晶片的厚度小于50密耳(千分之一英寸)。
前述的半导体元件封装构造，其中所述的封装基板是选自由高分子薄片、印刷电路板、陶瓷、双马来酰亚胺-三嗪(Bismaleimide-Triazine；BT)树脂和玻璃材料所组成的一族群。
前述的半导体元件封装构造，其中所述的封装构造为一倒装芯片封装构造或一打线接合封装构造。
本发明的目的及解决其技术问题另外还采用来下技术方案来实现。依据本发明提出的一种用来将一晶片接合至一封装基板的方法，其包括以下步骤：将至少一具有晶向(100)的晶片置放于一封装基板上，该封装基板与该晶片之间有电性连接；以及助焊(fluxing)该晶片与该封装基板；提供一底层填胶接合至该晶片与该封装基板，其中在该晶片的该至少一边上，该底层填胶的胶层高度为该晶片的厚度的至少百分之零点一，但不超过该晶片的厚度的百分之六十，其中该底层填胶的胶层角度是介于零度与六十度之间。
本发明与现有技术相比具有明显的优点和有益效果。由以上技术方案可知，本发明的主要技术内容如下：
在本发明一实施例中，一种新颖的硅晶圆晶体晶向(100)取代习用的硅晶圆晶体晶向(110)作为集成电路晶片基板。由于晶体晶向(100)的晶向，该新颖的硅晶圆晶体晶向(100)可增加在该集成电路晶片基板与封装基板之间的接合附着力。该增加的接合附着力所需的底层填胶工艺要求较低，可增加可靠性，因此成本低。在一实施例中，一半导体元件封装构造包括：一封装基板；至少一具有晶向(100)的晶片，其设于该基板上并且该封装基板与该晶片之间有电性连接；及一用来将该晶片接合至该封装基板的底层填胶，其胶层高度(fillet height)是小于该晶片至少一边厚度的百分之六十。
借由上述技术方案，本发明倒装芯片球栅阵列封装构造中具有晶体晶向(100)的应变硅晶圆至少具有下列优点：
本发明提供一种改善FCBGA工艺的方法，其引入一种新颖的硅晶圆晶体晶向作为集成电路晶片基板，使得FCBGA半导体元件制造可以低成本增进电性、机械与热效能的更佳元件封装设计。
综上所述，本发明新颖的倒装芯片球栅阵列封装构造中具有晶体晶向(100)的应变硅晶圆具有上述诸多优点及实用价值，其不论在产品结构、制造方法或功能上皆有较大改进，在技术上有较大进步，并产生了好用及实用的效果，且较现有的封装构造具有增进的多项功效，从而更加适于实用，并具有产业的广泛利用价值，诚为一新颖、进步、实用的新设计。
虽然本发明已在此例示并描述为，通过使用一种新颖的硅晶圆晶体晶向(100)，来改善集成电路晶片基板与封装基板之间接合附着力的方法，然其并非用来限定本发明于所示的细节，因为其中的各种修改与结构皆可不偏离本发明的精神而在申请专利范围均等的范围与范畴内。而经由后述的特定实施例以及附图，将更了解本发明的结构与运作方法以及另外的目的与优点。
附图说明
图1A是绘示在硅晶圆晶体晶向(100)切割的硅晶圆。
图1B是绘示用于硅晶体平面的四种标准标记。
图2A是绘示根据本发明一实施例的FCBGA装置的剖视图。
图2B是绘示根据本发明一实施例的集成电路晶片与封装基板连接的详细剖视图。
图2C是绘示根据本发明一实施例的FCBGA装置的俯视图。
图3是根据本发明一实施例的简化FCBGA制造流程。
100：硅晶圆          102：平坦端
104：图示            106：图示
108：图示            110：图示
200：FCBGA装置       202：封装基板
204：集成电路晶片    206：电性连接
208：底层填胶        210：晶片基板
212：印刷电路板      214：电性连接
216：晶片厚度        218：胶层角度
222：连接垫          300：流程
304：烘烤工艺        306：倒装芯片接合工艺
312：助焊剂清洁工艺步骤
316：底层填胶工艺步骤
320：安装步骤
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的倒装芯片球栅阵列封装构造中具有晶体晶向(100)的应变硅晶圆其具体实施方式、结构、制造方法、步骤、特征及其功效，详细说明如后。
通过具体实施方式的说明，当可对本发明为达成预定目的所采取的技术手段及功效得一更加深入且具体的了解，然而所附图式仅是提供参考与说明之用，并非用来对本发明加以限制。
本发明提供一种利用新颖的硅晶圆晶体晶向(100)，改善一FCBGA装置的半导体晶片与封装基板间接合附着力的方法。可以理解的是，本发明亦可用于打线接合式封装构造。
请参阅图1A所示为在硅晶圆晶体晶向(100)切割的硅晶圆100。如图1A所示，在该晶圆周边切割有一平坦端102，用来在IC制造时定晶圆的方位。硅晶体晶向在半导体工艺是重要的。特定的元件特性视晶体晶格结构而定。因此，特定工艺技术必须考虑该晶体晶格结构的晶向。米勒指数提供一种用来具体指明硅晶中平面与方向的现有习知方法。典型的硅晶体晶向结构(100)、(110)以及(111)描述于下。
请参阅图1B所示为显示四种硅晶体平面与其标准标记的四个图示104、106、108及110。米勒指数提供一种用来具体指明硅晶中平面与方向的现有习知方法。图示104、106、108及110分别显示四种晶体晶向的单位晶胞。晶体的特征在于在x、y、z方向重复的单位晶胞(结构的微小重复部分)。值得注意的是，四个图示使用相同的x、y、z配置，阴影区域表示晶向平面。
每一种晶体平面晶向可能具有不同的化学、机械与电子特性。例如氧化速率、结合强度、电容、电流、蚀刻速率、结合温度、掺杂浓度或晶体缺陷特性可能依晶体晶向而异。例如晶体晶向(100)的晶圆的蚀刻速率比晶体晶向(111)的晶圆快速百倍，然而晶体晶向(100)的结合温度远低于晶体晶向(110)或(111)的晶圆。此外，晶体晶向(111)的晶圆的氧化速率远较于晶体晶向(100)的晶圆快速。
请参阅图2A所示为根据本发明一实施例的FCBGA装置200的剖视图。该FCBGA装置200是由一具有“倒装芯片”集成电路晶片204的封装基板202所组成，该集成电路晶片204是通过电性连接(例如焊锡突块)206接合至该封装基板202，并且通过一粘着底层填胶208机械接合至该封装基板202。该封装基板可包括双马来酰亚胺-三嗪(Bismaleimide-Triazine；BT)树脂、高分子薄片、印刷电路板、陶瓷、玻璃或其任意组合。该集成电路晶片204是由制造在一晶片基板210上的晶片构件(该集成电路晶片204的内部区域)所组成。与现有习知利用晶体晶向(110)的FCBGA装置不同的是，本实施例是使用晶体晶向(100)。现有习知利用晶体晶向(110)的FCBGA装置易受潜在的机械故障影响，因而影响装置可靠性。该FCBGA装置200是通过设在封装基板202连接垫上的阵列排列的电性连接214，一般为锡球，而连接于一印刷电路板212。
大型集成电路技术的进展使封装技术朝更小尺寸、更高接脚数与更高效能的封装构造发展。倒装芯片球栅阵列封装构造(FCBGAs)这些需求的解决方案。利用封装构造下的区域给阵列排列的电性连接214，可以更有效利用板面积。其可使电性连接214数最大化而不增加封装构造的尺寸。如图2A所示，FCBGA装置可赋予用于高频应用的短电子路径。FCBGA封装构造使具有数以千计焊锡连接的封装构造的PCB安装简单可靠，并且允许所有连接经由一回焊炉一次同时焊接。FCBGA封装构造亦可实现优越的热阻抗值。
现有习知利用晶体晶向(110)的FCBGA装置具有潜在的机械问题。例如，在大型晶片高接脚倒装芯片封装构造存在有两种主要的故障机制：底层填胶与晶片的层裂(delamination)以及晶片破裂。底层填胶层裂一般大部分发生在封装构造回焊至印刷电路板上的时候。如果没有维持完整的粘着，产生之间隙会作为毛细管而可能导致该些焊锡突块间短路。短路会因流体静力压力进一步恶化，因为当倒装芯片接合在封装构造焊与印刷电路板焊接工艺中再度融化时，倒装芯片接合中的低共熔体会膨胀。晶片破裂发生在热循环。由于封装构造的零应力状态大致等同于底层填胶固化温度，破裂将由封装工艺或晶圆工艺导致的起始点累积。利用晶体晶向(100)的晶圆作为晶片基板210的材料可大幅改善集成电路晶片204与封装基板202的附着力，并且大幅降低底层填胶与晶片的层裂与晶片破裂的可能性。相较于晶体晶向(110)的切变强度，晶体晶向(100)可增加晶片基板210与封装基板202之间机械连接的切变强度。利用晶体晶向(110)晶圆上的微脊亦可增加变强度。研究显示，以深反应离子蚀刻在一晶体晶向(100)硅晶圆制成具有圆底面及晶体晶向(110)侧壁的微脊，可获得最高的晶体晶向切变强度。
请参阅图2B所示为利用底层填胶208物理连接集成电路晶片204与封装基板202的详细剖视图。电性连接206在该集成电路晶片204与封装基板202之间提供电性焊锡连接。本发明利用晶体晶向(100)的硅取代习用晶体晶向(110)的硅作为半导体晶片基板210的材料。该集成电路晶片204是由制造在一晶片基板210上的晶片构件(该集成电路晶片204的内部区域)所组成。机械切变强度越高的硅，允许较松弛的底层填胶维持机械接合的要求，而可简化工艺与降低制造成本。例如现有习知使用晶体晶向(110)的硅的封装构造设计，要求底层填胶的胶层高度(fillet height)需超过该集成电路晶片厚度的百分之七十。该晶片厚度包括晶片204与晶片基板210两者的厚度。在图2B中，晶片厚度是以长度216表示。在此实施例中，该晶片总厚度小于50密耳(mil＝千分之一英寸)。该晶体晶向(100)的硅晶圆基板所增加的接合强度使该胶层高度(fillet height)为该晶片厚度的百分之零点一至百分之四十五。在某些案例中，底层填胶的胶层高度为晶片厚度的百分之三十至百分之七十五。该底层填胶至少包覆该晶片的一角。用于晶体晶向(100)硅晶圆的胶层角度(fillet angle)218(介于晶片上表面与晶片侧壁胶表面之间)特定在小于六十度。在一些其他实施例中，胶层角度218介于三十度与六十度之间，而在其他实施例中，是介于零度与四十五度之间。接合材料或该底层填胶208可以是环氧树脂(epoxy)、环氧树脂-酸酐、银胶或任何粘附高分子。
请参阅图2C所示为根据本发明一实施例的FCBGA装置的俯视图220。该底部包括阵列排列的连接垫222，每个连接垫222接合有一锡球214。该些锡球在安装至印刷电路板212时会被加热而提供FCBGA装置200与印刷电路板212之间的电性与机械连接。值得注意的是，如果需要额外的输入/输出线路，其可提供额外的空间而不需增加晶片尺寸。
请参阅图3所示为根据本发明一实施例的简化FCBGA制造流程300。第一步骤为一烘烤工艺304藉此烘干一封装基板302。封装基板302内的外来湿气可能会影响回焊工艺。其亦可能影响底层填胶的固化与后续特性。因此，在封装或底层填胶之前，建议以烘烤移除湿气。
然后该流程进行至一倒装芯片接合工艺306，其包括助焊(fluxing)，晶片置放与回焊步骤，用来将一集成电路晶片308通过复数个焊锡突块310接合至封装基板302。然后该流程进行至助焊剂清洁工艺步骤312，其要完全清洁该集成电路晶片308、封装基板302以及该集成电路晶片308与封装基板302之间的区域(未标示)，以确保移除任何来自助焊剂残留、焊接工艺或在底层填胶与接合步骤前湿气暴露的污染物。可靠的助焊工艺是大量制造的基本。助焊剂的主要功能在于提供一无玷污表面并且在回焊工艺中保持表面洁净。助焊剂亦影响表面张力，因此影响焊锡流动。助焊剂涂布最常用的方法为浸渍助焊与助焊配送。倒装芯片晶片置放准确度一般较打线接合晶片置放方法更严格。具有焊锡突块的晶片必须与基板上的接垫对准。一般而言，大部分的倒装芯片封装工艺需要氮回焊气。
然后该流程进行至一底层填胶工艺步骤316，其是以一底层填胶材料318填满该集成电路晶片308与封装基板302之间，其不仅提供封装构造机械强度，其亦防止水气进入封装构造。典型的底层填胶材料是环氧树脂(epoxy)、环氧树脂-酸酐或高分子。然而底层填胶最重要的功能在于抵销该集成电路晶片308与封装基板302之间的热膨胀不匹配。底层填胶材料318通过将材料机械地结合在一起而吸收热应力。底层填胶工艺对于增加焊锡连接的疲劳寿命是必要的，特别是倒装芯片在有机基板上时。在此步骤中，工艺参数控制使得底层填胶的胶层高度在前述的范围内。
此流程最后步骤为安装步骤320，其是将一个以上的连接模组例如锡球322连接至封装基板302的背侧，用来最终连接至一印刷电路版。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用来限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (19)

1、一种半导体元件封装构造，其特征在于其包括：
一封装基板；
至少一具有晶向(100)的晶片，其设于该封装基板上并且该封装基板与该晶片之间有电性连接；以及
底层填胶，其是用来将该晶片接合至该封装基板，其中在该晶片的至少一边上，该底层填胶的胶层高度，小于该晶片的厚度的百分之六十。
2、根据权利要求1所述的半导体元件封装构造，其特征在于其中在该晶片的至少一边上，用来将该晶片接合至该封装基板的底层填胶的胶层高度为该晶片的厚度的百分之三十至百分之六十。
3、根据权利要求1所述的半导体元件封装构造，其特征在于其中在该晶片的至少一边上，用来将该晶片接合至该封装基板的底层填胶的胶层高度为该晶片的厚度的百分之零点一至百分之四十五。
4、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的底层填胶的胶层角度是介于零度与四十五度之间。
5、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的底层填胶的胶层角度是介于三十度与六十度之间。
6、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的底层填胶是环氧树脂。
7、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的底层填胶是环氧树脂-酸酐。
8、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的底层填胶是银胶。
9、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的底层填胶是由粘附高分子所组成。
10、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的底层填胶至少包覆该晶片的一角。
11、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的晶片的厚度小于50密耳。
12、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的封装基板是选自由高分子薄片、印刷电路板、陶瓷和玻璃材料所组成的一族群。
13、根据权利要求1所述的半导体元件封装构造，其特征在于其中所述的封装构造为一倒装芯片封装构造或一打线接合封装构造。
14、一种半导体元件封装构造，其特征在于其包括：
一封装基板；
至少一具有晶向(100)的晶片，其设于该封装基板上并且该封装基板与该晶片之间有电性连接；以及
底层填胶，其是用来将该晶片接合至该封装基板，其中在该晶片的该至少一边上，该底层填胶的胶层高度至少为该晶片的厚度的百分之零点一，但不超过该晶片的厚度的百分之六十，其中该底层填胶的胶层角度是介于零度与六十度之间。
15、根据权利要求14所述的半导体元件封装构造，其特征在于其中所述的底层填胶至少包覆该晶片的一角。
16、根据权利要求14所述的半导体元件封装构造，其特征在于其中所述的晶片的厚度小于50密耳。
17、根据权利要求14所述的半导体元件封装构造，其特征在于其中所述的封装基板是选自由高分子薄片、印刷电路板、陶瓷、双马来酰亚胺-三嗪树脂和玻璃材料所组成的一族群。
18、根据权利要求14所述的半导体元件封装构造，其特征在于其中所述的封装构造为一倒装芯片封装构造或一打线接合封装构造。
19、一种用来将一晶片接合至一封装基板的方法，其特征在于其包括以下步骤：
将至少一具有晶向(100)的晶片置放于一封装基板上，该封装基板与该晶片之间有电性连接；以及
助焊该晶片与该封装基板；
提供一底层填胶接合至该晶片与该封装基板，其中在该晶片的该至少一边上，该底层填胶的胶层高度为该晶片的厚度的至少百分之零点一，但不超过该晶片的厚度的百分之六十，其中该底层填胶的胶层角度是介于零度与六十度之间。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7585693B2 (en) * 2006-03-31 2009-09-08 Intel Corporation Method of forming a microelectronic package using control of die and substrate differential expansions and microelectronic package formed according to the method
JP5774292B2 (ja) * 2010-11-04 2015-09-09 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 回路装置およびその製造方法
US20130075892A1 (en) * 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
US9991262B1 (en) * 2017-06-15 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device on hybrid substrate and method of manufacturing the same
US10714433B2 (en) * 2018-05-16 2020-07-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959348A (en) * 1997-08-18 1999-09-28 International Business Machines Corporation Construction of PBGA substrate for flip chip packing
CN1244728A (zh) * 1998-04-28 2000-02-16 国际商业机器公司 倒装片电子封装件的柔顺表面层及其制作方法
US6353182B1 (en) * 1997-08-18 2002-03-05 International Business Machines Corporation Proper choice of the encapsulant volumetric CTE for different PGBA substrates
US6417573B1 (en) * 1998-04-08 2002-07-09 Agilent Technologies, Inc. High temperature flip chip joining flux that obviates the cleaning process
CN1452786A (zh) * 2000-04-17 2003-10-29 先进微装置公司 晶片背面的晶粒黏接材料的预先使用方法及封装组件
CN1466213A (zh) * 2002-06-28 2004-01-07 ��Ʒ���ܹ�ҵ�ɷ����޹�˾ 多芯片半导体封装件及其制法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL295293A (zh) * 1962-07-13
US5729045A (en) * 1996-04-02 1998-03-17 Advanced Micro Devices, Inc. Field effect transistor with higher mobility
JP2001326304A (ja) * 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
US20020121663A1 (en) * 2001-03-05 2002-09-05 Semiconductor Components Industries, Llc Semiconductor device and method
US7235433B2 (en) * 2004-11-01 2007-06-26 Advanced Micro Devices, Inc. Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959348A (en) * 1997-08-18 1999-09-28 International Business Machines Corporation Construction of PBGA substrate for flip chip packing
US6353182B1 (en) * 1997-08-18 2002-03-05 International Business Machines Corporation Proper choice of the encapsulant volumetric CTE for different PGBA substrates
US6417573B1 (en) * 1998-04-08 2002-07-09 Agilent Technologies, Inc. High temperature flip chip joining flux that obviates the cleaning process
CN1244728A (zh) * 1998-04-28 2000-02-16 国际商业机器公司 倒装片电子封装件的柔顺表面层及其制作方法
CN1452786A (zh) * 2000-04-17 2003-10-29 先进微装置公司 晶片背面的晶粒黏接材料的预先使用方法及封装组件
CN1466213A (zh) * 2002-06-28 2004-01-07 ��Ʒ���ܹ�ҵ�ɷ����޹�˾ 多芯片半导体封装件及其制法

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