CN108074875A - 半导体器件封装及制造其之方法 - Google Patents

半导体器件封装及制造其之方法 Download PDF

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CN108074875A
CN108074875A CN201710334218.4A CN201710334218A CN108074875A CN 108074875 A CN108074875 A CN 108074875A CN 201710334218 A CN201710334218 A CN 201710334218A CN 108074875 A CN108074875 A CN 108074875A
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carrier
hole
sealant
chamber
semiconductor packages
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房昱安
陈盈仲
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明提供一种半导体器件封装，其包括一载体、一盖、一电子部件和一密封剂。该载体具有一第一表面和与该第一表面相对的一第二表面，且限定从该第一表面延伸到该第二表面的一孔。该盖附接到该载体的该第一表面。该盖和该载体限定一腔室。该电子部件附接到该载体的该第一表面且设置在该腔室中。该密封剂附接到该载体的该第二表面并覆盖该孔。

Description

半导体器件封装及制造其之方法
技术领域
本发明涉及一种半导体器件封装。更特定来说，本发明涉及包括一盖的一半导体器件封装及制造其之方法。
背景技术
在半导体器件封装中，使用盖来保护衬底上的裸片和其它电子器件免受湿气、灰尘、微粒等的影响。盖子通过胶水附接到衬底上以形成半导体器件封装。然而，由于热循环引起的爆米花效应(pop-corn effect)(例如，可以加热半导体器件封装以固化盖子和衬底之间的胶水)，盖子可能与衬底分离(detached)。
发明内容
在某些实施例中之一方面，一种半导体器件封装，其包括一载体、一盖、一电子部件和一密封剂。该载体具有一第一表面和与该第一表面相对的一第二表面，且限定从该第一表面延伸到该第二表面的一孔。该盖附接到该载体的该第一表面。该盖和该载体限定一腔室。该电子部件附接到该载体的该第一表面且设置在该腔室中。该密封剂附接到该载体的该第二表面并覆盖该孔。
在某些实施例中之一方面，一种制造一半导体器件封装的方法，其包括：(a)提供一载体，其限定一通孔；(b)将一电子部件附接到该载体；(c)将一盖附接到该载体以覆盖该电子部件并且与该载体限定一腔室；且(d)在该载体上施加一密封剂材料以覆盖该通孔。
在某些实施例中之一方面，一种制造一半导体器件封装的方法，其包括：(a)提供一第一载体，其限定一通孔；(b)将一电子部件附接到该第一第一载体；(c)将一盖附接到该第一载体以覆盖该电子部件并且限定具有该第一载体的一腔室；(d)在该第一载体上施加一密封剂材料以覆盖该通孔；和(e)在该腔室内产生比环境空气压力更小的一空气压力。
附图说明
图1是根据本发明的一些实施例的半导体器件封装的截面图。
图2是根据本发明的一些实施例的另一半导体器件封装的截面图。
图3A、图3B、图3C、图3D、图3E及图3F示出了根据本发明的一些实施例的制造一半导体器件封装的方法。
贯穿图式及详细描述使用共同参考数字以指示相同或类似元件。本发明的实施例将从结合附图进行的以下详细描述更显而易见。
具体实施方式
本发明中描述了用于改进半导体器件封装的盖的附接的技术。而且，这些技术可以避免由于热循环引起的爆米花效应，使盖子与衬底分离。
相对于某一组件或组件的群组或组件或组件的群组的某一平面而指定空间描述，例如“之上”、“之下”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧”、“更高”“下部”、“上部”、“上方”、“下方”等，以用于定向如相关联图中所展示的组件。应理解，本文中所使用的空间描述仅是出于说明的目的，且本文中所描述的结构的实际实施可以任何定向或方式在空间上布置，其限制条件为本发明的实施例的优点是不因此布置而有偏差。
图1是根据本发明的一些实施例的半导体器件封装1的截面图。半导体器件封装1包括载体10、盖40、接合线22、电子部件20和21、垫50、密封剂70、焊球垫52、表面贴装技术(SMT)垫54和粘合层30。图1所示的半导体器件封装1是在分割之前形成在面板(panel)上的一例示单元，并且面板包括多个这样的单元。
载体10具有上表面101和与上表面101相对的下表面102。在一些实施例中，载体10可包括硅、陶瓷材料、有机材料(例如双马来酰亚胺-三嗪(bismaleimide-triazine(BT)或玻璃增强环氧材料(例如FR-4))或另一种合适的材料。通孔60从载体10的上表面101形成并延伸到下表面102。在一些实施例中，金属层可以设置在通孔60的侧壁上。在一些实施例中，通孔60的侧壁可以省略设置在其上的金属层。尽管在图1中未示出，预期载体10可以包括电路，例如包括导电迹线、垫、通孔等的再分布结构。
盖40经由粘合层30或经由焊接附接到载体10的上表面101。盖40和载体10一起限定了腔室A，盖40和载体10可以被粘合层30密封或经由焊接密封，并且密封可以是气密密封(hermetic seal)。气密密封可以经由金属接合、玻璃熔块(glass frit)，阳极接合、共晶键合(eutectic bonding)或熔融接合(fusion bonding)形成。在半导体器件封装1的制造过程期间，粘合层30经由加热操作从例如凝胶(gel)、胶水(glue)或其它粘合材料固化。
电子部件20和21(例如，半导体裸片、无源部件等)设置在上表面101上。电子部件20和21设置在腔室A中。接合线22将电子部件20和21電连接到载体10的电路。在一些实施例中，接合线22可以包括金(Au)、铜(Cu)或另外合适的导电材料。
垫50设置在载体10的下表面102上。焊球垫52形成在下表面102上，且垫54形成在下表面102上。垫50围绕通孔60。垫50具有或限定与通孔60连通的通孔62。垫50具有或限定与通孔60对准的通孔62。垫50具有圈形或环形(ring or an annular shape)。在一些实施例中，环形垫50可包括Cu-Pd(钯)-Au、Cu、镍(Ni)、Pd、Au或其组合或其它合适的材料。
密封剂70可以包括但不限于例如焊料，其可以包括锡(Sn)、锡-银(SnAg)、锡-银-铜(SnAgCu)或其它合适的材料。密封剂70设置在垫50上。接合部件72可以包括但不限于例如焊料，其可以包括Sn或SnAg、SnAgCu或其它合适的材料。在一些实施例中，接合部件72(例如，焊球)可以设置在焊球垫52上。在一些实施例中，密封剂70和接合部件72可以包括相同的材料。
垫50设置在密封剂70和载体10的下表面102之间。与垫50相邻的密封剂70的横向尺寸(例如，宽度)大于通孔62的横向尺寸(例如，宽度)，并且大于通孔60的横向尺寸(例如，宽度)。在一些实施例中，密封剂70实质上覆盖通孔62的开口的整体，且实质上覆盖通孔60的开口的整体。密封剂70密封通孔60和62。密封剂70气密地密封(hermetically seals)通孔60和62。密封剂70可以保护电子部件20和21(其位于腔室A中)不受损坏或污染(例如，颗粒、湿气等)。
密封剂70包括延伸到通孔60中的突起(protrusion)71。突起71具有弯曲或弧形的端部。突起71气密地密封通孔60。腔室A中的压力可能相对低于环境空气压力，并且腔室A中的压力可以避免在制造过程中的各种热循环期间的爆米花效应。
在一些实施例中，电子部件28(例如，无源部件)设置在载体10的下表面102上并且电连接到垫54。无源部件28的厚度和密封剂70的厚度可以小于接合部件72的厚度，使得当半导体器件封装1已经藉由接合部件72接合到母板(mother board)时，无源部件28和密封剂70将被容纳在由接合部件72、载体10和母板(未示出)限定的空间中。在一些实施例中，半导体器件封装1中的电子部件20和21可以与空气/外部环境隔离。在传送过程(deliveryprocess)中，可以使用半导体器件封装1的结构来保护电子部件20和21免受可能导致半导体器件封装1的灵敏度降低的湿气、灰尘、颗粒等的影响。
图2是根据本发明的一些实施例的另一半导体器件封装2的截面图。除了载体10'包括凹陷部分(recessed portion)之外，半导体器件封装2的结构在某些方面与半导体器件封装1的结构类似。图2所示的半导体器件封装2是在分割之前形成在面板上的例示单元，且面板包括多个这样的单元。
载体10'可包括陶瓷衬底(ceramic substrate)。盖40'覆盖载体10'的凹陷部分。盖40'可以包括硅、玻璃或其它合适的材料。盖40'和载体10'可以藉由粘合层30或藉由焊接来密封，且密封可以是气密密封。气密密封可以藉由金属接合、玻璃熔块、阳极结合，共晶键合或熔融接合形成。
通孔60从载体10'的上表面101'形成并延伸到下表面102'。金属层52包括三个部分，其中第一部分521设置在载体10'的上表面101'上、第二部分522设置在载体10'的侧壁上、第三部分523设置在载体10'的下表面102'。密封剂70覆盖第一部分521、第二部分522和第三部分523。
当半导体器件封装2已经藉由接合部件72而接合至母板时，无源部件28和密封剂70可以容纳在由接合部件72、载体10'和母板(未示出)所限定的空间中。在一些实施例中，半导体器件封装2中的电子部件20和21可以与空气/外部环境隔离。在传送过程中，可以使用半导体器件封装2的结构来保护电子部件20和21免受可能导致半导体器件封装2的灵敏度降低的湿气、灰尘、微粒等的影响。
图3A-3F示出了根据本发明的一些实施例的制造一半导体器件封装1的方法。参考图3A，提供了载体10。载体10具有表面101和与表面101相对的表面102。在一些实施例中，载体10可以包括硅、陶瓷材料、有机材料(例如BT或FR-4)或另外合适的材料。焊球垫52形成在表面102上。垫53形成在表面102上。
通孔60从载体10的表面102形成并延伸到表面101。通孔60藉由机械钻孔技术(machine drilling techniques)或激光钻孔技术形成。藉由电镀技术在载体10的表面102上形成环形垫(annular pad)50。环形垫50具有表面501并且围绕通孔60的开口。环形垫50具有或限定藉由机械钻孔技术或激光钻孔技术形成的通孔62。通孔62与通孔60连通。在一些实施例中，环形垫50可以包括Cu-Pd-Au、Cu、Ni、Pd、Au或它们的组合、或其它合适的材料。在一些实施例中，焊料掩模层(solder mask layer)(未示出)可以覆盖环形垫50。在一些实施例中，环形垫50可以形成并延伸以覆盖载体10的表面101的一部分、通孔60的侧壁和载体10的表面102的一部分。
参考图3B，电子部件20和21附接到载体10的表面101。接合线22电连接到电子部件20和21。每个接合线22的一端部附接到载体10的表面101，且接合线22的另一端部附接到相应的电子部件20或21。
参考图3C，盖40经由粘合层30附接到载体10的表面101，以覆盖电子部件20和21。盖40与载体10限定腔室A。在半导体器件封装1的制造过程的一个热循环期间，粘合层30经由加热过程从例如凝胶、胶水或其它粘合材料固化。在一些实施例中，粘合层30的粘合材料可以被金属接合、玻璃熔块、阳极结合，共晶键合或熔融接合取代。
参考图3D，密封材料70'(例如，焊料)被施加在环形垫50的表面501上并且覆盖通孔60和62。在一些实施例中，密封材料70'可以是包括Sn或其它合适材料的焊料。焊膏74可以藉由丝网印刷技术(screen printing techniques)施加在垫53上。密封材料70'和焊膏74可以施加在相同的阶段(stage)中，并且可以藉由丝网印刷技术施加在环形垫50和垫53上。
参考图3E，无源部件28藉由表面贴装技术(SMT)设置在焊膏74上。在无源部件28设置在垫53上之后，对图3E所示的结构进行加热操作。向密封材料70'施加助熔剂(flux)以帮助密封材料70'熔化。密封材料70'在加热操作期间软化。在加热操作期间，腔室A中的空气将膨胀；因此，腔室A中的压力大于外部空气压力。被加热的腔室A中的空气可以膨胀以穿过密封材料70'以形成通孔64。通孔60、62和64可允许部分膨胀的空气离开腔室A。由于密封材料70'处于熔融状态(molten state)并且处于液态，所以可以通过通孔60、62和64将腔室A中的空气驱逐或排出(expelled or vented out)腔室A。
在加热操作期间，从腔室A藉由通孔60、62和64释放的空气可以避免爆米花效应。由于热循环期间的膨胀空气藉由通孔60、62和64释放以避免爆米花效应，因此盖40和载体10之间的接合可能不会受到损害。由于载体10、垫50和密封材料70'的结构特征，因此盖40和载体10之间的接合可能不会损坏。
参考图3F所示，当腔室A中的空气很少或没有空气经由密封材料70'出来时，密封材料70'的形状可以改变为密封70”的形状，例如圆形或半球形(round or hemisphericalshape)。当加热温度达到约260℃至280℃时，密封材料70'可以改变为密封70”的形状，例如圆形或半球形。接合部件72形成在焊球垫52上。无源部件28、焊膏74和垫53的总厚度可以小于接合部件72的厚度。由于金属润湿(metal wetting)，焊膏74与垫53结合而形成SMT垫54。
密封剂70”覆盖或密封通孔60和62。当冷却操作期间温度下降时，腔室A中的空气压力小于外部空气压力(例如，在腔室A中产生较小的压力)。当温度下降时，密封剂70”变得固化(solid)，并且由于腔室A中的相对较小的空气压力，密封剂70”的一部分可以被吸入到通孔60和62中以形成突起71以形成如图1所示的半导体器件封装1。由于固体密封剂70”的覆盖，外部空气因此不能进入腔室A。
在密封剂70”固化之后，将半导体器件封装1对空气/外部环境密封。半导体器件封装1可以通过焊接部件72的回流(reflowing)而附接到母板。由于在回流阶段不对密封剂70”施加助熔剂，并且密封剂70”在其表面上具有氧化物，因此密封剂70”的熔点大于接合部件72的熔点。因此，在回流阶段期间，密封剂70”不熔化，使得半导体器件封装1保持对空气/外部环境的密封。
可以设想，半导体器件封装1可以附接到另一个载体(例如图中未示出的系统板)，并且半导体器件封装1可以进行另一个加热操作。在将半导体器件封装1附接到系统板的操作中，腔室A中的空气(其具有相对较低的压力)被加热。在将半导体器件封装1附接到系统板的操作中，腔室A中的空气(其具有相对较低的压力)的膨胀被补偿。藉由腔室A中的相对较低的压力来避免爆米花效应。
此外，半导体器件封装1在面板的分割操作期间保持对空气/外部环境的密封。此外，在随后的包装阶段和随后的传送过程中，半导体器件封装1保持对空气/外部环境的密封(例如，气密密封的状态)，并且不会由于随后的传送过程而被损坏。
如图2所示，类似的方法可用于制造半导体器件封装2，其中在设置在载体10'的上表面101'上的金属层52的第一部分521和位于载体10'的下表面102'上的金属层52的第三部分523两者上施加密封材料。
如本文所使用的，单数术语“一”，“一个”和“该”可以包括复数指示物，除非上下文另有明确指示。
如本文中所使用，词语“近似地”、“大体上”、“实质的”及“约”用以描述及说明小变化。当与事件或情形结合使用时，所述词语可指事件或情形明确发生的情况及事件或情形极近似于发生的情况。举例来说，当结合数值使用时，所述词语可指小于或等于彼数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，则可认为所述两个数值“大体上”相同。
在一些实施例的描述中，在另一部件“上”或“上方”提供的部件可包括前一部件直接在后一部件上(例如，实体或直接接触)的情况，以及其中一个或多个中间部件位于前部部件和后部部件之间的范例。
另外，有时在本文中按范围格式呈现量、比率及其它数值。应理解，此类范围格式是为便利及简洁起见而使用，且应灵活地理解为不仅包含明确指定为范围极限的数值，且还包含涵盖于彼范围内的所有个别数值或子范围，就如同明确指定每一数值及子范围一般。
尽管已参考本发明的特定实施例描述并说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员应理解，在不脱离如由所附权利要求书界定的本发明的真实精神及范畴的情况下，可作出各种改变且可用等效物取代。说明可不一定按比例绘制。归因于工艺及容限，本发明中的艺术再现与实际装置之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性而非限制性的。可作出修改，以使特定情形、材料、物质组成、方法或工艺适应于本发明的目标、精神及范畴。所有所述修改均意欲处于此处随附的权利要求书的范畴内。尽管已参看按特定次序执行的特定操作描述本文中所揭示的方法，但应理解，在不脱离本发明的教示的情况下，可组合、再分或重新定序这些操作以形成等效方法。因此，除非本文中具体指示，否则操作的次序及分组并非对本发明的限制。

Claims (20)

1.一种半导体器件封装，其包括：
一载体，其具有一第一表面和与该第一表面相对的一第二表面，且限定从该第一表面延伸到该第二表面的一孔；
一盖，其附接到该载体的该第一表面，该盖和该载体限定一腔室；
一电子部件，其附接到该载体的该第一表面且设置在该腔室中；和
一密封剂，其附接到该载体的该第二表面并覆盖该孔。
2.根据权利要求1所述的半导体器件封装，其中该密封剂包括该孔内的一突起。
3.根据权利要求2所述的半导体器件封装，其中该突起包括一弯曲或弧形端部。
4.根据权利要求1所述的半导体器件封装，其中该密封剂具有一宽度大于该孔的一宽度。
5.根据权利要求1所述的半导体器件封装，进一步包括围绕该载体的该第二表面上的该孔的一垫，其中该垫设置在该密封剂和该载体的该第二表面之间。
6.根据权利要求5所述的半导体器件封装，其中该垫限定一孔，且该密封剂具有一宽度大于由该垫限定的该孔的一宽度。
7.一种制造一半导体器件封装的方法，其包括：
(a)提供一载体，其限定一通孔；
(b)将一电子部件附接到该载体；
(c)将一盖附接到该载体以覆盖该电子部件并且与该载体限定一腔室；和
(d)在该载体上施加一密封剂材料以覆盖该通孔。
8.根据权利要求7所述的方法，其进一步包括(e)执行一加热操作。
9.根据权利要求8所述的方法，其中(e)包括向该密封剂材料施加一助熔剂(flux)。
10.根据权利要求8所述的方法，其中该密封剂材料在该加热操作期间软化，且该腔室中的空气经由形成在该软化的密封剂材料中的一孔而从该腔室排出。
11.根据权利要求8所述的方法，其中由该密封剂材料形成一密封剂密封该通孔。
12.根据权利要求8所述的方法，其进一步包括(f)执行一冷却操作(coolingoperation)。
13.根据权利要求12所述的方法，其中该密封剂材料被拉入到(f)中的该通孔中以密封该通孔。
14.根据权利要求7所述的方法，其进一步包括在(d)之前，在该载体上形成围绕该通孔的一垫。
15.根据权利要求14所述的方法，其中在(d)中将该密封剂材料施加到该垫上。
16.一种制造一电子设备的方法，其包括：
(a)提供一第一载体，其限定一通孔；
(b)将一电子部件附接到该第一第一载体；
(c)将一盖附接到该第一载体以覆盖该电子部件并且限定具有该第一载体的一腔室；
(d)在该第一载体上施加一密封剂材料以覆盖该通孔；和
(e)在该腔室内产生比环境空气压力更小的一空气压力。
17.根据权利要求16所述的方法，其中(e)包括执行一第一加热操作。
18.根据权利要求17所述的方法，其中其中(e)进一步包括在该第一加热操作之后执行一冷却操作。
19.根据权利要求17所述的方法，其中执行该第一加热操作包括向该密封剂材料施加一助熔剂。
20.根据权利要求17所述的方法，其进一步包括(f)藉由执行一第二加热操作将该第一载体接合到一第二载体。
CN201710334218.4A 2016-11-09 2017-05-12 半导体器件封装及制造其之方法 Pending CN108074875A (zh)

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