CN1244728A - 倒装片电子封装件的柔顺表面层及其制作方法 - Google Patents

倒装片电子封装件的柔顺表面层及其制作方法 Download PDF

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CN1244728A
CN1244728A CN99104390A CN99104390A CN1244728A CN 1244728 A CN1244728 A CN 1244728A CN 99104390 A CN99104390 A CN 99104390A CN 99104390 A CN99104390 A CN 99104390A CN 1244728 A CN1244728 A CN 1244728A
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米格尔·A·吉姆雷斯
埃里克·A·约汉森
李力
简·奥伯鲁兹
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GlobalFoundries Inc
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Abstract

倒装片电子封装件配备有通常位于底部填充层和诸如芯片载体或印刷电路板或卡之类的衬底之间的柔顺表面层,这降低了芯片和衬底之间热膨胀系数差异引起的应力和应变。储存模数应该小于衬底模数一半(最好在大约50000psi－20000psi之间)的柔顺层可以包含诸如硅酮之类的橡胶材料、诸如聚四氟乙烯之类的粘塑性聚合物或互穿聚合物网络(IPN)。用作焊料标记的光敏IPN最好。

Description

倒装片电子封装件的柔顺表面层及其制作方法
本发明涉及到电子封装件，更确切地说是涉及到借助于使芯片及安装芯片的衬底的热膨胀差异相互适应而改进倒装片连接的可靠性的方法与装置。
集成电路(IC)芯片或模块利用通常称为C4(可控崩塌芯片连接)或倒装片固定工艺连接于芯片载体，有时直接连接于PC板或卡上。小的焊料突块或球制作在芯片的有源表面上。然后将芯片倒转(因此称为“倒装片”)并置于要被固定于其上的载体、板或其它衬底上。各个元件被加热，使焊料在可控的崩塌过程中回流，从而实现芯片与衬底之间的电连接。此工艺在连接紧凑、电性能及成本方面都有许多优点，使其成为工业标准之一。但也存在一些缺点，妨碍了其更广泛的应用。
一个更为明显的缺点来自芯片与衬底热膨胀系数(CTE)之间的差异。诸如硅、锗和砷化镓之类的普通芯片材料通常具有约为3-6ppm/℃的CTE。安装芯片的有机芯片载体以及通常为有机介电质和金属电路的复合物的有机印刷电路板，多半具有约为12-20ppm/℃的CTE。当这些元件被加热和冷却时，衬底比芯片膨胀和收缩大得多。对于简单的芯片与衬底连接，来自不同膨胀的应变主要被柔软的焊料吸收。随着反复的热循环(这对许多电子元件来说是不可避免的)，焊料连接很可能失效。
解决此问题的常规方法是用CTE与焊料连接相匹配或接近的(通常约为22-28ppm/℃)介电质底部填充材料来环绕焊料连接。典型的底部填充材料是环氧基酐系。它们通常被二氧化硅之类的材料的极细小颗粒高浓度填充以得到所希望的CTE。此填料也使底部填充物具有通常大于2GPa或300ksi的高的模数(此处所用术语“模数”表示储存模数)。低部填充物承受了芯片与衬底不同膨胀所引起的大部分负荷，从而减小了焊料连接上的应变。但由于限制了芯片与衬底之间的不同的膨胀，芯片与载体之间比较强的耦合就倾向于使芯片和载体二者都弯曲。这增大了垂直于安装载体的衬底表面而作用的负荷。例如，当在载体被固定在通常具有BGA上的焊料球阵列的印刷电路板或卡之后封装件冷却时，芯片和载体倾向于在中部向上拱起，这在载体与印刷电路板或卡之间阵列的中央处的球上产生张力。这会导致BGA的早期失效。
为了缓解这些问题，进行过各种尝试，包括在多层有机印刷电路板或卡中的具有所希望的CTE的加强肋和柔顺材料层。但加强肋昂贵，而印刷电路板中的柔顺层在镀敷的通孔(PTH)穿处引起应力集中，形成切形变。于是就需要可靠而价廉的方法来适应芯片与诸如芯片载体和印刷电路板之类的电路化有机衬底之间的不同的热膨胀。
本发明的封装件和方法调节芯片与用置于芯片和衬底之间的柔顺材料层安装芯片的有机介电质载体、印刷电路板或其他衬底之间的CTE差异。芯片与衬底之间的焊料连接延伸通过此柔顺层，此柔顺层通常与常规底部填充物一起使用。柔顺层位于底部填充物与衬底之间，且其模数应该小于底部填充物模数的大约一半。一般希望柔顺材料的模数小于大约100000psi，模数大约为20000-50000psi的材料更好。
在芯片和衬底的热循环过程中，柔顺层的一侧与底部填充物的运动一致，而其另一侧与衬底的运动一致。这样，柔顺层就降低了芯片与衬底之间的耦合，从而减小了它们的弯曲。各种柔顺的介电质都可用作柔顺层，包括硅酮之类的橡胶材料以及聚四氟乙烯之类的粘塑性聚合物。用作完成焊料连接的掩模的光敏互穿聚合物网络则更好。
从下列描述中，本发明的其他优点将更为明显。
图1和2是现有技术电子封装件的示意剖面图。
图3是体现本发明的电子封装件的示意剖面图。
图4试验数据图示出了标准封装件和具有本发明柔顺层的封装件的曲率对温度的关系。
图1示出了一般示为10的常规电子封装件，它具有一个用C4连接方法连接于电路化载体22的裸芯片12。正如C4工艺常做的那样，焊料突块即焊料球16固定于集成电路芯片或模块12上的接触14，芯片倒转过来，使接触14处于顶部。然后将芯片倒扣于所示位置，而且使焊料球16对准于电路化载体22上的接触24。再对此封装件进行加热以回流焊料球16，从而在芯片12和载体22之间完成C4连接。载体中的常规电路(未示出)将载体顶部上的接触24连接到载体底部上的第二组接触26。比将芯片10固定于载体的焊料球16稍大的第二组焊料球28，被固定于载体下方的接触26。通常称为球栅阵列即BGA的这种焊料球阵列28，将接触26连接于印刷电路板、卡或其他衬底32上的接触34。可以选择BGA球28中的焊料以便在低于C4焊料球16中的焊料的温度下熔化，使芯片和载体能够固定于衬底32而不影响C4连接。
硅、锗和砷化镓之类的常规芯片材料的热膨胀系数约为3-6ppm/℃。它们通常固定于载体、印刷电路板和用玻璃填充的环氧树脂、聚酰亚胺、液晶聚合物、填充PTFE之类的有机介电质制造的其他复合衬底。由这些有机介电质制成的电路化载体、印刷电路板和其他衬底，其CTE一般约为12-20ppm/℃。由于电路化有机介电质的CTE更接近芯片的其它材料(例如陶瓷)具有许多优点(包括成本、BGA寿命和介电常数)，故有机介电质尽管有这一CTE失配，仍然被使用于许多应用中。但使用这种CTE失配的材料并不出现问题。当封装件10被加热或冷却时，载体22的横向膨胀或收缩明显大于芯片12的横向膨胀或收缩。这在C4焊料球16上产生切应变。许多电子元件在其一般操作中例行经受热循环，且这些热循环有时由于环境条件而恶化。100℃以上的热循环是相当普遍的。在极端操作或环境条件下可以超过125℃。这些循环加于C4连接上的应力/应变是这些连接早期失效的一个主要原因。
图2示出了引入了解决CTE失配问题的常规方法的另一封装件40。除了封装件40在芯片12和载体22之间具有环绕C4焊料球的底部填充物48之外，封装件40的各个部分基本上与封装件10的相同。可以由为此而设计的许多市售材料中任何一种制成的底部填充物48，在固定于衬底之后，通常分散在芯片边沿周围，由于毛细作用而进入C4连接之间的空间并固化。底部填充物也可以加于芯片或载体，并随C4回流同时固化。凝固的底部填充物承受芯片12与载体22膨胀和收缩差异所产生的大部分负荷，这显著地降低了C4连接16上的应变。
如上所述，底部填充材料一般含有显著数量的二氧化硅之类的材料的极细小的颗粒。此颗粒被加于材料中，使底部填充物48的CTE基本上等于焊料球16的CTE(一般约为22ppm/℃)。这些热膨胀系数必须匹配以便防止底部填充物交替伸缩并沿垂直于芯片表面方向压缩C4焊料球(这也会产生早期失效)。但此颗粒添加物使底部填充材料的模数高，通常大于2Gpa即300ksi。当图2所示类型的封装件在底部填充物固化后被冷却时，芯片14和载体22之间的CTE差异和强耦合倾向于使芯片和载体都弯曲。这可能使硅芯片破裂。在完成载体22和衬底22之间的BGA连接28之后冷却时，芯片和载体的弯曲在载体和衬底之间的球栅阵列中央焊料球28上施加张力。随后的热循环使这些焊料球受压，并能引起早期失效。这样，底部填充层本身也不是完全满意的解决办法。
图3示出了体现本发明的电子封装件60，它明显地降低了CTE差异引起的弯曲或翘曲以及早期芯片破裂或BGA芯片破碎的伴生危险。封装件60包括底部填充物48和载体22之间的柔顺层68，它在一侧与底部填充物48的运动一致，而在另一侧与载体22的运动一致。在图3所示的底部填充的封装件中，柔顺层68的模数应该小于填充物48的模数的大约一半。通常，模数小于大约100000psi的材料是合适的，而模数大约为50000-20000psi的材料更好。合适的材料包括光成像互穿聚合物网络、硅酮之类的橡胶材料和聚四氟乙烯之类的粘塑性材料。诸如此处列为参考的Day等人的美国专利5439779所公开的阳离子聚合环氧树脂基树脂系统的光成像互穿聚合物网络(IPN)特别好。这些IPN可用来制作焊料掩模，使芯片和载体之间的C4连接容易实现。它们的物理性质也使其非常可取。
最佳柔顺材料被用于固化和处理过的载体22的表面，以便提供对应于芯片12上C4焊料球和载体22上接触24的窗口66图形。然后将具有预制焊料球16的芯片置于柔顺层上，并加热封装件以软化焊料球，使焊料流过柔顺层中的窗口66，并完成与载体上的接触24的连接，通常在芯片固定于载体之后，使柔顺层与芯片之间的空间充满常规底部填充材料。
柔顺层68较低的模数使此层的顶部与底部填充物48的运动一致，而此层的底部与载体22的运动一致。这使芯片膨胀与载体膨胀显著地去耦，降低了应力转移和封装件60的弯曲，降低了BGA连接上的应力并提高了其可靠性。芯片与衬底之间降低了的耦合增大了C4连接16的切形变，但BGA连接28的增大了的可靠性(通常比C4更不可靠得多)比C4连接预期寿命的任何降低都变化得更大。借助于适当选择材料、尺寸和其它参量，本发明的封装件可以设计成使C4连接的预期寿命与BGA连接的预期寿命大致相同，总体可靠性大为提高。
有限元分析和试验数据表明，柔顺层的最佳厚度范围为芯片与载体之间空间的四分之一到二分之一。对于降低弯曲来说，更薄的层不如最佳范围内的层那样有效，而更厚的层使得难以用底部填充物来填充留下的空间。
从图4可以看到由于使用这些材料而对弯曲的改进，此图示出了常规芯片载体(曲线A)和具有本发明柔顺层的载体(曲线B)的试验弯曲数据(用莫尔干涉法得到的)。用同一个总共具有700个焊料球的阵列的硅芯片掩模模型制作了二个封装件。芯片被固定在CTE约为18ppm/℃而模数约为18GPa的玻璃填充的环氧树脂叠层(由相同的材料制成)。厚度约为2密耳的由200℃时模数约为0.3GPa的多元醇树脂和溴化环氧树脂制成的光成像互穿聚合物网络制成的柔顺层，被加于第二载体的表面并被处理，以便形成对应于芯片上阵列中的焊料球和载体表面上的接触的窗口。焊料球通过柔顺层中的窗口被连接到载体上的接触，在芯片和柔顺层之间留下大约4密耳的空间。在不具有柔顺层的第一载体中，芯片和载体之间的空间约为6密耳。各个封装件中C4连接周围的开放空间在室温下用模数约为11GPa的市售底部填充材料Dexter Hysol 4511填充。
图4示出，正比于封装件中的弯曲应力的弯曲曲率是温度的线性函数。弯曲曲率越低，弯曲应力就越小。封装件变平(弯曲曲率为零)时的温度，由于低于此温度时芯片将开始被锁定或耦合于叠层芯片载体，故定义为“无应力温度”或“芯片锁定温度”或“芯片耦合温度”。高于此温度时，芯片将与叠层芯片载体去耦，亦即，芯片几乎保持平坦，而弯曲曲率基本上保持为零。
如从图可见，第二封装件中的去耦层有效地降低了“芯片耦合温度”、零弯曲曲率点或曲线与温度轴的交点。此时，“芯片耦合温度”从标准封装件的140℃降低到具有去耦层的封装件的大约110℃。由于弯曲曲率与温度之间的线性关系，具有去耦层的封装件的整个弯曲曲线向下偏移。于是，在具有去耦层的封装件中，在低于“芯片耦合温度”点的整个温度范围内，得到了较低的弯曲曲率因而也是较低的弯曲应力。
如上所述，各种其它的柔顺材料都能够用作柔顺层68。诸如在Tg非常低的材料上的丝网印刷之类的其它制备焊料掩模的方法，也可以用于不能光成像的材料。正如本技术领域熟练人员从上述描述中可理解的那样，本发明提供了一种在倒装芯片于电路化有机介电质衬底的封装件中降低弯曲的有效、实用而成本合算的方法。获得了这些改进而没有产生别的困扰现有技术方法的问题。当然，本技术领域熟练人员还能理解，在本发明的范围内，对上述由下列权利要求所定义的材料、结构和方法可以做出许多修正。

Claims (14)

1.一种半导体封装件，它包含：
集成电路芯片；
热膨胀系数明显高于所述芯片热膨胀系数的电路化有机衬底；
在所述芯片和所述衬底之间的焊料连接；
环绕所述焊料连接的底部填充层；以及
在所述包封剂和所述电路化有机载体之间的柔顺介电质材料层，所述介电质材料的模数小于底部填充层模数的大约一半，并被用来与一侧上的底部填充层一致地运动和与另一侧上的所述有机衬底一致地运动。
2.根据权利要求1的封装件，其中的柔顺介电质材料包含模数小于大约100000psi的聚合物材料。
3.根据权利要求2的封装件，其中所述聚合物材料的模数为大约50000psi-20000psi。
4.根据权利要求3的封装件，其中所述聚合物材料包含互穿聚合物网络、橡胶材料或粘塑性聚合物。
5.根据权利要求1的封装件，其中的柔顺介电质材料包含互穿聚合物网络。
6.根据权利要求5的封装件，其中所述网络中至少一种聚合物是可光成像的。
7.根据权利要求1的封装件，其中的柔顺层包含焊料掩模。
8.根据权利要求7的封装件，其中的焊料掩模包含可光成像的互穿聚合物网络。
9.根据权利要求8的封装件，其中所述可光成像的互穿聚合物网络包含含有多元醇树脂和溴化环氧树脂的环氧基树脂系统。
10.根据权利要求9的封装件，其中所述聚合物网络在大约95-105℃的温度下开始转变到橡胶态。
11.根据权利要求1的封装件，其中柔顺材料的柔顺层的厚度约为芯片和载体之间距离的四分之一到二分之一。
12.一种电子设备，它包含：
集成电路芯片；
在第一表面上具有第一组接触并在正对着所述第一表面的第二表面上具有第二组接触，所述第二组中的接触电连接于所述第一组中的接触的电路化有机介电质芯片载体；
在所述芯片和载体之间的焊料连接；
环绕所述焊料连接的底部填充层；
在所述底部填充层和所述芯片载体之间的由互穿聚合物网络制成的柔顺层；
至少在一个表面上具有接触的电路化有机衬底；以及
在所述衬底上的接触与所述载体上的所述第二组接触之间的焊料连接阵列。
13.一种用来将集成电路芯片连接到至少一个表面上具有接触阵列的有机介电质芯片载体的方法，其特征是包含下列步骤：
提供一个从所述芯片有源表面突出的焊料元件阵列；
将互穿聚合物网络组成的柔顺层涂于所述衬底的所述表面，将所述表面上的接触覆盖；
在所述柔顺层中制作窗口以便能够接近所述衬底上的接触；
将所述集成电路芯片置于所述柔顺层上，使所述突出的焊料元件与所述窗口对准；并对焊料元件进行加热，使焊料流过所述窗口，从而完成所述芯片与所述接触之间的电连接；以及
制作环绕柔顺层与芯片之间的所述焊料连接的底部填充材料层。
14.一种装配电子元件的方法，它包含：
提供一个具有从所述芯片有源表面突出的焊料元件阵列的集成电路芯片；
提供一个在第一表面上具有第一组接触并在正对着所述第一表面的第二表面上具有第二组接触，所述第二组中的接触电连接于所述第一组中的接触的电路化有机介电质芯片载体；
在所述载体与所述芯片之间制作环绕所述突出焊料元件的底部填充层；
将所述集成电路芯片置于所述柔顺层上，使所述突出的焊料元件与所述窗口对准；并对焊料元件进行加热，使焊料流过所述窗口，从而完成所述芯片与所述接触之间的电连接；
在所述芯片载体的所述第一表面上，制作具有对应于所述突出焊料元件和所述载体上的所述接触，且模数为100000psi或更小的柔顺层；
将第二级焊料元件阵列键合到所述载体的第二表面上的接触；
提供至少在一个表面上具有接触的电路化有机印刷电路板或卡或其它衬底；
将具有所述第二级焊料元件的所述载体与所述衬底上的接触相接触；以及
使所述第二级焊料元件回流，从而完成从所述集成电路芯片通过所述一级焊料元件和所述二级焊料元件到所述衬底的电连接。
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