SG92634A1 - Compliant surface layer for flip-chip electronic packages and method for forming same - Google Patents
Compliant surface layer for flip-chip electronic packages and method for forming sameInfo
- Publication number
- SG92634A1 SG92634A1 SG9901579A SG1999001579A SG92634A1 SG 92634 A1 SG92634 A1 SG 92634A1 SG 9901579 A SG9901579 A SG 9901579A SG 1999001579 A SG1999001579 A SG 1999001579A SG 92634 A1 SG92634 A1 SG 92634A1
- Authority
- SG
- Singapore
- Prior art keywords
- flip
- surface layer
- substrate
- electronic packages
- chip electronic
- Prior art date
Links
- 239000002344 surface layer Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 3
- 239000010410 layer Substances 0.000 abstract 2
- 229920000642 polymer Polymers 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 1
- 239000004033 plastic Substances 0.000 abstract 1
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- -1 polytetrafluoroethylene Polymers 0.000 abstract 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 abstract 1
- 239000004810 polytetrafluoroethylene Substances 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/067,708 US6191952B1 (en) | 1998-04-28 | 1998-04-28 | Compliant surface layer for flip-chip electronic packages and method for forming same |
Publications (1)
Publication Number | Publication Date |
---|---|
SG92634A1 true SG92634A1 (en) | 2002-11-19 |
Family
ID=22077843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG9901579A SG92634A1 (en) | 1998-04-28 | 1999-03-31 | Compliant surface layer for flip-chip electronic packages and method for forming same |
Country Status (4)
Country | Link |
---|---|
US (1) | US6191952B1 (zh) |
CN (1) | CN1168138C (zh) |
MY (1) | MY138376A (zh) |
SG (1) | SG92634A1 (zh) |
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US6303408B1 (en) * | 1998-02-03 | 2001-10-16 | Tessera, Inc. | Microelectronic assemblies with composite conductive elements |
JP2001007473A (ja) * | 1999-06-17 | 2001-01-12 | Nec Corp | 集積回路素子の実装構造および方法 |
US6309908B1 (en) * | 1999-12-21 | 2001-10-30 | Motorola, Inc. | Package for an electronic component and a method of making it |
US6444921B1 (en) * | 2000-02-03 | 2002-09-03 | Fujitsu Limited | Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like |
US6373125B1 (en) * | 2000-02-23 | 2002-04-16 | International Business Machines Corporation | Chip scale package with direct attachment of chip to lead frame |
US6399896B1 (en) * | 2000-03-15 | 2002-06-04 | International Business Machines Corporation | Circuit package having low modulus, conformal mounting pads |
SG97872A1 (en) * | 2000-03-23 | 2003-08-20 | Advanpack Solutions Pte Ltd | Method of packaging an integrated circuit device |
US6774315B1 (en) * | 2000-05-24 | 2004-08-10 | International Business Machines Corporation | Floating interposer |
US6816385B1 (en) * | 2000-11-16 | 2004-11-09 | International Business Machines Corporation | Compliant laminate connector |
US6737295B2 (en) * | 2001-02-27 | 2004-05-18 | Chippac, Inc. | Chip scale package with flip chip interconnect |
US20020173077A1 (en) * | 2001-05-03 | 2002-11-21 | Ho Tzong Da | Thermally enhanced wafer-level chip scale package and method of fabricating the same |
US6603916B1 (en) | 2001-07-26 | 2003-08-05 | Lightwave Microsystems Corporation | Lightwave circuit assembly having low deformation balanced sandwich substrate |
US7015066B2 (en) * | 2001-09-05 | 2006-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly |
JP3566680B2 (ja) * | 2001-09-11 | 2004-09-15 | 富士通株式会社 | 半導体装置の製造方法 |
US6869831B2 (en) * | 2001-09-14 | 2005-03-22 | Texas Instruments Incorporated | Adhesion by plasma conditioning of semiconductor chip surfaces |
US7235886B1 (en) * | 2001-12-21 | 2007-06-26 | Intel Corporation | Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby |
US20030116860A1 (en) * | 2001-12-21 | 2003-06-26 | Biju Chandran | Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses |
JP2003298196A (ja) * | 2002-04-03 | 2003-10-17 | Japan Gore Tex Inc | プリント配線板用誘電体フィルム、多層プリント基板および半導体装置 |
DE502004010904D1 (de) * | 2004-01-27 | 2010-04-29 | Mettler Toledo Ag | Dehnmessstreifen mit Feuchtigkeitsschutz durch inhomogene anorganische Schicht auf glättender Polymerschicht (ORMOCER) und Schlitzanordnung |
CN100356534C (zh) * | 2004-06-15 | 2007-12-19 | 日月光半导体制造股份有限公司 | 半导体封装构造及其制造方法 |
DE102004037610B3 (de) * | 2004-08-03 | 2006-03-16 | Infineon Technologies Ag | Verfahren zur Verbindung einer integrierten Schaltung mit einem Substrat und entsprechende Schaltungsanordnung |
US7851916B2 (en) * | 2005-03-17 | 2010-12-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strain silicon wafer with a crystal orientation (100) in flip chip BGA package |
US7170159B1 (en) * | 2005-07-07 | 2007-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low CTE substrates for use with low-k flip-chip package devices |
US7633157B2 (en) * | 2005-12-13 | 2009-12-15 | Micron Technology, Inc. | Microelectronic devices having a curved surface and methods for manufacturing the same |
US7573138B2 (en) * | 2006-11-30 | 2009-08-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stress decoupling structures for flip-chip assembly |
US20080142996A1 (en) * | 2006-12-19 | 2008-06-19 | Gopalakrishnan Subramanian | Controlling flow of underfill using polymer coating and resulting devices |
US7875503B2 (en) * | 2006-12-28 | 2011-01-25 | Intel Corporation | Reducing underfill keep out zone on substrate used in electronic device processing |
US7745321B2 (en) * | 2008-01-11 | 2010-06-29 | Qimonda Ag | Solder contacts and methods of forming same |
US7973417B2 (en) * | 2008-04-18 | 2011-07-05 | Qimonda Ag | Integrated circuit and method of fabricating the same |
CN101814444B (zh) * | 2009-04-30 | 2012-01-25 | 中国空空导弹研究院 | 叠层器件的低应力底部填充方法 |
US8432034B2 (en) * | 2011-05-25 | 2013-04-30 | International Business Machines Corporation | Use of a local constraint to enhance attachment of an IC device to a mounting platform |
US8546900B2 (en) * | 2011-06-09 | 2013-10-01 | Optiz, Inc. | 3D integration microelectronic assembly for integrated circuit devices |
CN102279942A (zh) * | 2011-07-25 | 2011-12-14 | 上海祯显电子科技有限公司 | 一种新型智能卡 |
CN103946873A (zh) * | 2011-08-26 | 2014-07-23 | 艾迪田集团股份有限公司 | 卡层压 |
US20150064851A1 (en) * | 2013-09-03 | 2015-03-05 | Rohm And Haas Electronic Materials Llc | Pre-applied underfill |
US9281238B2 (en) * | 2014-07-11 | 2016-03-08 | United Microelectronics Corp. | Method for fabricating interlayer dielectric layer |
DE112014006844T5 (de) * | 2014-07-28 | 2017-04-13 | GM Global Technology Operations LLC | Systeme und Verfahren zum verstärkten Kleben |
EP3984059A4 (en) * | 2019-06-11 | 2022-07-20 | Kulicke & Soffa Netherlands B.V. | MATERIAL FOR POSITION ERROR COMPENSATION IN THE ASSEMBLY OF DISCREET COMPONENTS |
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US4658332A (en) | 1983-04-04 | 1987-04-14 | Raytheon Company | Compliant layer printed circuit board |
US4873615A (en) | 1986-10-09 | 1989-10-10 | Amp Incorporated | Semiconductor chip carrier system |
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US4847146A (en) * | 1988-03-21 | 1989-07-11 | Hughes Aircraft Company | Process for fabricating compliant layer board with selectively isolated solder pads |
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US5210157A (en) * | 1989-08-15 | 1993-05-11 | Akzo N.V. | Interpenetrating network of ring-containing allyl polymers and epoxy resin, and a laminate prepared therefrom |
ES2047244T3 (es) * | 1989-09-15 | 1994-02-16 | Akzo Nv | Reticulo interpenetrante quimicamente enlazado. |
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US5262280A (en) | 1992-04-02 | 1993-11-16 | Shipley Company Inc. | Radiation sensitive compositions |
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WO1994018701A1 (en) | 1993-02-05 | 1994-08-18 | W.L. Gore & Associates, Inc. | Stress-resistant semiconductor chip-circuit board interconnect |
US5439779A (en) | 1993-02-22 | 1995-08-08 | International Business Machines Corporation | Aqueous soldermask |
US5329423A (en) * | 1993-04-13 | 1994-07-12 | Scholz Kenneth D | Compressive bump-and-socket interconnection scheme for integrated circuits |
FR2704691B1 (fr) | 1993-04-30 | 1995-06-02 | Commissariat Energie Atomique | Procédé d'enrobage de composants électroniques hybrides par billes sur un substrat. |
US5511306A (en) | 1994-04-05 | 1996-04-30 | Compaq Computer Corporation | Masking of circuit board vias to reduce heat-induced board and chip carrier package warp during wavesolder process |
JPH10505376A (ja) * | 1994-09-08 | 1998-05-26 | アクゾ ノーベル ナムローゼ フェンノートシャップ | エチレン性不飽和無水物とビニル化合物との共重合体を含む、アリルを含むエポキシ樹脂組成物 |
US5493075A (en) | 1994-09-30 | 1996-02-20 | International Business Machines Corporation | Fine pitch solder formation on printed circuit board process and product |
US5579573A (en) | 1994-10-11 | 1996-12-03 | Ford Motor Company | Method for fabricating an undercoated chip electrically interconnected to a substrate |
US5633535A (en) | 1995-01-27 | 1997-05-27 | Chao; Clinton C. | Spacing control in electronic device assemblies |
US5801446A (en) * | 1995-03-28 | 1998-09-01 | Tessera, Inc. | Microelectronic connections with solid core joining units |
US5866952A (en) * | 1995-11-30 | 1999-02-02 | Lockheed Martin Corporation | High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate |
US5808874A (en) * | 1996-05-02 | 1998-09-15 | Tessera, Inc. | Microelectronic connections with liquid conductive elements |
US6054250A (en) * | 1997-02-18 | 2000-04-25 | Alliedsignal Inc. | High temperature performance polymers for stereolithography |
US6002590A (en) * | 1998-03-24 | 1999-12-14 | Micron Technology, Inc. | Flexible trace surface circuit board and method for making flexible trace surface circuit board |
-
1998
- 1998-04-28 US US09/067,708 patent/US6191952B1/en not_active Expired - Lifetime
-
1999
- 1999-03-25 MY MYPI99001137A patent/MY138376A/en unknown
- 1999-03-26 CN CNB991043901A patent/CN1168138C/zh not_active Expired - Lifetime
- 1999-03-31 SG SG9901579A patent/SG92634A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
CN1244728A (zh) | 2000-02-16 |
MY138376A (en) | 2009-05-29 |
US6191952B1 (en) | 2001-02-20 |
CN1168138C (zh) | 2004-09-22 |
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