TWI475649B - 用於積體電路裝置之３ｄ積體微電子總成及其製造方法（一） - Google Patents

用於積體電路裝置之３ｄ積體微電子總成及其製造方法（一） Download PDF

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TWI475649B
TWI475649B TW101118951A TW101118951A TWI475649B TW I475649 B TWI475649 B TW I475649B TW 101118951 A TW101118951 A TW 101118951A TW 101118951 A TW101118951 A TW 101118951A TW I475649 B TWI475649 B TW I475649B
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interconnects
microelectronic assembly
cavity
conductive material
forming
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TW101118951A
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TW201304079A (zh
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Vage Oganesian
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Optiz Inc
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Description

用於積體電路裝置之3D積體微電子總成及其製造方法(一) 發明領域
本發明係有關半導體封裝，且更特別有關一其中將一半導體裝置安裝在一含有另一半導體裝置的封裝體結構上之3D積體封裝體。
 發明背景
半導體裝置趨勢係在於被封裝在更小封裝體(其保護晶片同時提供晶片外信號連接性)中之更小的積體電路(IC)裝置(亦稱為晶片)。對於相關的晶片裝置(譬如一影像感測器及其處理器)而言，一種達成尺寸減小的方式係將兩裝置形成為相同IC晶片的部份(亦即將其積造在單一積體電路裝置內)。然而，如此將造成眾多複雜的製造議題，這會不利地影響操作、成本及良率。另一種用以組合相關晶片裝置之技術係為3D IC封裝，其藉由將分離的晶片堆積在單一封裝體內來節省空間。
3D封裝可導致增高的密度及較小的形狀因數(form factor)、較好的電性效能(因為較短的互連體長度容許具有增高的裝置速度及較低的功率消耗)、較好的異質積造(亦即積造諸如一影像感測器及其處理器等不同的功能層)、及較低的成本。
然而，用於微電子封裝之3D積造亦面臨到挑戰，諸如3D處理基礎建設及可存續供應鏈的高成本。包括先鑽孔 (Via-First)、後鑽孔(Via-Last)及中鑽孔(Via-middle)製程等用以形成貫通矽導孔(TSV)之既有3D IC封裝技術係利用先天即複雜且昂貴的半導體微影製程。結果，世上少有公司能負擔每年數十億美元計的CMOS研發費用以求跟上腳步。並且，IC封裝體之間的互連體會由於製造及安裝期間所受的應力、暨操作期間所受的熱或振動應力而失效。需要一種具互補性、合乎成本效益的TSV解決方案以能夠使用一能令影像感測器上的像素陣列區域達到最大化之分離但密切耦合的影像處理器，且能夠藉由將多重的晶片堆積及垂直互連而具有直接記憶體存取。
 發明概要
本發明係為一微電子總成，其提供一用於封裝/包封IC裝置之新穎晶圓層級3D積體封裝體，並能夠3D積造諸如一影像感測器與其處理器等多重相關但不同的IC裝置。該微電子總成係包括一晶系基材處置器，該晶系基材處置器係具有相對的第一及第二表面，其中一腔穴形成於第一表面內，一配置於腔穴中之第一IC裝置，一安裝至第二表面之第二IC裝置，及形成經過晶系基材處置器之複數個互連體。各互連體係包括一孔，該孔形成經過晶系基材處置器，其中一側壁延伸於第一及第二表面之間，一順應性介電材料，其沿著側壁配置，及一傳導材料，其沿著順應性介電材料配置且延伸於第一及第二表面之間，其中順應性介電材料係絕緣傳導材料與側壁。第二IC裝置係電性耦合至複 數個互連體的傳導材料。
一形成一微電子總成之方法係包括形成一腔穴於一具有相對的第一及第二表面之晶系基材處置器中，其中腔穴形成至第一表面內，將一第一IC裝置放置在腔穴中，將一第二IC裝置安裝至第二表面，且經過晶系基材處置器形成複數個互連體。複數個互連體的各者藉由經過晶系基材處置器形成一孔而被形成，其中一側壁延伸於第一及第二表面之間，沿著側壁形成一順應性介電材料，及使一傳導材料沿著順應性介電材料形成且延伸於第一及第二表面之間，其中順應性介電材料係絕緣傳導材料與側壁。該方法進一步包括將第二IC裝置電子性耦合至複數個互連體的傳導材料。
將經由檢閱說明書、申請專利範圍及附圖得知本發明的其他目的及特徵構造。
圖式簡單說明
第1至10圖是一半導體封裝結構之橫剖側視圖，其依順序顯示將一IC裝置安裝在一容置有另一IC裝置的半導體封裝結構上之封裝結構的處理中之步驟。
 較佳實施例之詳細說明
本發明係為可理想用於封裝/包封IC裝置、並能夠3D積造諸如影像感測器及其處理器等多重相關的IC裝置之晶圓層級3D IC積體封裝體解決方案。3D積體封裝體的形成係描述於下文。
該形成製程開始係為如第1圖所示的一晶系基材處置器10。一非限制性範例可包括具有約600μm厚度之晶系基材的一處置器。一腔穴12形成於處置器中，如第2圖所示。腔穴12可利用一雷射、一電漿蝕刻製程、一噴砂製程、一機械銑製製程、或任何其他類似方法形成。較佳地，腔穴12藉由光微影術電漿蝕刻形成，其包括形成一層光阻於處置器10上，將光阻層圖案化以曝露處置器10的一選擇部分，且然後進行一電漿蝕刻製程(譬如使用一SF6電漿)以移除處置器10的經曝露部分以形成腔穴12。較佳地，腔穴延伸不超過晶系基材厚度的3/4，或至少在腔穴底部留下約50μm的最小厚度。電漿蝕刻可為異向性、推拔狀、等向性、或其組合。
通孔(導孔)14隨後與腔穴12相鄰但連接地形成經過處置器10的厚度，如第3圖所示。孔14可利用一雷射、一電漿蝕刻製程、一噴砂製程、一機械銑製製程、或任何類似方法形成。較佳地，通孔14利用與形成腔穴12類似的方式藉由電漿蝕刻形成(差異在於孔14一路延伸經過晶系基材處置器10的厚度)。電漿矽蝕刻(譬如異向性、推拔狀、等向性、或其組合)係容許具有不同形狀的導孔輪廓。較佳地，孔14的輪廓為推拔狀，其中一較大維度係位於可供經過其形成腔穴12之表面上。較佳地，最小孔直徑為約25μm，且壁的角度相對於與可供經過其形成孔14之晶系基材表面呈正交的方向位於5°至35°之間，俾使孔在晶系基材10的一表面上具有比另一表面更小的橫剖面尺寸。
通孔14隨後利用一旋塗製程、一噴灑製程、一配送製程、一電化沉積製程、一層疊製程、或任何其他的類似方法充填一順應性介電材料16，如第4圖所示。一順應性介電質係為在三正交方向皆展現順應性且可容納晶系基材(~2.6ppm/℃)與Cu(~17ppm/℃)互連體之間的熱膨脹係數(CTE)不匹配之一種相對軟材料(譬如銲罩)。順應性介電材料16較佳係為一聚合物，諸如BCB(苯環丁烯)、銲罩、銲阻、或BT環氧樹脂。
通孔18隨後形成經過介電材料16。可利用對於較大尺寸孔18的一CO2 雷射(譬如約70μm的斑點尺寸)、或對於較小尺寸孔18(譬如小於50μm直徑)的一UV雷射(譬如在355nm波長之約20μm的斑點尺寸)來形成孔18。可使用小於140ns脈衝長度位於10及50kHz之間的雷射脈衝頻率。通孔18的側壁可隨後被金屬化(亦即塗覆有一金屬化層20)。金屬化製程較佳開始係為用於移除通孔18內部壁上髒污(由鑽過諸如環氧樹脂、聚醯亞胺、氰酸鹽酯樹脂等介電材料所造成)的任何樹脂之去污製程。該製程係涉及使樹脂髒污與γ丁內酯與水的一混合物作接觸以軟化樹脂髒污，接著以一鹼性過錳酸鹽溶液作處理以移除軟化的樹脂，並以一水性酸性中和劑作處理以中和並移除過錳酸鹽殘留物。在去污處理之後，初始傳導金屬化層20係由無電極銅鍍覆形成，接著係為一光微影術回蝕使得金屬化層在孔18的兩端以一段短距離(譬如25μm或以上)沿著介電質16延伸遠離孔18(但未遠到與晶系基材10產生電性接觸)。藉由來自表面粗度的一錨固 效應在經鍍覆介面獲得黏著。所產生的結構顯示於第5圖。
一介電層22隨後形成於不含通往腔穴12的開口之處置器的表面上。較佳地，利用一旋塗製程或一噴灑製程將一可光成像性介電質施加於處置器表面上來達成此作用。然後使用一光微影性製程(亦即UV曝光、選擇性材料移除)來選擇性移除通孔18上方(且因此使其曝露)之介電層22的部分及金屬化層20的水平部分。一金屬層隨後被濺鍍於介電層22上方。使用一光微影性製程(亦即阻劑層沉積、經過一罩幕的UV曝光、阻劑的選定部分之移除以曝露金屬層的選定部分、金屬蝕刻、及光阻移除)來選擇性移除金屬層的部分，而留下配置於通孔18上方且與金屬化層20電性接觸之金屬墊24。所產生的結構顯示於第6圖。雖然未圖示，金屬墊24的中心可穿設有一與通孔18對準之小孔。
一IC晶片26被插入腔穴12內，如第7圖所示。IC晶片26係包括一積體電路(亦即半導體裝置)。IC晶片26藉由一介電絕緣層28而與處置器10絕緣。IC晶片26的插入及絕緣層28的形成可以數種方式進行。一種方式係在裸IC晶片26插入之前(譬如藉由噴塗環氧樹脂、藉由電化沉積等)將絕緣層28形成於腔穴12的壁上。第二種方式係在被插入腔穴12內之前將絕緣層28形成於IC晶片26的背表面上。第三種方式係在晶片插入之前將絕緣層形成於腔穴壁上及IC晶片背表面上，其中兩絕緣層在晶片插入時被結合在一起，以形成絕緣層28。IC晶片26包括在其底表面上曝露之結合墊30。
一包封絕緣層32隨後形成於結構上，其將IC晶片26包 封在腔穴12內。較佳地，利用一可光成像性介電質(譬如一銲罩)形成層32。該層被預固化以部份地移除溶劑使得表面不黏。然後進行一光微影術步驟(亦即經過罩幕的UV曝光)，其後移除絕緣層32的選擇部分以曝露IC晶片結合墊30及延伸出通孔18外的金屬化層20。然後可進行後固化以增大層32的表面硬度。一金屬層隨後沉積在絕緣層32上方(譬如藉由金屬濺鍍，接著是一可光成像性阻劑層之沉積)。然後進行一光微影術步驟(亦即，經過罩幕的UV曝光以及選擇性阻劑層移除)，接著是藉由光阻移除所曝露的部分之選擇性金屬蝕刻，而留下與IC晶片結合墊30電性接觸之金屬扇出及扇入結合墊34，且留下與延伸出通孔18外的金屬化層20電性接觸之互連體結合墊36。此處亦可發生結合墊34/36的金屬鍍覆。所產生的結構顯示於第8圖(在光阻移除之後)。
一包封絕緣層38隨後形成於絕緣層32及結合墊34/36上方，接著是一選擇性回蝕以曝露結合墊34/36。選擇性回蝕可藉由一光微影製程進行以選擇性移除結合墊34/36上方之層38的部分。BGA互連體40隨後利用一銲料合金的一絲網印刷製程、或藉由一球置放製程、或藉由一鍍覆製程而形成於結合墊34/36上方。BGA(球柵陣列)互連體係為用於與對偶導體產生物理及電性接觸之圓弧形導體，通常藉由將金屬球銲接或部份地融化在結合墊上所形成。所產生的結構顯示於第9圖。
一IC晶片總成42隨後附接至絕緣層22，如第10圖所示。可利用習見的揀放晶粒附接設備進行附接。可使用黏 劑卷帶或可列印/可配送環氧樹脂材料作為黏劑。IC晶片總成42係包括一第二IC晶片44，以及用於信號連接至IC晶片44之CIS結合墊46。在第10圖的示範性實施例中，IC晶片44係為一影像感測器，其包括一基材45、一陣列的像素感測器47及一色濾器及微透鏡陣列48。理想上，IC晶片26係為一用於影像感測器之處理器。隨後係附接Au或Cu導線結合件50以將CIS結合墊的各者電性連接至互連金屬墊24的一者。
上述及圖示的IC封裝技術及其製造方法具有數項優點。第一，以矽為基礎的IC晶片26被容置在晶系基材10內，其提供IC晶片26的機械性及環境性保護。第二，利用一用於將IC晶片26固接在晶系基材10內的順應性介電材料28係降低了會負面影響兩者之熱及機械應力。第三，利用一具有用於封裝IC晶片26的扇出及扇入墊(其可在插入封裝件10前被分離地測試及驗證)之晶系基材封裝體結構係增強了可靠度與良率。第四，在一二晶片組合中，將晶片的一者容置於一其上安裝有另一晶片之晶系基材封裝體結構10內係增強了可靠度並提供一更快速且更可靠的信號互連方案。第五，用於兩晶片之電性連接係設置於處置器10的一共同表面上，以供有效率的信號耦合及連接。第六，利用用於層32的一晶圓層級介電疊層係提供橫越一很寬頻率範圍的很低阻抗。此阻抗可比既有的噴灑及旋塗介電質更低達到一個數量級或以上。這些超薄介電疊層亦提供將功率及接地平面上的雜訊予以減振之優點，並對於達成未來高速數位設計中的可接受電性效能而言很重要。
經過孔18形成之貫通聚合物互連體亦具有數項優點。第一，這些互連體係為傳導元件，其從晶片44可靠地重新繞佈電信號、經過處置器10、來到含有用於IC晶片26的電接觸部之處置器10的同側。第二，藉由將通孔14的壁形成有一傾斜，其降低了可由於90度角所導致之晶系基材上潛在具損害性的誘發應力。第三，孔14的傾斜狀側壁亦代表不具有會導致介電材料16形成間隙之負角區域。第四，藉由先形成絕緣材料16、然後在其上形成金屬化層20，可避免金屬擴散至處置器10的晶系基材結構內。第五，利用一鍍覆製程形成金屬層20係優於諸如濺鍍沉積等其他金屬化技術，原因在於鍍覆製程較不易損害絕緣材料16。第六，利用一順應性絕緣材料16來形成孔18的側壁係較為可靠。第七，利用雷射鑽製經過聚合物、去污、及金屬鍍覆來生成貫通聚合物互連體係比利用半導體濺鍍及金屬沉積工具更為便宜。最後，比起用於第一IC晶片26的結合墊而言，用於第二IC晶片44之導線結合係配置於封裝體結構10的相反側上，其能夠使晶片之間具有最短的電性路徑並且不再需要一撓性及/或有機封裝體處置器以供影像感測器的總成所用。
上述封裝組態係可理想使用於並IC晶片44身為影像感測器且IC晶片26身為用於處理來自影像感測器的信號之處理器並就此脈絡作描述(但不在此限)。影像感測器是一互補性金屬氧化物半導體(CMOS)裝置，其包括一含有一陣列的像素感測器之積體電路，各像素含有一光偵測器且較佳含 有其自身的主動放大器。各像素感測器將光能轉換成一電壓信號。晶片上可包括有額外電路以將電壓轉換成數位資料。影像處理晶片係包含硬體處理器及軟體演算法的一組合。影像處理器從個別像素感測器收集亮度及色度資訊並利用其運算/內插對於各像素的正確色彩及明度值。影像處理器評估一給定像素的色彩及明度資料，將其與來自鄰近像素的資料作比較且然後利用一去馬賽克演算法從不完全的色彩樣本重新建構一全色彩影像，並產生對於該像素的一適當明度值。影像處理器亦存取整體圖像並矯正銳利度且降低影像的雜訊。
影像感測器的演進係導致影像感測器中益加更高的像素數，以及諸如自動聚焦、紅眼消除、臉部追蹤等額外的攝影機功能，其需要可以更高速運作之更強力的影像感測器處理器。攝影者不想在可繼續進行拍攝之前等待攝影機的影像處理器完成其工作-其甚至不想注意到攝影機內部正在進行一些處理。因此，影像感測器必須被最適化以在相同或甚至更短時間期間中應付更多的資料。
請瞭解本發明不限於上述及顯示的實施例，而是涵蓋落在申請專利範圍的範疇內之任一及全部變異。譬如，本文對於本發明的指涉並無意限制任一申請專利範圍或申請專利範圍條件的範疇，而是僅指涉可被申請專利範圍的一或多者所涵蓋的一或多個特徵構造。上述材料、製程及數值範例僅為範例，且不應視為限制申請專利範圍。並且，如同申請專利範圍及說明書所得知，不需以所顯示或主張 的確切次序進行全部的方法步驟，而是以可容許妥當形成本發明的IC封裝之任何次序分離地或同時地進行即可。單層的材料可形成為多層的如是或類似材料，且反之亦然。雖然就IC晶片26身為一影像感測器處理器且IC晶片44身為一影像感測器之脈絡來揭露創新的封裝組態，本發明不限於這些IC晶片。
應注意如本文的“上方”及“上”用語皆包含性包括“直接位於~上”(不具有配置其間之中間材料、元件或空間)以及“間接位於~上”(具有配置其間之中間材料、元件或空間)。同理，“相鄰”用語係包括“直接相鄰”(不具有配置其間之中間材料、元件或空間)以及“間接相鄰”(具有配置其間之中間材料、元件或空間)，“安裝至”係包括“直接安裝至”(不具有配置其間之中間材料、元件或空間)以及“間接安裝至”(具有配置其間之中間材料、元件或空間)，且“電性耦合”係包括“直接電性耦合至”(不具有用於將元件電性連接在一起之位於其間的中間材料或元件)以及“間接電性耦合至”(具有用於將元件電性連接在一起之位於其間的中間材料或元件)。譬如，形成一元件“於一基材上方”可包括直接形成該元件於基材上方而其間不具有中間材料/元件、以及間接形成該元件於基材上方而其間具有一或多個中間材料/元件。
10‧‧‧晶系基材處置器
12‧‧‧腔穴
14‧‧‧通孔(導孔)
16‧‧‧順應性介電材料
18‧‧‧較大尺寸孔
20‧‧‧金屬化層
22‧‧‧介電層
24‧‧‧金屬墊
26‧‧‧IC晶片
28‧‧‧介電絕緣層
30‧‧‧結合墊
32‧‧‧包封絕緣層
34‧‧‧金屬扇出及扇入結合墊
36‧‧‧互連體結合墊
38‧‧‧包封絕緣層
40‧‧‧BGA互連體
42‧‧‧IC晶片總成
44‧‧‧第二IC晶片
45‧‧‧基材
46‧‧‧CIS結合墊
47‧‧‧像素感測器
48‧‧‧色濾器及微透鏡陣列
50‧‧‧Au或Cu導線結合件
第1至10圖是一半導體封裝結構之橫剖側視圖，其依順序顯示將一IC裝置安裝在一容置有另一IC裝置的半導體封裝結構上之封裝結構的處理中之步驟。
10‧‧‧晶系基材處置器
16‧‧‧順應性介電材料
18‧‧‧較大尺寸孔
20‧‧‧金屬化層
22‧‧‧介電層
24‧‧‧金屬墊
26‧‧‧IC晶片
28‧‧‧介電絕緣層
30‧‧‧結合墊
32‧‧‧包封絕緣層
34‧‧‧金屬扇出及扇入結合墊
36‧‧‧互連體結合墊
38‧‧‧包封絕緣層
40‧‧‧BGA互連體
42‧‧‧IC晶片總成
44‧‧‧第二IC晶片
45‧‧‧基材
46‧‧‧CIS結合墊
47‧‧‧像素感測器
48‧‧‧色濾器及微透鏡陣列
50‧‧‧Au或Cu導線結合件

Claims (22)

  1. 一種微電子總成，包含：一晶系基材處置器，其具有相對的第一及第二表面，其中一腔穴形成進入該第一表面，朝向該第二表面延伸但沒有到達該第二表面；一第一IC裝置，其係配置於該腔穴中；一第二IC裝置，其係安裝至該第二表面；複數個互連體，其形成穿過該晶系基材處置器，其中各互連體包含：一孔，其形成穿過該晶系基材處置器，其具有延伸於該等第一及第二表面之間的一側壁，一順應性介電材料，其係沿著該側壁配置，及一傳導材料，其係沿著該順應性介電材料配置且延伸於該等第一及第二表面之間，其中該順應性介電材料使該傳導材料與該側壁絕緣；其中該第二IC裝置係電氣耦合至該等複數個互連體的傳導材料。
  2. 如申請專利範圍第1項之微電子總成，其中該順應性介電材料包括一聚合物。
  3. 如申請專利範圍第1項之微電子總成，其中對於該等複數個互連體中的每一者，該孔係為推拔狀使得該孔在該第二表面比起在該第一表面具有一更小的橫剖面維度。
  4. 如申請專利範圍第1項之微電子總成，其中對於該等複數個互連體中的每一者，該側壁係相對於與該等第一及 第二表面正交的一方向在呈5°至35°之間的一方向延伸。
  5. 如申請專利範圍第1項之微電子總成，其中該等複數個互連體中的每一者進一步包含：一第一結合墊，其在該第一表面配置於該孔上方且電氣耦合至該傳導材料；及一第二結合墊，其在該第二表面配置於該孔上方且電氣耦合至該傳導材料。
  6. 如申請專利範圍第5項之微電子總成，其中該第二IC裝置係藉由電氣耦合至該等第二結合墊之複數條導線而電氣耦合至該等複數個互連體的傳導材料。
  7. 如申請專利範圍第1項之微電子總成，進一步包含：一或多層的絕緣材料，其係配置於該第一表面上且延伸橫越該第一表面中之該腔穴的一開口，該一或多層的絕緣材料將該第一IC裝置包封在該腔穴中。
  8. 如申請專利範圍第7項之微電子總成，進一步包含：複數個結合墊，其係電氣耦合至該第一IC裝置且至少部份地延伸穿過該一或多層的絕緣材料。
  9. 如申請專利範圍第8項之微電子總成，進一步包含：複數個圓弧狀互連體，其各電氣連接至該等複數個結合墊中的一者。
  10. 如申請專利範圍第1項之微電子總成，其中該第二IC裝置係為一影像感測器且該第一IC裝置係為一用於處理來自該影像感測器的信號之處理器。
  11. 如申請專利範圍第10項之微電子總成，其中該影像感測器係包含一陣列的像素感測器，該陣列的像素感測器各包括一用於將光能轉換成一電壓信號之光偵測器，且其中該處理器係組配來接收該等電壓信號，並對於來自該等像素感測器之該等電壓信號中的每一者運算或內插色彩及明度值。
  12. 一種用於形成微電子總成之方法，包含下列步驟：在具有相對的第一及第二表面之一晶系基材處置器中形成一腔穴，其中該腔穴形成進入該第一表面，朝向該第二表面延伸但沒有到達該第二表面；將一第一IC裝置放置在該腔穴中；將一第二IC裝置安裝至該第二表面；形成穿過該晶系基材處置器之複數個互連體，其中該等複數個互連體中的每一者係藉由下列步驟而形成：形成穿過該晶系基材處置器之一孔，其具有延伸於該等第一及第二表面之間的一側壁，沿著該側壁形成一順應性介電材料，形成一傳導材料沿著該順應性介電材料且延伸於該等第一及第二表面之間，其中該順應性介電材料係使該傳導材料與該側壁絕緣；及將該第二IC裝置電氣耦合至該等複數個互連體的傳導材料。
  13. 如申請專利範圍第12項之方法，其中該順應性介電材料包括一聚合物。
  14. 如申請專利範圍第12項之方法，其中對於該等複數個互連體中的每一者，該孔係為推拔狀使得該孔在該第二表面比起在該第一表面具有一更小的橫剖面維度。
  15. 如申請專利範圍第12項之方法，其中對於該等複數個互連體中的每一者，該側壁係相對於與該等第一及第二表面正交的一方向在呈5°至35°之間的一方向延伸。
  16. 如申請專利範圍第12項之方法，其中該等複數個互連體中的每一者之形成步驟進一步包含：將一第一結合墊在該第一表面形成於該孔上方且電氣耦合至該傳導材料；及將一第二結合墊在該第二表面形成於該孔上方且電氣耦合至該傳導材料。
  17. 如申請專利範圍第16項之方法，其中將該第二IC裝置電氣耦合至該等複數個互連體的傳導材料之步驟包括將複數條導線電氣耦合於該第二IC裝置及該等第二結合墊之間。
  18. 如申請專利範圍第12項之方法，進一步包含：將一或多層的絕緣材料形成於該第一表面上，該一或多層的絕緣材料延伸橫越該第一表面中之該腔穴的一開口，以將該第一IC裝置包封在該腔穴中。
  19. 如申請專利範圍第18項之方法，進一步包含：形成複數個結合墊，其係電氣耦合至該第一IC裝置且至少部份地延伸穿過該一或多層的絕緣材料。
  20. 如申請專利範圍第19項之方法，進一步包含： 形成複數個圓弧狀互連體，其各電氣連接至該等複數個結合墊中的一者。
  21. 如申請專利範圍第12項之方法，其中該第二IC裝置係為一影像感測器，且該第一IC裝置係為一用於處理來自該影像感測器的信號之處理器。
  22. 如申請專利範圍第21項之方法，其中該影像感測器包含一陣列的像素感測器，該陣列的像素感測器各包括一用於將光能轉換成一電壓信號之光偵測器，且其中該處理器係組配來接收該等電壓信號，並對於來自該等像素感測器之該等電壓信號中的每一者運算或內插色彩及明度值。
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US8546900B2 (en) 2013-10-01
US9054013B2 (en) 2015-06-09
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