CN102820282B - 用于集成电路器件的3d集成微电子组件及其制作方法 - Google Patents

用于集成电路器件的3d集成微电子组件及其制作方法 Download PDF

Info

Publication number
CN102820282B
CN102820282B CN201110190703.1A CN201110190703A CN102820282B CN 102820282 B CN102820282 B CN 102820282B CN 201110190703 A CN201110190703 A CN 201110190703A CN 102820282 B CN102820282 B CN 102820282B
Authority
CN
China
Prior art keywords
interconnection
bond pad
hole
conductive material
electrically coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110190703.1A
Other languages
English (en)
Other versions
CN102820282A (zh
Inventor
V.奥加涅相
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Optiz Inc
Original Assignee
Optiz Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Optiz Inc filed Critical Optiz Inc
Publication of CN102820282A publication Critical patent/CN102820282A/zh
Application granted granted Critical
Publication of CN102820282B publication Critical patent/CN102820282B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

本发明涉及用于集成电路器件的3D集成微电子组件及其制作方法。用于封装/包封IC器件的微电子组件，包括具有相对的第一和第二表面以及在第一表面中形成的腔体的晶体基板装卸器、布置在腔体中的第一IC器件和安装到第二表面的第二IC器件以及通过晶体基板装卸器形成的多个互连。互连中的每一个包括通过晶体基板装卸器形成的从第一表面到第二表面的孔、沿着孔的侧壁布置的柔性电介质材料以及沿着柔性电介质材料布置且在第一和第二表面之间延伸的导电材料。柔性电介质材料使导电材料与侧壁绝缘。可以是图像传感器的第二IC器件电耦合到多个互连的导电材料。第一IC可以是用于处理来自图像传感器的信号的处理器。

Description

用于集成电路器件的3D集成微电子组件及其制作方法
技术领域
本发明涉及半导体封装，且更具体而言，涉及一种3D集成封装，其中半导体器件安装在包含另一半导体器件的封装结构上。
背景技术
半导体器件的趋势是封装在较小封装（其在提供芯片外信令连接性时保护芯片）中的较小集成电路（IC）器件（也称为芯片）。使用相关芯片器件（例如，图像传感器及其处理器），实现尺寸减小的一种方式是将两个器件均形成为相同IC芯片的一部分（即，将它们集成到单个集成电路器件中）。然而，这引起可能不利地影响操作、成本和产量的很多复杂制造问题。用于组合相关芯片器件的另一种技术是3DIC封装，其通过在单个封装内部堆叠分离的芯片而节省空间。
3D封装可以导致增加的密度和较小的形状因子、较好的电性能（因为较短的互连长度，这允许增加的器件速度和较低的功耗）、较好的异构集成（即，集成诸如图像传感器及其处理器这样的不同功能层）以及较低的成本。
然而，用于微电子封装的3D集成也面临着挑战，诸如3D处理基础设施和可维持供应链的高成本。包括先通孔（Via-First）、后通孔（Via-Last）和中通孔（Via-middle）工艺的用于形成穿硅通孔（TSV）的现有3DIC封装技术利用本质上复杂且昂贵的半导体光刻工艺。因此，世界上很少公司可以付得起每年的CMOSR&D中的几十亿美元来保持步伐。此外，IC封装之间的互连可能由于制造和安装期间招致的应力以及在操作期间招致的热或振动应力而失败。需要一种补充的、成本有效的TSV解决方案，其通过堆叠和垂直互连多个芯片来实现分离但紧密耦合的图像处理器（实现图像传感器上的像素阵列区域最大化）的使用且实现直接存储器访问。
发明内容
本发明是一种提供用于封装/包封IC器件的新颖晶片级3D集成封装的微电子组件，且实现诸如图像传感器及其处理器这样的多个相关但不同的IC器件的3D集成。微电子组件包括：具有相对的第一和第二表面的晶体基板装卸器（handler），其中在第一表面中形成腔体；布置在腔体中的第一IC器件；安装到第二表面的第二IC器件；以及通过晶体基板装卸器形成的多个互连。每个互连包括通过晶体基板处理器形成的具有在第一和第二表面之间延伸的侧壁的孔、沿着侧壁布置的柔性电介质材料以及沿着柔性电介质材料布置且在第一和第二表面之间延伸的导电材料，其中柔性电介质材料使导电材料与侧壁绝缘。第二IC器件电耦合到多个互连的导电材料。
一种形成微电子组件的方法包括：在具有相对的第一和第二表面的晶体基板装卸器中形成腔体，其中在第一表面中形成腔体；将第一IC器件放置在腔体中；将第二IC器件安装到第二表面；以及形成通过晶体基板装卸器的多个互连。多个互连中的每一个通过以下步骤形成：形成通过晶体基板装卸器的具有在第一和第二表面之间延伸的侧壁的孔、形成沿着侧壁的柔性电介质材料以及形成沿着柔性电介质材料且在第一和第二表面之间延伸的导电材料，其中柔性电介质材料使导电材料与侧壁绝缘。该方法还包括电耦合第二IC器件到多个互连的导电材料。
本发明的其他目的和特征将通过说明书、权利要求书和附图的研究而将变得显见。
附图说明
图1至10是半导体封装结构的剖面侧视图，顺序地示出在将IC器件安装在容放另一IC器件的半导体封装结构上时的封装结构的处理的步骤。
具体实施方式
本发明是对于封装/包封IC器件而言理想的晶片级3DIC集成封装解决方案，且实现诸如图像传感器及其处理器这样的多个相关IC器件的3D集成。3D集成封装的形成在下面描述。
形成工艺开始于如图1中所示的晶体基板装卸器10。非限制性示例包括具有约600μm的厚度的晶体基板的装卸器。如图2所示，在装卸器中形成腔体12。腔体12可以通过使用激光、等离子体蚀刻工艺、喷砂工艺、机械研磨工艺或任意其他类似的方法来形成。优选地，腔体12通过光刻等离子体蚀刻来形成，该光刻等离子体蚀刻包括在装卸器10上形成光致抗蚀剂层、对光致抗蚀剂层图案化以露出装卸器10的选择部分以及然后执行等离子体蚀刻工艺（例如，使用SF6等离子体）以去除装卸器10的露出部分以形成腔体12。优选地，腔体不延伸超过晶体厚度的3/4，或至少在腔体的底部保留约50μm的最小厚度。等离子体蚀刻可以是各向异性的、锥形的、各向同性的或其组合。
然后形成通过装卸器10的厚度、与腔体12相邻但是与腔体12连通的贯通孔（通孔）14。孔14可以使用激光、等离子体蚀刻工艺、喷砂工艺、机械研磨工艺或任意类似方法来形成。优选地，贯通孔14以与形成腔体12的类似方式通过等离子体蚀刻来形成（除了孔14完全通过晶体基板装卸器10的厚度延伸）。等离子体硅蚀刻（例如，各向异性的、锥形的、各向同性的或其组合）允许通孔剖面的各种形状。优选地，孔14的剖面是锥形的，其中在形成腔体12所通过的表面处具有较大的尺寸。优选地，最小孔直径约为25μm，且壁相对于与形成孔14所通过的晶体基板装卸器的表面垂直的方向的角度介于5°和35°之间，使得孔在晶体基板装卸器10的一个表面处具有比在另一表面处更小的剖面尺寸。
如图4中所示，使用旋涂工艺、喷涂工艺、点胶工艺、电化学沉积工艺、层压工艺或任意其他类似方法，贯通孔14然后被填充以柔性（compliant）电介质材料16。柔性电介质是在所有三个正交方向上呈现柔性且可以适应晶体基板（~2.6ppm/°C）和铜（~17ppm/°C）互连之间的热膨胀系数（CTE）失配的相对软的材料（例如，阻焊剂）。柔性电介质材料16优选地是诸如BCB（苯并环丁烯）、阻焊剂、阻焊膜或BT环氧树脂的聚合物。
然后形成通过电介质材料16的贯通孔18。孔18可以通过使用用于较大尺寸的孔18的CO2激光（例如，约70μm的斑点尺寸）或用于较小尺寸的孔18（例如，直径小于50μm）的UV激光（例如，在355nm的波长下约20μm的斑点尺寸）来形成。可以使用脉冲长度小于140ns的介于10和50kHz之间的激光脉冲频率。贯通孔18的侧壁然后被金属化（即，被金属化层20覆盖）。金属化工艺优选地开始于用于去除涂污在贯通孔18的内壁上的任意树脂（由钻通诸如环氧、聚酰亚胺、氰酸酯树脂等的电介质材料导致）的除污工艺。该工艺涉及使用γ-丁内酯和水的混合物接触树脂涂污以软化树脂涂污，接着是用碱性高锰酸盐溶液处理以去除软化的树脂以及用水合酸性中和剂处理以中和并去除高锰酸盐残留。在除污处理之后，初始导电金属化层20通过化学镀铜来形成，接着被光刻回蚀，使得在孔18的两端，金属化层沿着电介质16远离孔18延伸短距离（例如，25μm或更长）（但是不远至与晶体基板10形成电接触）。通过来自表面粗糙度的固着效果而在电镀界面处获得粘合。所得到的结构在图5中示出。
然后在装卸器的不包含腔体22的开孔的表面上形成电介质层22。优选地，这通过使用旋涂工艺或喷涂工艺在装卸器表面上施加光可成像的电介质而完成。光刻工艺（即，UV曝光、选择性材料去除）然后用于选择性地去除在贯通孔18和金属化层20的水平部分之上的电介质22的部分（并且因此露出）。金属层然后被溅射在电介质层22上方。光刻工艺（即，抗蚀剂层沉积、通过掩模的UV曝光、抗蚀剂的选择部分的去除以露出金属层的选择部分、金属蚀刻以及光致抗蚀剂去除）用于选择性地去除金属层的部分，留下沉积在贯通孔18上且与金属化层20电接触的金属焊盘24。所得到的结构在图6中示出。尽管没有示出，金属焊盘24的中心可以具有通过那里与贯通孔18对准的小孔。
如图7所示，IC芯片26被插入到腔体12中。IC芯片26包括集成电路（即，半导体器件）。IC芯片26通过电介质绝缘层28而与装卸器10绝缘。IC芯片26的插入和绝缘层28的形成可以以若干方式执行。一种方式是在插入裸IC芯片26之前在腔体12的壁上形成绝缘层28（例如通过喷涂环氧、通过电化学沉积等）。第二种方式是在芯片26被插入到腔体12之前在IC芯片26的背面上形成绝缘层28。第三种方式是在芯片插入之前在腔体壁和IC芯片背面上均形成绝缘层，其中两个绝缘层在芯片插入时接合在一起以形成绝缘层28。IC芯片26包括在其底面上露出的接合焊盘30。
然后在在腔体12内包封了IC芯片26的结构上形成包封绝缘层32。优选地，层32使用光可成像的电介质（例如，阻焊剂）来形成。该层被预固化以部分去除溶剂，因此表面不粘。然后执行光刻步骤（即通过掩模的UV曝光），在此之后，绝缘层32的选择部分被去除以露出IC芯片接合焊盘30和延伸出贯通孔18的金属化层20。然后执行后固化以增加层32的表面硬度。然后在绝缘层32上方沉积金属层（例如，通过金属溅射，接着是光可成像的抗蚀剂层的沉积）。然后执行光刻步骤（即，通过掩模的UV曝光和选择性抗蚀剂层去除），接着是通过光致抗蚀剂去除而露出的那些部分的选择性金属蚀刻，留下与IC芯片接合焊盘30电接触的金属扇出和扇入接合焊盘34，且留下与延伸出贯通孔18的金属化层20电接触的互连接合焊盘36。此处也可以发生接合焊盘34/36的金属电镀。所得到的结构在图8中示出（在光致抗蚀剂去除之后）。
包封绝缘层38然后在绝缘层32和接合焊盘34/36上方形成，接着是选择性回蚀以露出接合焊盘34/36。选择性回蚀可以通过光刻工艺执行以选择性地去除接合焊盘34/36上方的层38的那些部分。然后使用焊接合金的丝网印刷工艺或通过植球工艺或通过电镀工艺在接合焊盘34/36上形成BGA互连40。BGA（球栅阵列）互连是通常通过焊接或部分熔融金属球到接合焊盘上形成的用于与对等导体形成物理和电接触的圆形导体。所得的结构在图9中示出。
如图10中所示，IC芯片组件42然后被附接到绝缘层22上。附接可以使用常规拾放或管芯附接装置来执行。胶带或可印刷/可分配的环氧材料可以用作粘合剂。IC芯片组件42包括第二IC芯片44以及用于到IC芯片44的信号连接的CIS接合焊盘46。在图10所示的示例性实施例中，IC芯片44是图像传感器，其包括基板45、像素传感器阵列47以及滤色片和微透镜阵列48。理想地，IC芯片26是用于图像传感器的处理器。Au或Cu引线接合50然后被附接以电连接CIS接合焊盘中的每一个到互连金属焊盘24之一。
上面描述且在附图中示出的IC封装技术及其制造方法具有若干优点。首先，硅基IC芯片26容放在晶体基板10内，该晶体基板10提供IC芯片26的机械和环境保护。其次，利用用于将IC芯片26固定在晶体基板10内的柔性电介质材料28减小了可能不利地影响二者的热和机械应力。第三，使用具有用于封装IC芯片26的扇出和扇入焊盘的晶体基板封装结构（其可以在插入到封装10之前单独测试和验证）增强了可靠性和产量。第四，在两个芯片的组合中，将芯片之一容放在晶体基板封装结构10内（另一芯片安装在其上）增强了可靠性且提供了更快速和更可靠的信号互连方案。第五，用于两个芯片的电互连在装卸器10的公共表面上提供，用于高效的信号耦合和连接。第六，利用用于层32的晶片级电介质层叠在很宽的频率范围上提供很低的阻抗。该阻抗可以与现有喷涂和旋涂电介质具有相同或更低的数量级。这些超薄电介质层叠还提供抑制关于电源和接地面的噪声的优点且对于在未来高速数字设计中实现可接受电性能而言将是重要的。
通过孔18形成的贯通聚合物互连还具有很多优点。首先，这些互连是可靠地将电信号从芯片44通过装卸器10重新路由到包含用于IC芯片26的电接触的装卸器10的相同侧的导电元件。其次，通过形成具有斜面的贯通孔14的壁，减小在晶体基板上潜在地损害性诱生应力，该诱生应力可能来自于90度拐角。第三，孔14的倾斜侧壁还意味着不存在可能导致与电介质材料16一起形成的缝隙的负角度区域。第四，通过先形成绝缘材料16，然后在其上形成金属化层20，向装卸器10的晶体基板结构的金属扩散得以避免。第五，使用电镀工艺形成金属层20优于诸如溅射沉积之类的其它金属化技术，因为电镀工艺更不倾向于损害绝缘材料16。第六，使用柔性绝缘材料16来形成孔18的侧壁是更加可靠的。第七，使用激光钻通聚合物、除污以及金属电镀的贯通聚合物互连的创建比使用半导体溅射和金属沉积工艺更便宜。最后，用于第二IC芯片44的引线接合布置在封装结构10与用于第一IC芯片26的接合焊盘相对的一侧上，这实现芯片之间的最短电学路径且消除了对用于图像传感器的组件的挠性和/或有机封装装卸器的需要。
上述封装配置理想地用于（但不必限制于）IC芯片44是图像传感器且IC芯片26是用于处理来自图像传感器的信号的处理器的上下文且在该上下文中被描述。图像传感器是包括集成电路的互补金属氧化物半导体（CMOS）器件，该集成电路含有像素传感器阵列，每个像素包含光电检测器以及优选地其自己的有源放大器。每个像素传感器将光能转换成电压信号。可以在芯片上包括附加电路以将电压转换成数字数据。图像处理芯片包含（一个或多个）硬件处理器和软件算法的组合。图像处理器收集来自各个像素传感器的亮度和色度信息且使用它来计算/插值对于每个像素的正确的颜色和亮度值。图像处理器估算给定像素的颜色和亮度数据，将它们与来自相邻像素的数据进行比较且然后使用去马赛克算法以从不完整的颜色样品重构全色图像且产生用于该像素的适当亮度值。图像处理器还评估完整图片且校正锐度并减小图像的噪声。
图像传感器的演变导致图像传感器中的日益更高的像素计数以及诸如自动聚焦、缩放和红眼消除、人脸跟踪等的附加照相机功能性，这要求可以以更高速度操作的更强大的图像传感器处理器。摄影师不希望在他们可以实施拍摄之前等待照相机的图像处理器完成其工作，他们甚至不希望告知某些处理正在照相机内部进行。因此，图像处理器必须优化以在相同甚至更短的时间周期内处理更多的数据。
要注意，本发明不限于上面描述和此处示出的（一个或多个）实施例，而是涵盖落在所附权利要求的范围内的任意和所有变型。例如，此处对于本发明的引用并不旨在限制任意权利要求或权利要求术语的范围，而是相反仅引用可以被一个或多个权利要求覆盖的一个或多个特征。上述的材料、工艺和数值示例仅是示例性的，且不应认为限制了权利要求。而且，从权利要求和说明书显见，并不是所有方法步骤必须以示出或要求保护的确切顺序执行，而是以允许本发明的IC封装的适当形成的任意顺序单独或同时执行。单层材料可以形成为这种或类似材料的多层，且反之亦然。尽管在IC芯片26是图像传感器处理器且IC芯片44是图像传感器的上下文中公开了本发明的封装配置，但是本发明不必限制于那些IC芯片。
应当注意，如此使用的术语“上方”和“上”均包括性包括“直接位于…上”（没有布置于其间的中间材料、元件或空间）和“间接位于…上”（有布置于其间的中间材料、元件或空间）。同样，术语“相邻”包括“直接相邻”（没有布置于其间的中间材料、元件或空间）和“间接相邻”（有布置于其间的中间材料、元件或空间），“安装到”包括“直接安装到”（没有布置于其间的中间材料、元件或空间）和“间接安装到”（有布置于其间的中间材料、元件或空间），且“电耦合”包括“直接电偶合到”（其间没有把元件电连接在一起的中间材料或元件）和“间接电耦合到”（其间有把元件电连接在一起的中间材料或元件）。例如，“在基板上方”形成元件可以包括直接在基板上形成元件，其间没有中间材料/元件，也可以在基板上间接形成元件，其间具有一个或多个中间材料/元件。

Claims (14)

1.一种微电子组件，包含：
具有相对的第一和第二表面的晶体基板装卸器，其中在第一表面中形成腔体；
布置在腔体中的第一IC器件；
安装到第二表面的第二IC器件；
通过晶体基板装卸器形成的多个第一互连，其中每个第一互连包含：
通过晶体基板装卸器形成的具有在第一和第二表面之间延伸的侧壁的孔，
沿着侧壁布置的柔性电介质材料，以及
沿着柔性电介质材料布置且在第一和第二表面之间延伸的导电材料，其中柔性电介质材料使导电材料与侧壁绝缘；
其中第二IC器件电耦合到多个第一互连的导电材料，其中针对多个第一互连中的每一个，侧壁相对于与第一和第二表面垂直的方向在5°和35°之间的方向上延伸；
一层或多层绝缘材料，其被布置在第一表面上且跨越将第一IC器件包封在腔体中的第一表面中的腔体的开孔延伸；
多个第一接合焊盘，其被电耦合到第一IC器件；
多个第二互连，每个第二互连被电耦合到所述多个第一接合焊盘中的一个，其中所述第一接合焊盘中的每个以及与其耦合的第二互连从所述第一IC器件延伸通过所述一层或多层绝缘材料；
多个第二接合焊盘，每个所述第二接合焊盘被布置在所述第一表面处的孔中的一个的上方且被电耦合到所述导电材料；以及
多个第三互连，每个第三互连被电耦合到所述多个第二接合焊盘中的一个，其中所述第二接合焊盘中的每个以及与其耦合的第三互连从所述第一互连中的一个延伸通过所述一层或多层绝缘材料。
2.根据权利要求1所述的微电子组件，其中柔性电介质材料包括聚合物。
3.根据权利要求1所述的微电子组件，其中针对多个第一互连中的每一个，孔是锥形的，使得孔在第二表面处比在第一表面处具有更小的剖面尺寸。
4.根据权利要求1所述的微电子组件，其中多个第一互连中的每一个还包含：
第三接合焊盘，其被布置在第二表面处的孔的上方且电耦合到导电材料。
5.根据权利要求4所述的微电子组件，其中第二IC器件通过电耦合到第三接合焊盘的多个引线而电耦合到多个互连的导电材料。
6.根据权利要求1所述的微电子组件，其中第二IC器件是图像传感器且第一IC器件是用于处理来自图像传感器的信号的处理器。
7.根据权利要求6所述的微电子组件，其中图像传感器包含像素传感器阵列，每个像素传感器包括用于将光能转换成电压信号的光电检测器，且其中处理器配置成接收电压信号且计算或插值对于来自像素传感器的电压信号中的每一个的颜色和亮度值。
8.一种形成微电子组件的方法，包含：
在具有相对的第一和第二表面的晶体基板装卸器中形成腔体，其中在第一表面中形成腔体；将第一IC器件放置在腔体中；
将第二IC器件安装到第二表面；
形成通过晶体基板装卸器的多个第一互连，其中多个第一互连中的每一个通过以下步骤形成：
形成通过晶体基板装卸器的具有在第一和第二表面之间延伸的侧壁的孔，
形成沿着侧壁的柔性电介质材料，
形成沿着柔性电介质材料且在第一和第二表面之间延伸的导电材料，其中柔性电介质材料使导电材料与侧壁绝缘；以及
电耦合第二IC器件到多个第一互连的导电材料，其中针对多个第一互连中的每一个，侧壁相对于与第一和第二表面垂直的方向在5°和35°之间的方向上延伸；
形成一层或多层绝缘材料，其在第一表面上且跨越将第一IC器件包封在腔体中的第一表面中的腔体的开孔延伸；
形成多个第一接合焊盘，其被电耦合到第一IC器件；
形成多个第二互连，每个第二互连被电耦合到所述多个第一接合焊盘中的一个，其中所述第一接合焊盘中的每个以及与其耦合的第二互连从所述第一IC器件延伸通过所述一层或多层绝缘材料；
形成多个第二接合焊盘，每个所述第二接合焊盘被布置在所述第一表面处的孔中的一个的上方且被电耦合到所述导电材料；以及
形成多个第三互连，每个第三互连被电耦合到所述多个第二接合焊盘中的一个，其中所述第二接合焊盘中的每个以及与其耦合的第三互连从所述第一互连中的一个延伸通过所述一层或多层绝缘材料。
9.根据权利要求8所述的方法，其中柔性电介质材料包括聚合物。
10.根据权利要求8所述的方法，其中针对多个第一互连中的每一个，孔是锥形的，使得孔在第二表面处比在第一表面处具有更小的剖面尺寸。
11.根据权利要求8所述的方法，其中多个互连中的每一个的形成还包含：
形成第三接合焊盘，该第三接合焊盘在第二表面处的孔的上方且电耦合到导电材料。
12.根据权利要求11所述的方法，其中电耦合第二IC器件到多个互连的导电材料包括在第二IC器件和第三接合焊盘之间电耦合多个引线。
13.根据权利要求8所述的方法，其中第二IC器件是图像传感器且第一IC器件用于处理来自该图像传感器的信号的处理器。
14.根据权利要求13所述的方法，其中图像传感器包含像素传感器阵列，每个像素传感器包括用于将光能转换成电压信号的光电检测器，且其中处理器配置成接收电压信号且计算或插值对于来自像素传感器的电压信号中的每一个的颜色和亮度值。
CN201110190703.1A 2011-06-09 2011-07-08 用于集成电路器件的3d集成微电子组件及其制作方法 Active CN102820282B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/157193 2011-06-09
US13/157,193 2011-06-09
US13/157,193 US8546900B2 (en) 2011-06-09 2011-06-09 3D integration microelectronic assembly for integrated circuit devices

Publications (2)

Publication Number Publication Date
CN102820282A CN102820282A (zh) 2012-12-12
CN102820282B true CN102820282B (zh) 2016-06-29

Family

ID=47292451

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110190703.1A Active CN102820282B (zh) 2011-06-09 2011-07-08 用于集成电路器件的3d集成微电子组件及其制作方法

Country Status (4)

Country Link
US (2) US8546900B2 (zh)
KR (1) KR101384912B1 (zh)
CN (1) CN102820282B (zh)
TW (1) TWI475649B (zh)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8604576B2 (en) * 2011-07-19 2013-12-10 Opitz, Inc. Low stress cavity package for back side illuminated image sensor, and method of making same
TWI462266B (zh) * 2012-03-20 2014-11-21 Chipmos Technologies Inc 晶片堆疊結構及其製造方法
US9159699B2 (en) * 2012-11-13 2015-10-13 Delta Electronics, Inc. Interconnection structure having a via structure
AT513747B1 (de) 2013-02-28 2014-07-15 Mikroelektronik Ges Mit Beschränkter Haftung Ab Bestückungsverfahren für Schaltungsträger und Schaltungsträger
CN104051489B (zh) * 2013-03-12 2017-09-08 奥普蒂兹公司 小轮廓图像传感器
US20140353019A1 (en) * 2013-05-30 2014-12-04 Deepak ARORA Formation of dielectric with smooth surface
US9142695B2 (en) * 2013-06-03 2015-09-22 Optiz, Inc. Sensor package with exposed sensor array and method of making same
US11574889B2 (en) * 2013-06-04 2023-02-07 Infineon Technologies Ag Power module comprising two substrates and method of manufacturing the same
US9461190B2 (en) 2013-09-24 2016-10-04 Optiz, Inc. Low profile sensor package with cooling feature and method of making same
US9391002B2 (en) 2013-11-21 2016-07-12 Amphenol Thermometrics, Inc. Semiconductor sensor chips
US9379072B2 (en) * 2013-11-27 2016-06-28 Xintec Inc. Chip package and method for forming the same
US9496297B2 (en) 2013-12-05 2016-11-15 Optiz, Inc. Sensor package with cooling feature and method of making same
US9667900B2 (en) 2013-12-09 2017-05-30 Optiz, Inc. Three dimensional system-on-chip image sensor package
US9711485B1 (en) * 2014-02-04 2017-07-18 Amkor Technology, Inc. Thin bonded interposer package
US9666730B2 (en) 2014-08-18 2017-05-30 Optiz, Inc. Wire bond sensor package
JP2016058628A (ja) * 2014-09-11 2016-04-21 株式会社東芝 半導体装置、及び半導体装置の製造方法
US9543347B2 (en) 2015-02-24 2017-01-10 Optiz, Inc. Stress released image sensor package structure and method
US10468363B2 (en) 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts
US9590580B1 (en) * 2015-09-13 2017-03-07 Guoguang Electric Company Limited Loudness-based audio-signal compensation
KR101964853B1 (ko) * 2015-11-11 2019-04-02 주식회사 지파랑 광 인터페이스를 가지는 반도체 칩 패키지
EP3168874B1 (en) 2015-11-11 2020-09-30 Lipac Co., Ltd. Semiconductor chip package with optical interface
US10038025B2 (en) * 2015-12-29 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Via support structure under pad areas for BSI bondability improvement
US10103069B2 (en) 2016-04-01 2018-10-16 X-Celeprint Limited Pressure-activated electrical interconnection by micro-transfer printing
EP3243793B1 (en) * 2016-05-10 2018-11-07 ams AG Sensor assembly and arrangement and method for manufacturing a sensor assembly
US10222698B2 (en) 2016-07-28 2019-03-05 X-Celeprint Limited Chiplets with wicking posts
US11064609B2 (en) 2016-08-04 2021-07-13 X Display Company Technology Limited Printable 3D electronic structure
US9996725B2 (en) 2016-11-03 2018-06-12 Optiz, Inc. Under screen sensor assembly
CN109950236A (zh) * 2017-12-21 2019-06-28 北京万应科技有限公司 传感器微系统封装方法及传感器微系统
US11638353B2 (en) * 2018-09-17 2023-04-25 Hutchinson Technology Incorporated Apparatus and method for forming sensors with integrated electrical circuits on a substrate
NL2022062B1 (en) * 2018-11-23 2020-06-05 Ampleon Netherlands Bv Rf power amplifier pallet
CN111627939B (zh) * 2019-02-27 2023-04-18 中芯集成电路（宁波）有限公司 Cmos图像传感器封装模块及其形成方法、摄像装置
CN110211946A (zh) * 2019-06-17 2019-09-06 上海先方半导体有限公司 一种芯片封装结构及其制造方法
US11408589B2 (en) 2019-12-05 2022-08-09 Optiz, Inc. Monolithic multi-focus light source device
US11387178B2 (en) 2020-03-06 2022-07-12 X-Celeprint Limited Printable 3D electronic components and structures
US11490519B2 (en) 2021-01-11 2022-11-01 X-Celeprint Limited Printed stacked micro-devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101232033A (zh) * 2007-01-23 2008-07-30 育霈科技股份有限公司 影像感测器模块与其方法

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739581A (en) 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
IL123207A0 (en) 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
US6191952B1 (en) * 1998-04-28 2001-02-20 International Business Machines Corporation Compliant surface layer for flip-chip electronic packages and method for forming same
JP2001007468A (ja) * 1999-06-24 2001-01-12 Nec Kansai Ltd 配線基板，多層配線基板およびその製造方法
IL133453A0 (en) 1999-12-10 2001-04-30 Shellcase Ltd Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US7033664B2 (en) 2002-10-22 2006-04-25 Tessera Technologies Hungary Kft Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US6972480B2 (en) 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
KR101078621B1 (ko) 2003-07-03 2011-11-01 테쎄라 테크놀로지스 아일랜드 리미티드 집적회로 디바이스를 패키징하기 위한 방법 및 장치
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
JP4966487B2 (ja) * 2004-09-29 2012-07-04 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
US7936062B2 (en) 2006-01-23 2011-05-03 Tessera Technologies Ireland Limited Wafer level chip packaging
IL175011A (en) 2006-04-20 2011-09-27 Amitech Ltd Coreless cavity substrates for chip packaging and their fabrication
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7935568B2 (en) 2006-10-31 2011-05-03 Tessera Technologies Ireland Limited Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US7807508B2 (en) 2006-10-31 2010-10-05 Tessera Technologies Hungary Kft. Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US20080136002A1 (en) * 2006-12-07 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US7749886B2 (en) 2006-12-20 2010-07-06 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
US7538413B2 (en) * 2006-12-28 2009-05-26 Micron Technology, Inc. Semiconductor components having through interconnects
US20080174008A1 (en) * 2007-01-18 2008-07-24 Wen-Kun Yang Structure of Memory Card and the Method of the Same
US7446303B2 (en) * 2007-01-31 2008-11-04 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd Ambient light sensing using a color sensor
EP2575166A3 (en) 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US8148255B2 (en) * 2007-09-18 2012-04-03 International Business Machines Corporation Techniques for forming solder bump interconnects
KR101572600B1 (ko) 2007-10-10 2015-11-27 테세라, 인코포레이티드 다층 배선 요소와 마이크로전자 요소가 실장된 어셈블리
US20090212381A1 (en) 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US20100053407A1 (en) 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US20110024899A1 (en) * 2009-07-28 2011-02-03 Kenji Masumoto Substrate structure for cavity package
US8399987B2 (en) * 2009-12-04 2013-03-19 Samsung Electronics Co., Ltd. Microelectronic devices including conductive vias, conductive caps and variable thickness insulating layers
US20110186960A1 (en) * 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8697569B2 (en) 2010-07-23 2014-04-15 Tessera, Inc. Non-lithographic formation of three-dimensional conductive elements
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8686565B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Stacked chip assembly having vertical vias
US8685793B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Chip assembly having via interconnects joined by plating
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US20120194719A1 (en) * 2011-02-01 2012-08-02 Scott Churchwell Image sensor units with stacked image sensors and image processors

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101232033A (zh) * 2007-01-23 2008-07-30 育霈科技股份有限公司 影像感测器模块与其方法

Also Published As

Publication number Publication date
TWI475649B (zh) 2015-03-01
US9054013B2 (en) 2015-06-09
US20140004646A1 (en) 2014-01-02
KR20120137254A (ko) 2012-12-20
TW201304079A (zh) 2013-01-16
CN102820282A (zh) 2012-12-12
US8546900B2 (en) 2013-10-01
KR101384912B1 (ko) 2014-04-11
US20120313207A1 (en) 2012-12-13

Similar Documents

Publication Publication Date Title
CN102820282B (zh) 用于集成电路器件的3d集成微电子组件及其制作方法
CN102820274B (zh) 具有应力减小互连的3d集成微电子组件及其制作方法
KR102620629B1 (ko) 반도체 장치의 제조 방법
CN102891151B (zh) 背照式图像传感器的低应力腔体封装及其制作方法
US8716873B2 (en) Semiconductor packages and methods of packaging semiconductor devices
CN110660680B (zh) 半导体结构的形成方法
KR101420934B1 (ko) Ｃｍｏｓ 이미지 센서를 위한 와이어 본드 인터포저 패키지 및 그 제조 방법
WO2015183959A1 (en) Structure and method for integrated circuits packaging with increased density
JP2007019454A (ja) チップ挿入型媒介基板の構造及びその製造方法、並びにこれを用いた異種チップのウェーハレベル積層構造及びパッケージ構造
CN101789380B (zh) 内埋芯片封装的结构及工艺
US20070138630A1 (en) Structure of circuit board and method for fabricating same
KR101532816B1 (ko) 반도체 패키지 및 반도체 소자 패키징 방법
JP2005235860A (ja) 半導体装置及びその製造方法
CN111128914A (zh) 一种低翘曲的多芯片封装结构及其制造方法
US8450844B2 (en) Semiconductor package and method of manufacturing the same
CN110854093A (zh) 一种三维叠层封装结构及其制造方法
CN102544040B (zh) 利用TSV技术实现GaAs图像传感器的圆片级封装方法
CN102224579B (zh) 半导体装置及电子设备
JP2004343088A (ja) 半導体装置及びその製造方法
US20130292832A1 (en) Semiconductor package and fabrication method thereof
CN116314155A (zh) 芯片封装器件、衬底集成结构、芯片封装结构和封装方法
CN113937017A (zh) 晶圆级封装方法
KR101150464B1 (ko) 반도체 소자 및 그 형성 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant