TWI545710B - 具有應力減低互連體之3d積體微電子總成及其製造方法 - Google Patents
具有應力減低互連體之3d積體微電子總成及其製造方法 Download PDFInfo
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Description
本發明係有關半導體封裝,且更特別有關一其中將一半導體裝置封裝體安裝在另一半導體裝置封裝體上之3D積體封裝體。
半導體裝置趨勢係在於被封裝在更小封裝體(其保護晶片同時提供晶片外信號連接性)中之更小的積體電路(IC)裝置(亦稱為晶片)。對於相關的晶片裝置(譬如一影像感測器及其處理器)而言,一種達成尺寸減小的方式係將兩裝置形成為相同IC晶片的部份(亦即將其積造在單一積體電路裝置內)。然而,如此將造成眾多複雜的製造議題,這會不利地影響操作、成本及良率。另一種用以組合相關晶片裝置之技術係為3D IC封裝,其藉由將分離的晶片堆積在單一封裝體內或將一晶片包裝件堆積在另一晶片封裝體上來節省空間。
3D封裝可導致增高的密度及較小的形狀因數(form factor)、較好的電性效能(因為較短的互連體長度容許具有增高的裝置速度及較低的功率消耗)、較好的異質積造(亦即積造諸如一影像感測器及其處理器等不同的功能層)、及較低的成本。
然而,用於微電子封裝之3D積造亦面臨到挑戰,諸如
3D處理基礎建設及可存續供應鏈的高成本。包括先鑽孔(Via-First)、後鑽孔(Via-Last)及中鑽孔(Via-middle)製程等用以形成貫通矽導孔(TSV)之既有3D IC封裝技術係利用先天即複雜且昂貴的半導體微影製程。結果,世上少有公司能負擔每年數十億美元計的CMOS研發費用以求跟上腳步。並且,IC封裝體之間的互連體會由於製造及安裝期間所受的應力、暨操作期間所受的熱或振動應力而失效。需要一種具互補性、合乎成本效益的TSV解決方案以能夠使用一能令影像感測器上的像素陣列區域達到最大化之分離但密切耦合的影像處理器,且能夠藉由將多重的晶片堆積及垂直互連而具有直接記憶體存取。
本發明係為一微電子總成,其提供一用於封裝/包封IC裝置之新穎的3D積體封裝體,並能夠3D積造諸如一影像感測器與其處理器等多重相關但不同的IC裝置。
該微電子總成係包含第一及第二微電子元件。第一微電子元件係包括一具有第一及第二相對表面之基材,一半導體裝置,及電性耦合至半導體裝置之位於第一表面的傳導墊。第二微電子元件係包括一具有第一及第二相對表面之處置器,一第二半導體裝置,及電性耦合至第二半導體裝置之位於處置器第一表面的傳導墊。第一及第二微電子元件係被積造至彼此使得第二表面面對彼此。第一微電子元件包括傳導元件,各傳導元件從傳導墊的一者延伸且經
過基材至第一微電子元件的第二表面。第二微電子元件係包括傳導元件,各傳導元件延伸於處置器的第一及第二表面之間。第一微電子元件之傳導元件的各者係電性耦合至第二微電子元件的傳導元件的至少一者。
形成微電子總成之方法係包含提供第一及第二微電子元件。第一微電子元件係包含一具有第一及第二相對表面之基材,一半導體裝置,及電性耦合至半導體裝置之位於第一表面的傳導墊。第二微電子元件係包含一具有第一及第二相對表面之處置器,一第二半導體裝置,及電性耦合至第二半導體裝置之位於處置器第一表面的傳導墊。該方法進一步包含形成傳導元件,各傳導元件從傳導墊的一者延伸且經過基材至第一微電子元件的第二表面,形成傳導元件,各傳導元件延伸於處置器的第一及第二表面之間,及將第一及第二微電子元件積造至彼此使得第二表面面對彼此且使得第一微電子元件之傳導元件的各者電性耦合至第二微電子元件之傳導元件的至少一者。
將經由檢閱說明書、申請專利範圍及附圖得知本發明的其他目的及特徵構造。
第1至10圖是一半導體封裝結構之橫剖側視圖,其依順序顯示在形成第一封裝結構中之封裝結構的處理中之步驟;第11至17圖是一半導體封裝結構之橫剖側視圖,其依順序顯示在形成第二封裝結構中之封裝結構的處理中之步
驟;第18圖是被安裝至第一封裝結構之第二封裝結構的橫剖側視圖。
本發明係為可理想用於封裝/包封IC裝置、並能夠3D積造諸如影像感測器及其處理器等多重相關的IC裝置之晶圓層級3D IC積體封裝體解決方案。3D積體封裝體的形成係描述於下文,首先是形成用於一第一IC裝置之一第一封裝體、然後是用於一第二IC封裝體之一第二封裝體,然後是積造兩封裝體以形成一用於積造兩IC裝置之微電子總成。
第1至10圖顯示第一封裝體1的形成。第一封裝體形成製程開始係為如第1圖所示的一晶系處置器10。一非限制性範例可包括具有約600μm厚度之晶系的一處置器。一腔穴12形成於處置器中,如第2圖所示。腔穴12可利用一雷射、一電漿蝕刻製程、一噴砂製程、一機械銑製製程、或任何其他類似方法形成。較佳地,腔穴12藉由光微影術電漿蝕刻形成,其包括形成一層光阻於處置器10上,將光阻層圖案化以曝露處置器10的一選擇部分,且然後進行一電漿蝕刻製程(譬如使用一SF6電漿)以移除處置器10的經曝露部分以形成腔穴12。較佳地,腔穴延伸不超過晶系厚度的3/4,或至少在腔穴底部留下約50μm的最小厚度。電漿蝕刻可為異向性、推拔狀、等向性、或其組合。
通孔(導孔)14隨後與腔穴12相鄰但連接地形成經過處
置器10的厚度,如第3圖所示。孔14可利用一雷射、一電漿蝕刻製程、一噴砂製程、一機械銑製製程、或任何類似方法形成。較佳地,通孔14利用與形成腔穴12類似的方式藉由電漿蝕刻形成(差異在於孔14一路延伸經過晶系處置器10的厚度)。電漿矽蝕刻(譬如異向性、推拔狀、等向性、或其組合)係容許具有不同形狀的導孔輪廓。較佳地,孔14的輪廓為推拔狀,其中一較大維度係位於可供經過其形成腔穴12之表面上。較佳地,最小孔直徑為約25μm,且壁的角度相對於與可供經過其形成孔14之晶系處置器表面呈正交的方向位於5°至35°之間,俾使孔在晶系處置器10的一表面上具有比另一表面更小的橫剖面尺寸。
通孔14隨後利用一旋塗製程、一噴灑製程、一配送製程、一電化沉積製程、一層疊製程、或任何其他的類似方法充填一順應性介電材料16,如第4圖所示。一順應性介電質係為在三正交方向皆展現順應性且可容納矽(~2.6ppm/℃)與Cu(~17ppm/℃)互連體之間的熱膨脹係數(CTE)不匹配之一種相對軟材料(譬如銲罩)。順應性介電材料16較佳係為一聚合物,諸如BCB(苯環丁烯)、銲罩、銲阻、或BT環氧樹脂。
通孔18隨後形成經過介電材料16。可利用對於較大尺寸的孔18的一CO2雷射(譬如約70μm的斑點尺寸)、或對於較小尺寸的孔18(譬如小於50μm直徑)的一UV雷射(譬如在355nm波長之約20μm的斑點尺寸)來形成孔18。可使用小於140ns脈衝長度位於10及50kHz之間的雷射脈衝頻率。通孔
18的側壁可隨後被金屬化(亦即塗覆有一金屬化層20)。金屬化製程較佳開始係為用於移除通孔18內部壁上髒污(由鑽過諸如環氧樹脂、聚醯亞胺、氰酸鹽酯樹脂等介電材料所造成)的任何樹脂之去污製程。該製程係涉及使樹脂髒污與γ丁內酯與水的一混合物作接觸以軟化樹脂髒污,接著以一鹼性過錳酸鹽溶液作處理以移除軟化的樹脂,並以一水性酸性中和劑作處理以中和並移除過錳酸鹽殘留物。在去污處理之後,初始傳導金屬化層20係由無電極銅鍍覆形成,接著係為一光微影術回蝕使得金屬化層在孔18的兩端以一段短距離(譬如25μm或以上)沿著介電材料16延伸遠離孔18(但未遠到與晶系處置器10產生電性接觸)。藉由來自表面粗度的一錨固效應在經鍍覆介面獲得黏著。所產生的結構顯示於第5圖。
一介電層22隨後形成於不含通往腔穴12的開口之處置器的表面上。較佳地,利用一旋塗製程或一噴灑製程將一可光成像性介電質施加於處置器表面上來達成此作用。然後使用一光微影性製程(亦即UV曝光、選擇性材料移除)來選擇性移除通孔18上方(且因此使其曝露)之介電層22的部分及金屬化層20的水平部分。一金屬層隨後被濺鍍於介電層22上方。使用一光微影性製程(亦即阻劑層沉積、經過一罩幕的UV曝光、阻劑的選定部分之移除以曝露金屬層的選定部分、金屬蝕刻、及光阻移除)來選擇性移除金屬層的部分,而留下配置於通孔18上方且與金屬化層20電性接觸之金屬墊24。所產生的結構顯示於第6圖。雖然未圖示,金屬
墊24的中心可穿設有一與通孔18對準之小孔。
一IC晶片26被插入腔穴12內,如第7圖所示。IC晶片26係包括一積體電路(亦即半導體裝置)27。IC晶片26藉由一介電絕緣層28而與處置器10絕緣。IC晶片26的插入及絕緣層28的形成可以數種方式進行。一種方式係在裸IC晶片26插入之前(譬如藉由噴塗環氧樹脂、藉由電化沉積等)將絕緣層28形成於腔穴12的壁上。第二種方式係在被插入腔穴12內之前將絕緣層28形成於IC晶片26的背表面上。第三種方式係在晶片插入之前將絕緣層形成於腔穴壁上及IC晶片背表面上,其中兩絕緣層在晶片插入時被結合在一起,以形成絕緣層28。IC晶片26包括在其底表面上曝露之結合墊30。
一包封絕緣層32隨後形成於結構上,其將IC晶片26包封在腔穴12內。較佳地,利用一可光成像性介電質(譬如一銲罩)形成層32。該層被預固化以部份地移除溶劑使得表面不黏。然後進行一光微影術步驟(亦即經過罩幕的UV曝光),其後移除絕緣層32的選擇部分以曝露IC晶片結合墊30及延伸出通孔18外的金屬化層20。然後可進行後固化以增大層32的表面硬度。一金屬層隨後沉積在絕緣層32上方(譬如藉由金屬濺鍍,接著是一可光成像性阻劑層之沉積)。然後進行一光微影術步驟(亦即,經過罩幕的UV曝光以及選擇性阻劑層移除),接著是藉由光阻移除所曝露的部分之選擇性金屬蝕刻,而留下與IC晶片結合墊30電性接觸之金屬扇出及扇入結合墊34,且留下與延伸出通孔18外的金屬化層20電性接觸之互連體結合墊36。此處亦可發生結合墊34/36
的金屬鍍覆。所產生的結構顯示於第8圖(在光阻移除之後)。
一包封絕緣層38隨後形成於絕緣層32及結合墊34/36上方,接著是一選擇性回蝕以曝露結合墊34/36。選擇性回蝕可藉由一光微影製程進行以選擇性移除結合墊34/36上方之層38的部分。BGA互連體40隨後利用一銲料合金的一絲網印刷製程、或藉由一球置放製程、或藉由一鍍覆製程而形成於結合墊34/36上方。BGA(球柵陣列)互連體係為用於與對偶導體產生物理及電性接觸之圓弧形導體,通常藉由將金屬球銲接或部份地融化在結合墊上所形成。所產生的結構顯示於第9圖。
一金屬層隨後沉積在該介電層22上方(譬如藉由金屬濺鍍,接著是一可光成像性阻劑層之沉積)。然後進行一光微影術步驟(亦即,經過罩幕的UV曝光以及選擇性阻劑層移除),接著是藉由光阻移除所曝露的那些部分之選擇性金屬蝕刻,而留下與金屬墊24電性接觸之金屬扇出及扇入結合墊52。此處亦可發生結合墊52的金屬鍍覆。一絕緣層54隨後形成於該介電層22及結合墊52上方,接著係為一選擇性回蝕以曝露結合墊52的選擇部分。選擇性回蝕可由一光微影製程進行以選擇性移除結合墊52的選擇部分上方之層54的那些部分。所產生的結構係為第10圖所示的微電子裝置(在光阻移除之後)。
第11至17圖顯示第二封裝體的形成。第二封裝體形成製程開始係為一順應性支撐性結構,譬如一聚合物片60,如第11圖所示。一非限制性範例可包括具有約100μm厚度之
一片聚合物。一孔62係形成經過聚合物片60,如第12圖所示。孔62可利用一雷射、一電漿蝕刻製程、一噴砂製程、一機械銑製製程、或任何其他的類似方法形成。較佳地,孔62由一雷射形成。一諸如透明玻璃晶圓等透明保護性層64係附接至順應性聚合物片60,其在該處覆蓋住孔62,如第13圖所示。較佳地,保護性層64至少為100μm厚。
順應性聚合物片及保護性層60/64隨後附接至一第二IC晶片66,如第14圖所示。在第14圖的示範性實施例中,IC晶片66係為一影像感測器,其包括一基材68、一陣列的像素感測器70、像素感測器70上方之一色濾器及微透鏡陣列72、及被電性耦合至像素感測器70以從像素感測器供應輸出電信號之結合墊74。可在基材(例如聚合物片60)/覆蓋件(例如保護性層64)附接之後進行矽基材68的一選用性薄化,較佳留下具有至少50μm厚度之基材68。
以類似於上文對於經過處置器10所形成的電性互連描述之方式,在矽基材68中形成電性互連。確切來說,孔76形成於基材68的底表面內,直到其抵達且曝露結合墊74為止,如第15圖所示。孔76可利用一雷射、一電漿蝕刻製程、一噴砂製程、一機械銑製製程、或任何類似方法形成。較佳地,孔76藉由電漿蝕刻(譬如異向性、推拔狀、等向性、或其組合)形成,其容許具有不同形狀的孔輪廓。較佳地,孔76的輪廓為推拔狀,其中一較大維度係位於可供經過其製作孔76之表面上,且一較小維度位於結合墊74上。較佳地,結合墊74的最小孔直徑為約10μm,且壁的角度相對於
與可供經過其形成孔76之矽基材68表面呈正交的方向位於5°至35°之間。
利用一旋塗製程、一噴灑製程、一配送製程、一電化沉積製程、一層疊製程、或任何其他的類似方法形成一層的順應性介電材料78,該層順應性介電材料78係覆蓋住基材68的底表面且充填孔76,如第16圖所示。順應性介電材料78較佳係為一聚合物,諸如BCB(苯環丁烯)、銲罩、銲阻、BT環氧樹脂或環氧樹脂丙烯酸酯。孔80隨後形成經過介電材料78,如第16圖所示。可利用對於較大尺寸的孔80的一CO2雷射(譬如約70μm的斑點尺寸)、或對於較小尺寸的孔80(譬如小於50μm直徑)的一UV雷射(譬如在355nm波長之約20μm的斑點尺寸)來形成孔80。可使用小於140ns脈衝長度位於10及50kHz之間的雷射脈衝頻率。孔80的側壁隨後被金屬化(亦即塗覆有一金屬化層82),與結合墊74產生電性接觸。金屬化製程較佳開始係為用於移除孔80內部壁上髒污(由鑽過諸如環氧樹脂、聚醯亞胺、氰酸鹽酯樹脂等介電材料所造成)的任何樹脂之去污製程。該製程係涉及使樹脂髒污與γ丁內酯與水的一混合物作接觸以軟化樹脂髒污,接著以一鹼性過錳酸鹽溶液作處理以移除軟化的樹脂,並以一水性酸性中和劑作處理以中和並移除過錳酸鹽殘留物。在去污處理之後,初始傳導金屬化層82係由無電極銅鍍覆形成,接著係為一光微影術回蝕使得金屬化層以一段短距離沿著介電材料78延伸遠離孔80。藉由來自表面粗度的一錨固效應在經鍍覆介面獲得黏著。所產生的結構顯示於第16
圖。
一金屬層隨後形成在介電材料78上方(譬如藉由金屬濺鍍,接著是一可光成像性阻劑層之沉積)。然後進行一光微影術步驟(亦即,經過罩幕的UV曝光以及選擇性阻劑層移除),接著是藉由光阻移除所曝露的那些部分之選擇性金屬蝕刻,而留下與從孔80延伸的金屬化層82電性接觸之金屬結合墊84。此處亦可發生結合墊84的金屬鍍覆。一絕緣層86隨後形成於介電材料78及結合墊84上方,接著是一選擇性回蝕以曝露結合墊84。選擇性回蝕可藉由一光微影製程進行以選擇性移除結合墊84上方之層86的那些部分。BGA互連體88隨後利用一銲料合金的一絲網印刷製程、或藉由一球置放製程、或藉由一鍍覆製程而形成於結合墊84上。BGA(球柵陣列)互連體係為用於與對偶導體產生物理及電性接觸之圓弧形導體,通常藉由將金屬球銲接或部份地融化在結合墊上所形成。所產生的結構是第17圖所示的微電子裝置。
第二封裝體2隨後積造(亦即機械性附接或安裝)至第一封裝體1,如第18圖所示,其中第二封裝體2的BGA互連體88係與第一封裝體1的結合墊52接觸且產生電性連接。可利用習見的揀放或晶粒附接設備進行積造。較佳地,這係在一加熱環境中進行,故BGA互連體88係結合於封裝體1及2(且在其間產生一穩固電性連接)。所產生的結構是附接在一起的一對微電子裝置,在其背離彼此的各別表面(面向外的表面)上具有結合墊。微電子裝置的一者之結合墊係(經由延
伸經過第一微電子裝置之電性傳導元件以及延伸經過第二微電子裝置之電性傳導元件)耦合至另一微電子裝置的面向外表面上之結合墊,故另一微電子裝置的該面向外表面上之結合墊係提供來自兩微電子裝置的信號。
上述及圖示的IC封裝技術及其製造方法具有數項優點。第一,以矽為基礎的IC晶片26被容置在處置器10內,其提供IC晶片26的機械性及環境性保護。第二,利用一用於將IC晶片26固接在處置器10內的順應性介電材料(例如介電絕緣層28)係降低了會負面影響兩者之熱及機械應力。第三,利用一具有用於封裝IC晶片26的扇出及扇入墊(其可在插入處置器10之前被分離地測試及驗證)之處置器結構係增強了可靠度與良率。第四,用於兩晶片的電性連接係設置於處置器10的一共同表面上,以供有效率的信號耦合及連接。第五,利用用於層32的一晶圓層級介電疊層係提供橫越一很寬頻率範圍的很低阻抗。此阻抗可比既有的噴灑及旋塗介電質更低達到一個數量級或以上。這些超薄介電疊層亦提供將功率及接地平面上的雜訊予以減振之優點,並對於達成未來高速數位設計中的可接受電性效能而言很重要。
經過孔18形成之貫通聚合物互連體亦具有數項優點。第一,這些互連體係為傳導元件,其從封裝體2可靠地重新繞佈電信號、經過處置器10、來到含有用於IC晶片26的電接觸部之處置器10的同側。第二,藉由將通孔14的壁形成有一傾斜,其降低了可由於90度角所導致之晶系上潛在具
損害性的誘發應力。第三,孔14的傾斜狀側壁亦代表不具有會導致介電材料16形成間隙之負角區域。第四,藉由先形成絕緣材料(例如該介電材料16)、然後在其上形成金屬化層20,可避免金屬擴散至處置器10的晶系結構內。第五,利用一鍍覆製程形成金屬層20係優於諸如濺鍍沉積等其他金屬化技術,原因在於鍍覆製程較不易損害絕緣材料(例如該介電材料16)。第六,利用一順應性絕緣材料(例如該介電材料16)來形成孔18的側壁係較為可靠。最後,利用雷射鑽製經過聚合物、去污、及金屬鍍覆來生成貫通聚合物互連體係比利用半導體濺鍍及金屬沉積工具更為便宜。
經過孔80形成的貫通聚合物互連體係提供與上述經過孔18形成者相同之優點(亦即,自結合墊74繞佈電信號、經過基材68、以經由結合墊84電性耦合至結合墊52之傳導元件)。此外,在已知使用順應性材料(例如順應性介電材料16及78)下,經過孔18及80形成的貫通聚合物互連體係吸收原本會損害周遭結構之應力。藉由使孔80中的互連體終止於結合墊74、藉由在結合墊80上設有一順應性基材、且藉由對於絕緣層86使用一順應性材料,來吸收額外的應力。
上述封裝組態係可理想使用於並IC晶片66身為影像感測器且IC晶片26身為用於處理來自影像感測器的信號之處理器並就此脈絡作描述(但不在此限)。影像感測器是一互補性金屬氧化物半導體(CMOS)裝置,其包括一含有一陣列的像素感測器之積體電路,各像素含有一光偵測器且較佳含有其自身的主動放大器。各像素感測器將光能轉換成一電
壓信號。晶片上可包括有額外電路以將電壓轉換成數位資料。影像處理晶片係包含硬體處理器及軟體演算法的一組合。影像處理器從個別像素感測器收集亮度及色度資訊並利用其運算/內插對於各像素的正確色彩及明度值。影像處理器評估一給定像素的色彩及明度資料,將其與來自鄰近像素的資料作比較且然後利用一去馬賽克演算法從不完全的色彩樣本重新建構一全色彩影像,並產生對於該像素的一適當明度值。影像處理器亦存取整體圖像並矯正銳利度且降低影像的雜訊。
影像感測器的演進係導致影像感測器中益加更高的像素數,以及諸如自動聚焦、紅眼消除、臉部追蹤等額外的攝影機功能,其需要可以更高速運作之更強力的影像感測器處理器。攝影者不想在可繼續進行拍攝之前等待攝影機的影像處理器完成其工作一其甚至不想注意到攝影機內部正在進行一些處理。因此,影像感測器必須被最適化以在相同或甚至更短時間期間中應付更多的資料。
請瞭解本發明不限於上述及顯示的實施例,而是涵蓋落在申請專利範圍的範疇內之任一及全部變異。譬如,本文對於本發明的指涉並無意限制任一申請專利範圍或申請專利範圍條件的範疇,而是僅指涉可被申請專利範圍的一或多者所涵蓋的一或多個特徵構造。上述材料、製程及數值範例僅為範例,且不應視為限制申請專利範圍。並且,如同申請專利範圍及說明書所得知,不需以所顯示或主張的確切次序進行全部的方法步驟,而是以可容許妥當形成
本發明的IC封裝之任何次序分離地或同時地進行即可。單層的材料可形成為多層的如是或類似材料,且反之亦然。雖然就IC晶片26身為一影像感測器處理器且IC晶片66身為一影像感測器之脈絡來揭露創新的封裝組態,本發明不限於這些IC晶片。
應注意如本文的“上方”及“上”用語皆包含性包括“直接位於~上”(不具有配置其間之中間材料、元件或空間)以及“間接位於~上”(具有配置其間之中間材料、元件或空間)。同理,“相鄰”用語係包括“直接相鄰”(不具有配置其間之中間材料、元件或空間)以及“間接相鄰”(具有配置其間之中間材料、元件或空間),“安裝至”係包括“直接安裝至”(不具有配置其間之中間材料、元件或空間)以及“間接安裝至”(具有配置其間之中間材料、元件或空間),且“電性耦合”係包括“直接電性耦合至”(不具有用於將元件電性連接在一起之位於其間的中間材料或元件)以及“間接電性耦合至”(具有用於將元件電性連接在一起之位於其間的中間材料或元件)。譬如,形成一元件“於一基材上方”可包括直接形成該元件於基材上方而其間不具有中間材料/元件、以及間接形成該元件於基材上方而其間具有一或多個中間材料/元件。
1‧‧‧第一封裝體
2‧‧‧第二封裝體
10‧‧‧處置器、晶系處置器
12‧‧‧腔穴
14、18‧‧‧孔、通孔
16、78‧‧‧順應性介電材料、介電材料
20、82‧‧‧金屬化層
22‧‧‧介電層
24‧‧‧金屬墊
26‧‧‧IC晶片
27‧‧‧積體電路
28‧‧‧介電絕緣層、絕緣層
30、74、84‧‧‧結合墊
32‧‧‧包封絕緣層、絕緣層、層
38‧‧‧包封絕緣層、層
34、52‧‧‧金屬扇出及扇入結合墊、結合墊
36‧‧‧互連體結合墊、結合墊
40、88‧‧‧BGA互連體
54、86‧‧‧絕緣層、層
60‧‧‧聚合物片
62、76、80‧‧‧孔
64‧‧‧透明保護性層
66‧‧‧第二IC晶片、IC晶片
68‧‧‧基材、矽基材
70‧‧‧像素感測器
72‧‧‧色濾器及微透鏡陣列
第1至10圖是一半導體封裝結構之橫剖側視圖,其依順序顯示在形成第一封裝結構中之封裝結構的處理中之步驟;第11至17圖是一半導體封裝結構之橫剖側視圖,其依
順序顯示在形成第二封裝結構中之封裝結構的處理中之步驟;第18圖是被安裝至第一封裝結構之第二封裝結構的橫剖側視圖。
1‧‧‧第一封裝體
10‧‧‧處置器、晶系處置器
16‧‧‧順應性介電材料、介電材料
18‧‧‧孔、通孔
20‧‧‧金屬化層
22‧‧‧介電層
24‧‧‧金屬墊
26‧‧‧IC晶片
27‧‧‧積體電路
28‧‧‧介電絕緣層、絕緣層
30‧‧‧結合墊
32‧‧‧包封絕緣層、絕緣層、層
38‧‧‧包封絕緣層、層
34、52‧‧‧金屬扇出及扇入結合墊、結合墊
36‧‧‧互連體結合墊、結合墊
40‧‧‧BGA互連體
54‧‧‧絕緣層、層
Claims (26)
- 一種微電子總成,包含:一第一微電子元件,其包含:一矽基材,其具有第一及第二相對表面,整體性地形成於該第一表面之一半導體裝置,及位於該第一表面的傳導墊,其電性耦合至該半導體裝置;一第二微電子元件,其包含:一矽處置器,其具有第一及第二相對表面,形成於該處置器的該第一表面中之一腔穴,設置於該腔穴中之一第二半導體裝置,及位於該處置器第一表面的傳導墊,其電性耦合至該第二半導體裝置;該等第一及第二微電子元件係被積造至彼此,使得該等第二表面面對彼此;該第一微電子元件包括傳導元件,各個傳導元件從該等傳導墊的一者延伸且經過該基材至該第一微電子元件的第二表面;該第二微電子元件係包括傳導元件,各個傳導元件延伸於該處置器的第一及第二表面之間;及該第一微電子元件之該等傳導元件的各者係電性耦合至該第二微電子元件之傳導元件的至少一者。
- 如申請專利範圍第1項之微電子總成,其中該第一微電 子元件之該等傳導元件的各者係包含:一形成於該基材中之孔,其具有從該基材的第二表面延伸至該第一微電子元件的傳導墊的一者之一側壁;一順應性介電材料,其沿著該側壁配置;及一傳導材料,其沿著該順應性介電材料配置且延伸於該基材的第二表面與該第一微電子元件的一傳導墊之間。
- 如申請專利範圍第2項之微電子總成,其中該順應性介電材料包括一聚合物。
- 如申請專利範圍第2項之微電子總成,其中針對於該第一微電子元件之傳導元件的各者,該孔係為推拔狀使得該孔在該一傳導墊比起在該基材的第二表面具有一更小的橫剖面維度。
- 如申請專利範圍第2項之微電子總成,其中針對於該第一微電子元件之傳導元件的各者,該側壁係延伸於相對於與該基材的第一及第二表面正交的一方向呈5°至35°之間的一方向。
- 如申請專利範圍第1項之微電子總成,其中該第二微電子元件的半導體裝置係形成在一配置於該腔穴中的基材上。
- 如申請專利範圍第1項之微電子總成,其中該第二微電子元件之傳導元件的各者係包含:一形成於該處置器中之孔,其具有延伸於該處置器的第一及第二表面之間的一側壁; 一順應性介電材料,其沿著該側壁配置;及一傳導材料,其沿著該順應性介電材料配置且延伸於該處置器的第一及第二表面之間。
- 如申請專利範圍第7項之微電子總成,其中該順應性介電材料包括一聚合物。
- 如申請專利範圍第7項之微電子總成,其中針對於該第二微電子元件之傳導元件的各者,該孔係為推拔狀使得該孔在該第二表面比起在該處置器的第一表面具有一更小的橫剖面維度。
- 如申請專利範圍第7項之微電子總成,其中針對於該第二微電子元件之傳導元件的各者,該側壁係延伸於相對於與該處置器的第一及第二表面正交的一方向呈5°至35°之間的一方向。
- 如申請專利範圍第1項之微電子總成,其中該第一微電子總成的半導體裝置係為一影像感測器,且該第二微電子總成的半導體裝置係為一用於處理來自該影像感測器的信號之處理器。
- 如申請專利範圍第11項之微電子總成,其中該影像感測器係包含一陣列的像素感測器,該陣列的像素感測器各包括一用於將光能轉換成一電壓信號之光偵測器,且其中該處理器係組構為接收該等電壓信號並對於來自該等像素感測器之該等電壓信號的各者運算或內插色彩及明度值。
- 如申請專利範圍第1項之微電子總成,其中該第一及第 二微電子元件的積造係包含複數個BGA互連體,該等複數個BGA互連體各電性耦合於該等第一微電子元件之傳導墊的一者與該等第二微電子元件之傳導墊的一者之間。
- 一種形成一微電子總成之方法,包含下列步驟:提供一第一微電子元件,其包含:一矽基材,其具有第一及第二相對表面,整體性地形成於該第一表面之一半導體裝置,及位於該第一表面的傳導墊,其電性耦合至該半導體裝置;提供一第二微電子元件,其包含:一矽處置器,其具有第一及第二相對表面,一第二半導體裝置,及位於該處置器第一表面的傳導墊,其電性耦合至該第二半導體裝置;於該處置器的該第一表面中形成一腔穴;於該腔穴中設置該第二半導體裝置;形成傳導元件,該等傳導元件各從該等傳導墊的一者延伸且經過該基材至該第一微電子元件的第二表面;形成傳導元件,該等傳導元件各延伸於該處置器的第一及第二表面之間;將該第一及第二微電子元件積造至彼此,使得該等第二表面面對彼此,且使得該第一微電子元件之傳導元 件的各者電性耦合至該第二微電子元件之傳導元件的至少一者。
- 如申請專利範圍第14項之方法,其中形成該第一微電子元件之該等傳導元件的各者之步驟係包含:形成一孔於該基材中,其具有從該基材的第二表面延伸至該第一微電子元件的傳導墊的一者之一側壁;形成一沿著該側壁配置之順應性介電材料;及形成一傳導材料,其沿著該順應性介電材料配置且延伸於該基材的第二表面與該第一微電子元件的一傳導墊之間。
- 如申請專利範圍第15項之方法,其中該順應性介電材料包括一聚合物。
- 如申請專利範圍第15項之方法,其中針對於該第一微電子元件之傳導元件的各者,該孔係為推拔狀使得該孔在該一傳導墊比起在該基材的第二表面具有一更小的橫剖面維度。
- 如申請專利範圍第15項之方法,其中針對於該第一微電子元件之傳導元件的各者,該側壁係延伸於相對於與該基材的第一及第二表面正交的一方向呈5°至35°之間的一方向。
- 如申請專利範圍第15項之方法,其中該第二微電子元件的半導體裝置係形成在一配置於該腔穴中的基材上。
- 如申請專利範圍第14項之方法,其中形成該第二微電子元件之傳導元件的各者之步驟係包含: 形成一孔於該處置器中,其具有延伸於該處置器的第一及第二表面之間的一側壁;形成一沿著該側壁配置之順應性介電材料;及形成一傳導材料,其沿著該順應性介電材料配置且延伸於該處置器的第一及第二表面之間。
- 如申請專利範圍第20項之方法,其中該順應性介電材料包括一聚合物。
- 如申請專利範圍第20項之方法,其中針對於該第二微電子元件之傳導元件的各者,該孔係為推拔狀使得該孔在該第二表面比起在該處置器的第一表面具有一更小的橫剖面維度。
- 如申請專利範圍第20項之方法,其中針對於該第二微電子元件之傳導元件的各者,該側壁係延伸於相對於與該處置器的第一及第二表面正交的一方向呈5°至35°之間的一方向。
- 如申請專利範圍第14項之方法,其中該第一微電子總成的半導體裝置係為一影像感測器,且該第二微電子總成的半導體裝置係為一用於處理來自該影像感測器的信號之處理器。
- 如申請專利範圍第24項之方法,其中該影像感測器係包含一陣列的像素感測器,該陣列的像素感測器各包括一用於將光能轉換成一電壓信號之光偵測器,且其中該處理器係組構為接收該等電壓信號並對於來自該等像素感測器之該等電壓信號的各者運算或內插色彩及明度 值。
- 如申請專利範圍第14項之方法,其中該積造步驟係包含:形成複數個BGA互連體,該等複數個BGA互連體各電性耦合於該等第一微電子元件之傳導墊的一者與該等第二微電子元件之傳導墊的一者之間。
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