CN1244728A - Soft and flexible surface layer of inverted packed sheet electronic packing piece - Google Patents
Soft and flexible surface layer of inverted packed sheet electronic packing piece Download PDFInfo
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- CN1244728A CN1244728A CN99104390A CN99104390A CN1244728A CN 1244728 A CN1244728 A CN 1244728A CN 99104390 A CN99104390 A CN 99104390A CN 99104390 A CN99104390 A CN 99104390A CN 1244728 A CN1244728 A CN 1244728A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Flip-chip electronic packages are provided with a compliant surface layer, normally positioned between an underfill layer and a substrate such as a chip carrier or a printed circuit board or card, which reduces stress and strain resulting from differences in coefficients of thermal expansion between the chip and substrate. The compliant layer, which should have a storage modulus of less than 1/2 the modulus of the substrate, preferably between about 50,000 psi and about 20,000 psi, may comprise rubbery materials such as silicone, virco-plastic polymers such as polytetrafluoroethylene or interpenetrating polymer networks (IPNs). Photosensitive IPNs used for solder marks are preferred.
Description
The present invention relates to electronic packing piece, relate to the method and apparatus that improves the reliability of flip-chip connection by means of the thermal dilation difference phase coadaptation of the substrate that makes chip and installation chip more precisely.
Integrated circuit (IC) chip or module utilization are commonly referred to C4 (controlled avalanche chip connects) or the flip-chip technique for fixing is connected in chip carrier, are directly connected in sometimes on PC plate or the card.Little solder bump or ball are produced on the active surface of chip.Then with chip reversing (therefore being called " flip-chip ") and place on carrier, plate or other substrate that will be fixed thereon.Each element is heated, and scolder is refluxed in controlled avalanche process, thereby realizes being electrically connected between chip and the substrate.This technology makes it become one of industrial standard aspect connection compactness, electrical property and the cost many advantages being arranged all.But also there are some shortcomings, hindered it to use widely.
One more significant disadvantages from the difference between chip and the substrate thermal coefficient of expansion (CTE).Common chip material such as silicon, germanium and GaAs has usually and is about 3-6ppm/ ℃ CTE.The organic chip carrier of chip and the organic printed circuit board (PCB) that is generally the compound of organic dielectric medium and metallic circuit are installed, are had mostly and be about 12-20ppm/ ℃ CTE.When these elements were heated and cool off, substrate expanded than chip and shrinks much bigger.Be connected with substrate for simple chip, the strain of expanding from difference is mainly absorbed by the scolder of softness.Along with thermal cycle (this is inevitable to many electronic components) repeatedly, scolder connects inefficacy probably.
The conventional method of head it off is connected with scolder with CTE and is complementary or approaching (being about 22-28ppm/ ℃ usually) dielectric medium underfill comes to connect around scolder.Typical underfill is an epoxy radicals acid anhydride system.They are filled to obtain desirable CTE by the superfine granule high concentration of the material of silicon dioxide and so on usually.This filler also makes bottom filler have common high modulus greater than 2GPa or 300ksi (term used herein " modulus " expression stores modulus).The lower curtate filler has born the caused most of load of the different expansions with substrate of chip, thereby has reduced the strain in the scolder connection.But owing to limited different expansion between chip and the substrate, more intense coupling is just tended to make chip and carrier the two is all crooked between chip and the carrier.This has increased the load that acts on perpendicular to the substrate surface that carrier is installed.For example, when packaging part cools off after being fixed on the printed circuit board (PCB) that has the array of solder balls on the BGA usually at carrier or blocking, chip and carrier tend to upwards arch upward at the middle part, and this produces tension force on the ball of the centre of array between carrier and printed circuit board (PCB) or the card.This can cause the early failure of BGA.
In order to alleviate these problems, carried out various trials, be included in ribs with desirable CTE and submissive material layer in organic printed circuit board (PCB) of multilayer or the card.But the ribs costliness, and the compliant layers in the printed circuit board (PCB) causes that at through hole (PTH) place of wearing of plating stress is concentrated, forms shear deformation.So adapt to different thermal expansion between chip and the organic substrate of the circuitization such as chip carrier and printed circuit board (PCB) with regard to the reliable and inexpensive method of needs.
Packaging part of the present invention and method regulate chip with the CTE difference between the organic dielectric medium carrier, printed circuit board (PCB) or other substrates that place the submissive material layer installation chip between chip and the substrate.Chip is connected with scolder between the substrate and extends through this compliant layers, and this compliant layers is used with conventional bottom filler usually.Compliant layers is between bottom filler and substrate, and that its modulus should be less than the bottom filler modulus is only about half of.The modulus of generally wishing submissive material is less than about 100000psi, and it is better that modulus is approximately the material of 20000-50000psi.
In the thermal cycle process of chip and substrate, a side of compliant layers is consistent with the motion of bottom filler, and its opposite side is consistent with the motion of substrate.Like this, compliant layers has just reduced the coupling between chip and the substrate, thereby has reduced their bending.Various submissive dielectric mediums all can be used as compliant layers, comprise the visco-plasticity polymer of the elastomeric material of silicone and so on and polytetrafluoroethylene and so on.Photosensitive interpenetrating polymer networks as the mask of finishing the scolder connection is then better.
From following description, other advantages of the present invention will be more obvious.
Fig. 1 and 2 is the constructed profile of prior art electronic packing piece.
Fig. 3 is the constructed profile that embodies electronic packing piece of the present invention.
Fig. 4 test data illustrates the relation of the curvature of standard packaging part and the packaging part with compliant layers of the present invention to temperature.
Fig. 1 shows and generally is shown 10 conventional electrical packaging part, and it has a bare chip 12 that is connected in circuit carrier 22 with the C4 method of attachment.As C4 technology often do, solder bump is that solder ball 16 is fixed in the contact 14 on integrated circuit (IC) chip or the module 12, chip makes contact 14 be in the top the other way around.Then with the chip back-off in shown in the position, and make solder ball 16 in alignment with the contact on the circuit carrier 22 24.Again this packaging part is heated with Reflow Soldering pellet 16, connect thereby between chip 12 and carrier 22, finish C4.Custom circuit (not shown) in the carrier is connected to second set of contact 26 on the carrier base with the contact on the carrier top 24.The second big slightly assembly welding pellet 28 of solder ball 16 than chip 10 being fixed in carrier is fixed in the contact 26 of carrier below.Being commonly referred to ball grid array is this array of solder balls 28 of BGA, with contact 26 contacts 34 that are connected on printed circuit board (PCB), card or other substrates 32.Can select the scolder in the BGA ball 28 so that melt under the temperature of the scolder in being lower than C4 solder ball 16, make chip can be fixed in substrate 32 and do not influence C4 to be connected with carrier.
The thermal coefficient of expansion of the conventional chip material of silicon, germanium and GaAs and so on is about 3-6ppm/ ℃.They are fixed in other compound substrate of organic dielectric medium manufacturing of carrier, printed circuit board (PCB) and the epoxy resin of filling with glass, polyimides, liquid crystal polymer, filling PTFE and so on usually.By circuit carrier, printed circuit board (PCB) and other substrates that these organic dielectric mediums are made, its CTE generally is about 12-20ppm/ ℃.Because the CTE of the organic dielectric medium of circuitization more has many advantages (comprising cost, BGA life-span and dielectric constant) near other material (for example pottery) of chip, so although organic dielectric medium has this CTE mismatch, still be used in many application.But use the material of this CTE mismatch not go wrong.When packaging part 10 is heated or cooled, the lateral expansion of carrier 22 or contraction obvious lateral expansion or contraction greater than chip 12.This produces shear strain on C4 solder ball 16.Many electronic components routine in its general operation stands thermal cycle, and these thermal cycles are sometimes owing to environmental condition worsens.Thermal cycle more than 100 ℃ is quite general.Can be under extreme operation or environmental condition above 125 ℃.The stress/strain that these circulations are added in the C4 connection is these main causes that connect early failure.
Fig. 2 shows and has introduced another packaging part 40 that solves the conventional method of CTE mismatch problems.Except packaging part 40 the bottom filler 48 that has between chip 12 and the carrier 22 around the C4 solder ball, the various piece of packaging part 40 is identical with packaging part 10 basically.Can after being fixed in substrate, be dispersed in usually around the chip edge by any bottom filler of making 48 for this reason and in many commercially available material of design, because capillarity enters space and the curing of C4 between connecting.Bottom filler also can be added on chip or carrier, and solidifies simultaneously with the C4 backflow.The bottom filler that solidifies bears chip 12 and the major part load that carrier 22 expands and difference in shrinkage is produced, and this has reduced the strain in the C4 connection 16 significantly.
As mentioned above, underfill generally contains the superfine little particle of material of the silicon dioxide and so on of remarkable quantity.This particle is added in the material, makes the CTE of bottom filler 48 be substantially equal to the CTE (generally being about 22ppm/ ℃) of solder ball 16.These thermal coefficient of expansions must mate so that prevent that bottom filler is alternately flexible also along compressing C4 solder ball (this also can produce early failure) perpendicular to the chip surface direction.But this particle additive makes the modulus height of underfill, is 300ksi greater than 2Gpa usually.When the packaging part of type shown in Figure 2 was cooled after bottom filler solidifies, CTE difference between chip 14 and the carrier 22 and close coupling tended to make chip and carrier all crooked.This may make silicon break.When cooling off after the BGA connection of finishing between carrier 22 and the substrate 22 28, the bending of chip and carrier applies tension force on the central authorities of the ball grid array between carrier and substrate solder ball 28.Thermal cycle subsequently makes these solder ball pressurizeds, and can cause early failure.Like this, the solution that neither be satisfied with fully of bottom packed layer itself.
Fig. 3 shows and embodies electronic packing piece 60 of the present invention, and it has reduced the bending that CTE difference causes or the association danger of warpage and early stage chip rupture or bga chip fragmentation significantly.Packaging part 60 comprises the compliant layers 68 between bottom filler 48 and the carrier 22, and it is consistent with the motion of bottom filler 48 in a side, and consistent with the motion of carrier 22 at opposite side.In the packaging part that fill bottom shown in Figure 3, what the modulus of compliant layers 68 should be less than the modulus of filler 48 is only about half of.Usually, modulus is suitable less than the about material of 100000psi, and that modulus is approximately the material of 50000-20000psi is better.Suitable material comprises the viscoplastic material of the elastomeric material of photoimaging interpenetrating polymer networks, silicone and so on and polytetrafluoroethylene and so on.Photoimaging interpenetrating polymer networks (IPN) such as the people's such as Day that classify reference herein as United States Patent (USP) 5439779 disclosed cationic polymerization epoxy resin-matrix resin systems is good especially.These IPN can be used to make solder mask, and the C4 ease of connection between chip and the carrier is realized.Their physical property also makes it very desirable.
The surface of the carrier 22 that best submissive material is used to solidify and handled contacts 24 window 66 figures so that provide corresponding on C4 solder ball on the chip 12 and the carrier 22.The chip that will have prefabricated solder ball 16 then places on the compliant layers, and the heating packaging part is with softening solder ball, make scolder flow through window 66 in the compliant layers, and finish with carrier on being connected of contact 24, usually after chip is fixed in carrier, make the space between compliant layers and the chip be full of conventional underfill.
Finite element analysis and test data show, the optimum thickness range of compliant layers be between chip and the carrier space 1/4th to 1/2nd.Crooked for reducing, the thinner layer layer interior not as optimum range is effective like that, is difficult to fill the space that stays with bottom filler and thicker layer is feasible.
As seen from Figure 4 owing to use these materials to the improvement of bending, this illustrates conventional chip carrier (curve A) and has the test bending data (obtaining with More's interferometric method) of the carrier (curve B) of compliant layers of the present invention.Two packaging parts have been made with the same silicon mask model that has the array of 700 solder balls altogether.Chip is fixed on CTE and is about the epoxy resin laminate (being made by identical materials) that glass that 18ppm/ ℃ and modulus be about 18GPa is filled.Thickness be about 2 mils by 200 ℃ the time modulus be about the compliant layers that the polyol resin of 0.3GPa and photoimaging interpenetrating polymer networks that brominated epoxy resin is made are made, be added on the surface of second carrier and processed, so that form corresponding to the window that contacts on the solder ball in the array on the chip and the carrier surface.Solder ball is connected to contact on the carrier by the window in the compliant layers, stays the space of about 4 mils between chip and compliant layers.In not having first carrier of compliant layers, the space between chip and the carrier is about 6 mils.Open space around C4 connects in each packaging part at room temperature is about commercially available underfill Dexter Hysol 4511 fillings of 11GPa with modulus.
Fig. 4 illustrates, and the bending curvature that is proportional to the bending stress in the packaging part is the linear function of temperature.Bending curvature is low more, and bending stress is just more little.Temperature when packaging part flattens (bending curvature be zero) will be because chip will begin locked or will be coupled in the laminated chips carrier when being lower than this temperature, so be defined as " unstressed temperature " or " chip lock fixed temperature " or " chip coupling temperature ".When being higher than this temperature, chip will with the decoupling of laminated chips carrier, that is it is smooth that chip almost keeps, and bending curvature remains zero basically.
As from scheming as seen, the decoupling layer in second packaging part has reduced the intersection point of " chip coupling temperature ", 1 bending curvature point or curve and temperature axis effectively.At this moment, " chip coupling temperature " is reduced to about 110 ℃ of packaging part with decoupling layer from 140 ℃ of standard packaging part.Because the linear relationship between bending curvature and the temperature, the whole buckling curve with packaging part of decoupling layer offsets downward.So, in packaging part, in the whole temperature range that is lower than " chip coupling temperature " point, obtained lower bending curvature thereby also be lower bending stress with decoupling layer.
As mentioned above, various other submissive materials can both be used as compliant layers 68.Such as the silk screen printing on the low-down material of Tg other prepares the method for solder mask, also can be used for can not photoimaging material.As the one skilled in the art from foregoing description intelligible, the invention provides a kind of flip-chip in the packaging part of the organic dielectric medium substrate of circuitization, reduce crooked effectively, practicality and the worthwhile method of cost.Obtain these improvement and do not produced the problem that other perplexs art methods.Certainly, the one skilled in the art can also understand, and within the scope of the invention, can make many corrections to above-mentioned by material defined by the following claims, structure and method.
Claims (14)
1. semiconductor package part, it comprises:
Integrated circuit (IC) chip;
Thermal coefficient of expansion is apparently higher than the organic substrate of the circuitization of described chip thermal coefficient of expansion;
Scolder between described chip and described substrate connects;
Bottom packed layer around described scolder connection; And
Submissive dielectric material layer between described encapsulation agent and described circuit organic carrier, the modulus of described dielectric material is only about half of less than bottom packed layer modulus, and be used to a side on the bottom packed layer as one man move and as one man move with described organic substrate on the opposite side.
2. according to the packaging part of claim 1, submissive dielectric material wherein comprises the polymeric material of modulus less than about 100000psi.
3. according to the packaging part of claim 2, the modulus of wherein said polymeric material is about 50000psi-20000psi.
4. according to the packaging part of claim 3, wherein said polymeric material comprises interpenetrating polymer networks, elastomeric material or visco-plasticity polymer.
5. according to the packaging part of claim 1, submissive dielectric material wherein comprises interpenetrating polymer networks.
6. according to the packaging part of claim 5, at least a polymer is a Photoimageable in the wherein said network.
7. according to the packaging part of claim 1, compliant layers wherein comprises solder mask.
8. according to the packaging part of claim 7, solder mask wherein comprises the interpenetrating polymer networks of Photoimageable.
9. packaging part according to Claim 8, the interpenetrating polymer networks of wherein said Photoimageable comprises the epoxy system that contains polyol resin and brominated epoxy resin.
10. according to the packaging part of claim 9, wherein said polymer network begins to be converted to rubbery state under about 95-105 ℃ temperature.
11. according to the packaging part of claim 1, wherein the thickness of the compliant layers of submissive material is about 1/4th to 1/2nd of distance between chip and the carrier.
12. an electronic equipment, it comprises:
Integrated circuit (IC) chip;
Have second set of contact having first set of contact on the first surface and facing on the second surface of described first surface, the contact in described second group is electrically connected on the organic dielectric medium chip carrier of circuitization of the contact in described first group;
Scolder between described chip and carrier connects;
Bottom packed layer around described scolder connection;
The compliant layers of making by interpenetrating polymer networks between described bottom packed layer and described chip carrier;
At least the organic substrate of circuitization that on a surface, has contact; And
Scolder between described second set of contact on the contact on the described substrate and the described carrier is connected array.
13. a method that is used for integrated circuit (IC) chip is connected to the organic dielectric medium chip carrier that has contact array at least one surface is characterized in that comprising the following step:
A solder element array outstanding from the active surface of described chip is provided;
The compliant layers that interpenetrating polymer networks is formed is applied to the described surface of described substrate, will described lip-deep contact covering;
In described compliant layers, make window so that can be near the contact on the described substrate;
Described integrated circuit (IC) chip is placed on the described compliant layers, described outstanding solder element is aimed at described window; And solder element heated, make scolder flow through described window, thereby finish the electrical connection between described chip and described the contact; And
The underfill layer that making is connected with described scolder between the chip around compliant layers.
14. the method for an assembling electronic element, it comprises:
Integrated circuit (IC) chip with solder element array outstanding from the active surface of described chip is provided;
Provide one to have second set of contact having first set of contact on the first surface and facing on the second surface of described first surface, the contact in described second group is electrically connected on the organic dielectric medium chip carrier of circuitization of the contact in described first group;
Between described carrier and described chip, make bottom packed layer around described outstanding solder element;
Described integrated circuit (IC) chip is placed on the described compliant layers, described outstanding solder element is aimed at described window; And solder element heated, make scolder flow through described window, thereby finish the electrical connection between described chip and described the contact;
On the described first surface of described chip carrier, make described contact the have corresponding on described outstanding solder element and the described carrier, and modulus is 100000psi or littler compliant layers;
Second level solder element array is bonded to the contact on the second surface of described carrier;
At least the organic printed circuit board (PCB) of circuitization or card or other substrate that have contact on a surface are provided;
Contacting on the described carrier that will have a described second level solder element and the described substrate contacts; And
Described second level solder element is refluxed, thereby finish from described integrated circuit (IC) chip by the electrical connection of described one-level solder element and described secondary solder element to described substrate.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US067708 | 1993-05-26 | ||
| US067,708 | 1998-04-28 | ||
| US09/067,708 US6191952B1 (en) | 1998-04-28 | 1998-04-28 | Compliant surface layer for flip-chip electronic packages and method for forming same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1244728A true CN1244728A (en) | 2000-02-16 |
| CN1168138C CN1168138C (en) | 2004-09-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991043901A Expired - Lifetime CN1168138C (en) | 1998-04-28 | 1999-03-26 | Soft and flexible surface layer of inverted packed sheet electronic packing piece |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6191952B1 (en) |
| CN (1) | CN1168138C (en) |
| MY (1) | MY138376A (en) |
| SG (1) | SG92634A1 (en) |
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| CN100437990C (en) * | 2005-03-17 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Strain silicon wafer with a crystal orientation (100) in flip chip bga package |
| CN1648626B (en) * | 2004-01-27 | 2011-01-26 | 梅特勒-托利多公开股份有限公司 | Moisture protection for an electromechanical transducer |
| CN102279942A (en) * | 2011-07-25 | 2011-12-14 | 上海祯显电子科技有限公司 | Novel intelligent card |
| CN101814444B (en) * | 2009-04-30 | 2012-01-25 | 中国空空导弹研究院 | Low-stress bottom filling method of laminating device |
| CN103946873A (en) * | 2011-08-26 | 2014-07-23 | 艾迪田集团股份有限公司 | Card lamination |
| TWI475649B (en) * | 2011-06-09 | 2015-03-01 | Optiz Inc | 3d integration microelectronic assembly for integrated circuit devices and method of making same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN101814444B (en) * | 2009-04-30 | 2012-01-25 | 中国空空导弹研究院 | Low-stress bottom filling method of laminating device |
| TWI475649B (en) * | 2011-06-09 | 2015-03-01 | Optiz Inc | 3d integration microelectronic assembly for integrated circuit devices and method of making same |
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| CN102279942A (en) * | 2011-07-25 | 2011-12-14 | 上海祯显电子科技有限公司 | Novel intelligent card |
| CN103946873A (en) * | 2011-08-26 | 2014-07-23 | 艾迪田集团股份有限公司 | Card lamination |
Also Published As
| Publication number | Publication date |
|---|---|
| US6191952B1 (en) | 2001-02-20 |
| SG92634A1 (en) | 2002-11-19 |
| MY138376A (en) | 2009-05-29 |
| CN1168138C (en) | 2004-09-22 |
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