CN113497033A - 半导体装置及其控制方法 - Google Patents

半导体装置及其控制方法 Download PDF

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CN113497033A
CN113497033A CN202010666280.5A CN202010666280A CN113497033A CN 113497033 A CN113497033 A CN 113497033A CN 202010666280 A CN202010666280 A CN 202010666280A CN 113497033 A CN113497033 A CN 113497033A
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semiconductor layer
electrode
semiconductor
type semiconductor
layer
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系数裕子
末代知子
岩鍜治阳子
罇贵子
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Abstract

实施方式提供一种能够降低恢复损耗的半导体装置及其控制方法。实施方式的半导体装置具备半导体部、设于所述半导体部的背面上的第一电极、设于所述半导体部的表面上的第二电极、以及设于所述半导体部与所述第二电极之间控制电极。所述控制电极配置在设于所述半导体部的沟槽的内部，通过第一绝缘膜与所述半导体部电绝缘。所述半导体部包括第一导电型的第一层、第二导电型的第二层、以及第二导电型的第三层。所述第一层在所述第一电极与所述第二电极之间延伸。所述第二层设于所述第一层与所述第二电极之间，并与所述第二电极连接。所述第三层设于所述第一层与所述第二电极之间，并与所述第二层及所述第一绝缘膜相接。

Description

半导体装置及其控制方法
相关申请
本申请享受以日本专利申请2020－49917号(申请日：2020年3月19日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及半导体装置及其控制方法。
背景技术
对于电力用半导体装置，要求降低开关损耗。例如，对于与IGBT(Insulated GateBiplar Transistor，绝缘栅双极型晶体管)一同构成电力转换电路的二极管，要求降低从接通状态移至断开状态过程中的恢复损耗。
发明内容
实施方式提供一种能够降低恢复损耗的半导体装置及其控制方法。
实施方式的半导体装置具备半导体部、设于所述半导体部的背面上的第一电极、设于所述半导体部的表面上的第二电极、以及设于所述半导体部与所述第二电极之间的控制电极。所述控制电极配置在设于所述半导体部的沟槽的内部，通过第一绝缘膜与所述半导体部电绝缘，通过第二绝缘膜与所述第二电极电绝缘。所述半导体部包括第一导电型的第一半导体层、第二导电型的第二半导体层、以及所述第二导电型的第三半导体层。所述第一半导体层在所述第一电极与所述第二电极之间延伸，所述控制电极从所述半导体部的所述表面侧延伸到所述第一半导体层中。所述第二半导体层设于所述第一半导体层与所述第二电极之间，并与所述第二电极连接。所述第三半导体层设于所述第一半导体层与所述第二电极之间，并与所述第二半导体层及所述第一绝缘膜相接。所述第三半导体层与所述第二电极电连接，并包含浓度比所述第二半导体层的第二导电型杂质的浓度高的第二导电型杂质。
附图说明
图1是示意地表示实施方式的半导体装置的立体图。
图2的(a)、(b)是表示实施方式的半导体装置的示意剖面图。
图3的(a)、(b)是表示实施方式的半导体装置的动作的示意剖面图。
图4的(a)、(b)是表示实施方式的变形例的半导体装置的示意剖面图。
图5的(a)、(b)是表示实施方式的另一变形例的半导体装置的示意图。
图6是示意地表示第二实施方式的半导体装置的立体图。
图7的(a)、(b)是表示第二实施方式的变形例的半导体装置的示意图。
具体实施方式
以下，参照附图对实施方式进行说明。对附图中的相同的部分标注相同的附图标记而适当省略其详细说明，对不同的部分进行说明。另外，附图是模式性的或概念性的，各部分的厚度与宽度的关系、部分间的大小的比率等并不一定与现实相同。另外，即使在表示相同的部分的情况下，也存在根据附图而彼此的尺寸、比率被不同地表示的情况。
而且，使用各图中所示的X轴、Y轴以及Z轴对各部分的配置以及构成进行说明。X轴、Y轴、Z轴相互正交，分别表示X方向、Y方向、Z方向。另外，有时将Z方向设为上方、将其相反方向设为下方而进行说明。
(第一实施方式)
图1是示意地表示实施方式的半导体装置1的立体图。半导体装置1例如为二极管，具有沟槽栅极构造。另外，图1所示的沟槽栅极构造是例示性的，并非限定于此。例如，也可以是将阳极电极与栅极电极电连接的构成。
半导体装置1具备半导体部10(参照图2的(a))和控制电极20。半导体部10包括n型半导体层11、p型半导体层13、以及p型半导体层15。半导体部10例如是硅。
控制电极20配置在设于半导体部10的栅极沟槽GT的内部。控制电极20从半导体部10的表面侧延伸到n型半导体层11中。控制电极20通过绝缘膜23与半导体部10电绝缘。控制电极20的上端例如被绝缘膜25覆盖。控制电极20例如是具有导电性的多晶硅。绝缘膜23以及绝缘膜25例如是硅氧化膜。
控制电极20设有多个。p型半导体层13在多个控制电极20中的相邻的两个控制电极20之间设于n型半导体层11之上。p型半导体层13通过向半导体部10的表面侧离子注入p型杂质例如硼(B)而形成。
p型半导体层15设于n型半导体层11之上，位于p型半导体层13与控制电极20之间。p型半导体层15与绝缘膜23相接。另外，p型半导体层15隔着绝缘膜23与控制电极20相对地设置。p型半导体层15包含浓度比p型半导体层13的p型杂质高的p型杂质。
p型半导体层15通过向栅极沟槽GT的内壁离子注入p型杂质、例如硼(B)并使其活化而形成。例如，通过控制相对于半导体部10的表面的入射角，能够向栅极沟槽GT的上部离子注入p型杂质。
如图1所示，p型半导体层13的下端例如在Z方向上位于与n型半导体层11与p型半导体层15的边界大致相同的水平。另外，p型半导体层13的下端例如也可以在Z方向上位于比n型半导体层11与p型半导体层15的边界靠下的水平。即，p型半导体层13隔着p型半导体层15与绝缘膜23相对地设置。p型半导体层15例如在从p型半导体层13朝向控制电极20的方向(X方向)上，具有比p型半导体层13的宽度窄的宽度。另外，p型半导体层15设置为，X方向的宽度壁沿着绝缘膜23的Z方向的长度窄。
而且，p型半导体层13的下端例如有时在Z方向上位于比n型半导体层11与p型半导体层15的边界靠上的水平。p型半导体层13例如除了位于n型半导体层11的附近的部分以外，隔着p型半导体层15与绝缘膜23相对地设置。
图2的(a)以及(b)是表示实施方式的半导体装置1的示意剖面图。
图2的(a)是表示与X－Z平面平行的截面的示意图。图2的(b)是沿着图2的(a)中所示的A－A线的剖面图。
如图2的(a)所示，半导体部10设于第一电极30与第二电极40之间。第一电极30例如是阴极电极，设于半导体部10的背面上。第二电极40例如是阳极电极，设于半导体部10的表面上。第一电极30以及第二电极40例如是含有钛(Ti)以及铝(Al)的金属层。
控制电极20通过栅极绝缘膜(绝缘膜23)与半导体部10电绝缘。另外，控制电极20通过绝缘膜25与第二电极40电绝缘。
第二电极40与p型半导体层13以及p型半导体层15连接。第二电极40与p型半导体层13例如肖特基连接。另外，第二电极40p与型半导体层15例如欧姆连接。
半导体部10还包括n型半导体层17。n型半导体层17设于n型半导体层11与第一电极30之间。第一电极30与n型半导体层17电连接。n型半导体层17包含浓度比n型半导体层11的n型杂质的浓度高的n型杂质。
如图2的(b)所示，控制电极20沿着半导体部10的表面10F，例如在Y方向上延伸，并与栅极布线50电连接。栅极布线50例如具有连接部50c。连接部50c在设于绝缘膜25的接触孔内延伸，并与控制电极20连接。栅极布线50例如与未图示的栅极焊盘连接。另外，控制电极20并非限定于该例，例如也可以是不设置栅极布线50以及栅极焊盘而与第二电极40(阳极电极)电连接的方式。
图3的(a)以及(b)是表示实施方式的半导体装置1的动作的示意剖面图。图3的(a)示出了第一电极30的电位比第二电极40的电位低的情况(接通状态)下的载流子(电子以及空穴)的流动。图3的(b)示出了第一电极30的电位被偏置为高于第二电极40的电位时(从接通状态向断开状态的恢复时)的载流子的流动。
如图3的(a)所示，从第一电极30经由n型半导体层17向n型半导体层11注入电子。对应于此，从第二电极40经由p型半导体层13以及p型半导体层15向n型半导体层11注入空穴。
在该例子中，由于在p型半导体层13与第二电极40的界面存在肖特基势垒，因此可抑制空穴从第二电极40向p型半导体层13的注入。因此，从第二电极40注入到p型半导体层15的空穴主要向n型半导体层11注入。
如此，从第二电极40向n型半导体层11注入的空穴的量减少，因此从第一电极30向n型半导体层11注入电子的量也减少。由此，能够抑制接通状态下的n型半导体层11中的第二电极40侧的阳极区域以及第一电极30侧的阴极区域中的载流子密度。
在图3的(b)所示的恢复时，对控制电极20与第二电极40之间施加负的控制电压、例如负15V。由此，在n型半导体层11与绝缘膜23之间感应出p型反转层PIV。
如图3的(b)所示，n型半导体层11中的电子经由n型半导体层17向第一电极30排出。另外，n型半导体层11中的空穴主要经由p型反转层PIV以及p型半导体层15向第二电极40排出。
在该例子中，通过感应p型反转层PIV，可形成从n型半导体层11到第二电极40的空穴的排出路径，能够促进空穴的排出。在半导体装置1中，在接通状态下，抑制n型半导体层11中的载流子密度，在恢复时，通过p型反转层PIV促进空穴的排出。由此，能够缩短恢复时间，降低恢复损耗。
而且，空穴的排出路径形成于n型半导体层11与绝缘膜23的界面附近。由此，例如能够将因控制电极20的下端附近的电场集中所引起的雪崩击穿现象而产生的空穴向第二电极40顺畅地排出。即，能够提高半导体装置1的破坏耐量，扩大恢复时的安全动作区域。
图4的(a)以及(b)是表示实施方式的变形例的半导体装置2a以及2b的示意剖面图。半导体装置2具有将IGBT与二极管一体化的构造。
如图4的(a)所示，半导体装置2a包括二极管区域和IGBT区域。半导体装置2具备设于二极管区域的控制电极20、设于IGBT区域的控制电极60、以及第三电极70。
控制电极20在半导体部10与第二电极40之间，配置在设于半导体部10的栅极沟槽GT1的内部。
控制电极60在半导体部10与第二电极40之间，配置在设于半导体部10的栅极沟槽GT2的内部。控制电极60通过绝缘膜63与半导体部10电绝缘。另外，控制电极60通过绝缘膜65与第二电极40电绝缘。
第三电极70设于IGBT区域的端部。第三电极70在半导体部10与第二电极40之间，配置在设于半导体部10的沟槽ET的内部。第三电极70通过绝缘膜73与半导体部10电绝缘。第三电极70与第二电极40电连接。
半导体部10在二极管区域中，包括n型半导体层11、p型半导体层13、p型半导体层15、以及n型半导体层17。p型半导体层13、p型半导体层15以及n型半导体层17与图1所示的半导体装置1同样地配置。
半导体部10在IGBT区域中，还包括p型半导体层31、p型半导体层43、n型半导体层45、以及p型半导体层47。
p型半导体层31设于n型半导体层11与第二电极40之间。p型半导体层31例如是p型集电层，与第一电极30电连接。
p型半导体层43设于n型半导体层11与第二电极40之间。p型半导体层43例如是p型基底层。
n型半导体层45选择性地设于p型半导体层43与第二电极40之间。n型半导体层45设于与绝缘膜63相接的位置。n型半导体层45包含浓度比n型半导体层11的n型杂质的浓度高的n型杂质。
p型半导体层47选择性地设于p型半导体层43与第二电极40之间。p型半导体层47包含浓度比p型半导体层43的p型杂质的浓度高的p型杂质。
第二电极40例如与n型半导体层45以及p型半导体层47相接，并且电连接。
半导体部10还具备p型半导体层71。p型半导体层71设于二极管区域与IGBT区域之间的中间区域。p半导体层71设于n型半导体层11与第二电极40之间。p型半导体层71位于处于二极管区域的端部的控制电极20与处于IGBT区域的端部的第三电极70之间。
图4的(b)所示的半导体装置2b还包括n型半导体层33。n型半导体层33设于n型半导体层11与p型半导体层31之间以及n型半导体层11与n型半导体层17之间。n型半导体层33例如是n型缓冲层，包含浓度比n型半导体层11的n型杂质的浓度高的n型杂质。另外，n型半导体层33例如包含浓度比n型半导体层17的n型杂质低的n型杂质。
半导体装置2a以及2b在第一电极30被偏置为比第二电极40的电位高的电位的状态下，作为IGBT而进行动作。另一方面，在第一电极30被偏置为比第二电极40的电位低的电位的状态下，作为所谓的回流二极管进行动作。
在半导体装置2a以及2b中，通过具有与第二电极40相接的p型半导体层13以及p型半导体层15，能够降低从二极管模式向IGBT模式的恢复过程中的开关损耗(即，恢复损耗)。另外，通过适当控制控制电极20，能够进一步降低恢复损耗，并且能够提高恢复过程中的破坏耐量。
图5的(a)以及(b)是表示实施方式的另一变形例的半导体装置3的示意图。图5的(a)是表示半导体装置3的立体图。图5的(b)是表示半导体装置3的与X－Z平面平行的截面的示意图。
如图5的(a)所示，在半导体装置3中，p型半导体层13以及p型半导体层15也设于相邻的控制电极20之间。另外，p型半导体层13以及p型半导体层15设于n型半导体层11上。p型半导体层13包括多个接触部13c。另外，p型半导体层15包括接触部15c。
p型半导体层13的接触部13c在控制电极20的延伸方向(例如Y方向)上并列。p型半导体层15的接触部15c设于相邻的接触部13c之间。
在图5的(a)中所示的由虚线包围的接触区域CR中，第二电极40与p型半导体层13以及p型半导体层15相接。即，第二电极40经由多个接触部13c与p型半导体层13连接，经由接触部15c与p型半导体层15连接。
如图5的(a)所示，从半导体部10的表面到p型半导体层13与接触部15c的边界的Z方向的深度比从半导体部10的表面到n型半导体层11与p型半导体层13的边界的Z方向的深度浅。
如图5的(b)所示，第二电极40经由延伸到设于绝缘膜25的接触孔中的连接部40c而与p型半导体层13以及p型半导体层15连接。
例如，在p型半导体层15的X方向的宽度较窄的情况下，难以将连接部40c与p型半导体层15连接。在该例子中，通过在p型半导体层15设置接触部15c，并将连接部40c与接触部15c连接，使p型半导体层15与第二电极40之间的电连接变得容易。
另外，实施方式并非限定于图5所示的接触区域CR，例如也可以以第二电极40也与p型半导体层15的位于接触部13c与绝缘膜23之间的部分相接的方式扩大接触区域CR的X方向的宽度。
(第二实施方式)
图6是示意地表示第二实施方式的半导体装置4的立体图。
如图6所示，在相邻的控制电极20之间，p型半导体层13设于n型半导体层11上。
p型半导体层15沿着绝缘膜23延伸，以与控制电极20的侧面以及底面对置的方式设置。p型半导体层15包括在p型半导体层13与绝缘膜23之间延伸的部分、以及在n型半导体层11与绝缘膜23之间延伸的部分。
p型半导体层15包含浓度比p型半导体层13的p型杂质的浓度高的p型杂质。第二电极40例如与p型半导体层15欧姆连接(参照图2的(a))。另外，第二电极40例如与p型半导体层13肖特基连接。
在该例中，通过抑制从第二电极40向p型半导体层13的空穴注入，也能够降低接通状态下的n型半导体层11中的载流子密度，缩短恢复时间。另外，在从接通状态向断开状态的恢复过程中，p型半导体层15成为空穴从n型半导体层11向第二电极40的排出路径。由此，能够进一步缩短恢复时间，降低开关损耗。
在该例子中，无需对控制电极20施加负的控制电压而感应p型反转层PIV(参照图3的(b))，能够简化对控制电极20供给控制电压的电路(未图示)的构成。另外，也可以将控制电极20电连接于第二电极40，使两者成为相同的电位。
图7的(a)以及(b)是表示第二实施方式的变形例的半导体装置5的示意图。图7的(a)是表示半导体装置5的立体图。图7的(b)是表示半导体装置5的与Y－Z平面平行的截面的示意图。
如图7的(a)所示，在相邻的控制电极20之间，p型半导体层13以及p型半导体层15设于n型半导体层11上。控制电极20通过绝缘膜23与半导体部10(参照图2的(a))电绝缘，p型半导体层15设于p型半导体层13与绝缘膜23之间。
半导体部10还包括p型半导体层19。控制电极20通过绝缘膜23与半导体部10电绝缘。p型半导体层19以隔着绝缘膜23而与控制电极20的下端对置的方式设置。p型半导体层19设于远离p型半导体层13以及p型半导体层15的位置。
如图7的(b)所示，控制电极20沿Y方向延伸，在其端部与栅极布线50电连接。p型半导体层19也沿Y方向延伸，隔着绝缘膜23与控制电极20对置。另外，控制电极20并非限定于该例，例如也可以是不设置栅极布线50而与第二电极40(阳极电极)电连接的方式。
p型半导体层19沿着控制电极20的一端，在Z方向上延伸，并与布线80电连接。布线80具有接触部80c，该接触部80c在设于绝缘膜25的接触孔内延伸，并与p型半导体层19相接。p型半导体层19可以是浮动电位，但也可以经由布线80以及电阻Rc与第二电极40电连接。
在该例子中，在恢复过程中，对控制电极20与第二电极40之间施加负的控制电压。在n型半导体层11与绝缘膜23的界面感应出p型反转层(参照图3的(b))，p型半导体层15与p型半导体层19相连。由此，可形成空穴从n型半导体层11向第二电极40的排出路径，能够缩短恢复时间，并降低开关损耗(恢复损耗)。另外，因控制电极20的下端的电场集中所引起的雪崩击穿现象而产生的空穴被向第二电极40顺畅地排出，能够提高恢复过程中的破坏耐量。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些新的实施方式能够以其他各种方式来实施，在不脱离发明的主旨的范围内，能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围或主旨内，并且包含在权利要求书所记载的发明及其等效的范围内。

Claims (11)

1.一种半导体装置，具备：
半导体部；
第一电极，设于所述半导体部的背面上；
第二电极，设于所述半导体部的表面上；以及
控制电极，在所述半导体部与所述第二电极之间，配置在设于所述半导体部的沟槽的内部，通过第一绝缘膜与所述半导体部电绝缘，通过第二绝缘膜与所述第二电极电绝缘，
所述半导体部包括第一导电型的第一半导体层、第二导电型的第二半导体层、以及所述第二导电型的第三半导体层，
所述第一半导体层在所述第一电极与所述第二电极之间延伸，所述控制电极从所述半导体部的所述表面侧延伸到所述第一半导体层中，
所述第二半导体层设于所述第一半导体层与所述第二电极之间，并与所述第二电极连接，
所述第三半导体层设于所述第一半导体层与所述第二电极之间，与所述第二半导体层及所述第一绝缘膜相接，与所述第二电极电连接，包含浓度比所述第二半导体层的第二导电型杂质的浓度高的第二导电型杂质。
2.如权利要求1所述的半导体装置，
所述第二半导体层具有多个接触部，该多个接触部在沿着所述半导体部的所述表面的所述控制电极的延伸方向上并列，并与所述第二电极相接，
所述第三半导体层还包括与所述第二电极相接的接触部，
所述第三半导体层的接触部位于所述第二半导体层的多个接触部中的在所述延伸方向上相邻的两个接触部之间。
3.如权利要求1所述的半导体装置，
所述第二半导体层具有多个接触部，该多个接触部在沿着所述半导体部的所述表面的所述控制电极的延伸方向上并列，
所述第三半导体层还包括位于所述第二半导体层的多个接触部中的在所述延伸方向上相邻的两个接触部之间的部分，
所述第二电极与所述第二半导体层的所述多个接触部、所述第三半导体层的位于所述第二半导体层与所述第一绝缘膜之间的部分以及位于所述多个接触部之间的部分相接。
4.如权利要求2或3所述的半导体装置，
所述第二半导体层具有从所述第一电极朝向所述第二电极的第一方向上的第一厚度，
所述第三半导体层的接触部具有所述第一方向上的第二厚度，所述第一厚度比所述第二厚度厚。
5.如权利要求1所述的半导体装置，
所述第三半导体层包括沿着所述第一绝缘膜延伸且位于所述第一半导体层与所述第一绝缘膜之间的部分。
6.如权利要求1所述的半导体装置，
所述第三半导体层具有从所述第二半导体层朝向所述控制电极的方向上的第一层厚，
所述第二半导体层具有所述方向上的第二层厚，所述第一层厚比所述第二层厚薄。
7.如权利要求6所述的半导体装置，
所述第三半导体层在从所述第一电极朝向所述第二电极的方向上，具有沿着所述第一绝缘膜的第一长度，
所述第一长度比所述第一层厚长。
8.如权利要求1所述的半导体装置，
所述半导体部还包括所述第二导电型的第五半导体层，该第五半导体层设于所述第一半导体层与所述第一绝缘膜之间，沿着所述沟槽的底部延伸，并覆盖所述控制电极的端部。
9.如权利要求8所述的半导体装置，
所述第五半导体层经由电阻而与所述第二电极连接。
10.如权利要求1所述的半导体装置，
所述半导体部设于所述第一半导体层与所述第一电极之间，还包含浓度比所述第一半导体层的第一导电型杂质高的第一导电型杂质。
11.一种控制方法，其是权利要求1～10所述的半导体装置的控制方法，
在从以使所述第二电极的电位比所述第一电极的电位高的方式对所述第一电极与所述第二电极之间施加了电压的状态起，到使施加于所述第一电极与所述第二电极之间的电压反转以使所述第二电极的电位比所述第一电极的电位低的过程中，对所述第二电极与所述控制电极之间施加负电压。
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