CN1130762C - 减少寄生电阻和电容的场效应晶体管及其制造方法 - Google Patents
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Abstract
介绍了一种场效应晶体管及其形成方法,其中场效应晶体管引入与原有的浅结区自对准的T形栅和源和漏接触。本发明提供一种低阻栅电极和自对准的低阻源/漏接触,适于亚微米FET器件,并可以缩小到更小器件尺寸。
Description
发明领域
本发明涉及半导体,特别涉及具有亚微米栅长度的T形栅的自对准金属氧化物半导体(MOS)场效应晶体管(FET)。
技术背景
金属氧化物半导体(MOS)场效应晶体管(FET)的技术要求将栅长度缩小到0.25μm以下。形成栅的标准工艺是淀积多晶硅层,腐蚀该层限定出需要的栅长度,以及使用多晶硅做掩膜进行源/漏浅注入步骤。浅注入步骤之后形成氮化物侧壁间隔层,在源/漏区内注入深欧姆区,然后形成栅和源/漏注入的金属硅化物。由此随着栅长度减少,栅的电阻增加,是由于栅金属硅化物具有与下面的多晶硅栅相同的栅长度。由于RC时间延迟,栅电阻降低了器件的速度。此外,通过在氧化层中开出窗口并构图金属,可以形成比多晶硅栅更长的的金属栅。该工艺生产出了迄今为止最快的硅器件,但要求对初始的多晶硅栅进行进行高度严格的再对准,如果不成功,将导致栅与欧姆源/漏接触短路。因此,以上工艺不适合半导体的制造。
随着MOSFET中栅长度减少,欧姆源/漏接触必须在深度上密封,以保持栅长度与结深度的宽高比大于1。对浅结的该要求设置了硅量的上限,以确保形成低电阻率的金属硅化物接触。与较薄的硅化物源/漏接触相关的较高电阻会进一步降低FET的速度性能。
发明内容
根据本发明,介绍一种制造场效应晶体管的结构和工艺步骤,能够容易地将长度和宽度缩小到亚微米尺寸。该工艺依靠形成与原有结区自对准的升高的源/漏接触,然后形成栅介质和T形的自对准的金属或金属/多晶硅栅,以便减少寄生栅电阻。
本发明提供一种形成栅叠层的工艺,可以形成T形金属栅而没有严格的对准步骤,使栅电阻显著下降。
本发明还提供一种新工艺,能够形成T形栅,与现有的浅源/漏接触自对准,不需要任何严格的对准,例如对于0.05到0.2μm范围内的栅长度,本发明可以获得约0.2μm的对准精度。
本发明还提供一种新的替代工艺,其中栅由金属或金属/多晶硅的复分层形成,不需要任何硅化处理,产生极低的栅接触电阻。
本发明还提供一种工艺,其中在栅介质和栅导体之前淀积与原有浅结自对准的高电导率的源/漏接触。原有浅结区优选通过离子注入之后退火激活、通过原位掺杂的半导体的空间选择性外延生长、或通过如气体浸没激光掺杂(GILD)的工艺形成,在GILD工艺中在含掺杂剂原子的气体存在的条件下由高强度的激光照射结区。
本发明还提供几个密封升高的源/漏接触使它们与栅电隔离的方法。
根据本发明的上述思想,提供了一种形成场效应晶体管的方法,包括以下步骤:在半导体衬底的至少一个表面上形成至少一个牺牲层,构图所述至少一个牺牲层,形成由暴露的衬底区环绕的牺牲栅形结构,在所述牺牲栅形结构的相对侧上的所述暴露的衬底区内形成掺杂的半导体结区,在所述结区上选择性地形成源和漏接触金属化层,在所述源和漏接触金属化层上选择性地形成介质帽盖,除去所述牺牲栅形结构以露出所述衬底的下面的区域和所述源和漏接触金属化层的侧壁,淀积栅介质覆盖所述露出的衬底区域和所述源和漏接触金属化层的侧壁和上部,在所述栅介质的所有表面上形成导电层,所述导电层也填充了原先由牺牲栅形结构占据的体积,以及构图所述导电层限定栅介质。
在上述方法中,所述半导体材料为选自由GaAs、InGaAs、InP、Si、InGaAsP和SiGe组成的组中的一种单晶材料。
在上述方法中,所述形成至少一个牺牲层的步骤包括从SiO2、四乙氧基硅烷(TEOS)的衍生氧化物、可流动氧化物和Si3N4组成的组中选择一下层材料,从SiO2、四乙氧基硅烷(TEOS)的衍生氧化物、可流动氧化物、和Si3N4、TiN和硅组成的组中选择一上层材料的步骤。
在上述方法中,所述形成源和漏接触金属化层的步骤包括从Co、Ni、Pd、Pt、Rh、Ta、Ti、W、这些金属的导电硅化物、重掺杂的多晶硅、或重掺杂的多晶硅锗组成的组中选择至少一个接触金属化材料的步骤。
在上述方法中,在所述源和漏接触金属化上层形成介质帽盖层的所述步骤包括从平面化介质、介质氧化物和介质氮化物组成的组中选择一种介质材料的步骤。其中,所述介质帽盖层包括选自SiO2、四乙氧基硅烷(TEOS)的衍生氧化物、可流动氧化物和Si3N4组成的组中的一种平面化介质。所述介质帽盖层包括选自TiO2、Ta2O5和WO3组成的组中的一种介质氧化物。
在上述方法中,所述形成掺杂的半导体结的步骤包括离子注入和激活退火。
在上述方法中,所述形成掺杂的半导体结的步骤包括气体浸没激光掺杂。
在上述方法中,所述形成掺杂的半导体结的步骤包括在未由所述牺牲栅覆盖的所述暴露的衬底区上选择性外延生长掺杂的半导体结。
在上述方法中,在所述结区上形成源和漏接触金属化层的步骤包括覆盖(blanket)淀积所述接触金属化材料并平面化的步骤。优选地,通过化学机械抛光进行所述平面化。其中,还可以包括通过选择性腐蚀将源和漏接触金属化层的上表面开槽到低于牺牲栅形结构上表面下的水平的步骤。
在上述方法中,在所述结区上形成源和漏接触金属化层的所述步骤包括在所述结区上选择生长所述接触金属化材料的步骤。
在上述方法中,所述形成所述介质帽盖层的步骤包括覆盖淀积并平面化所述介质帽盖材料的步骤。
在上述方法中,所述形成所述介质帽盖层的步骤包括通过选自氧化和氮化组成的组中的一种工艺在接触金属化层上表面上生长所述帽盖层的步骤。所述氧化为热氧化或阳极氧化。
在上述方法中,还可以包括在牺牲栅形结构上形成介质侧壁间隔层的步骤,所述侧壁间隔层由与所述牺牲栅形结构的材料不同的材料形成。
在上述方法中,还可以包括通过自氧化和氮化组成的组中选择的一种工艺在所述源和漏接触金属化层的侧壁上生长介质侧壁间隔层的步骤。所述氧化为热氧化或阳极氧化。
在上述方法中,所述接触金属化层的厚度小于所述栅形结构的厚度,且所述介质帽盖层的上表面与所述牺牲栅形结构的上表面持平。
根据本发明的另一个方面,提供了一种场效应晶体管,包括:半导体衬底;两个隔开的掺杂的半导体区,形成源和漏结区,并限定出两者之间的沟道衬底区;所述结区上的第一导电层,所述第一导电层形成源和漏接触金属化层;所述接触金属化层的上表面上的第一介质层;所述沟道衬底区上的栅介质,在所述接触金属化层的侧壁和上表面上延伸;以及,具有T形截面的栅,包括所述栅介质上的第二导电层,该层在第一介质层和部分源和漏接触金属化层上延伸。
在所述场效应晶体管中,所述结构还包括置于栅介质和接触金属化层的侧壁之间的介质侧壁间隔层。
根据本发明的再一个方面,提供了一种形成场效应晶体管的方法,包括以下步骤:在单晶半导体衬底上形成至少一个牺牲层;构图所述至少一个牺牲层,形成由暴露的衬底区环绕的牺牲栅形结构;在所述牺牲栅形结构的相对侧上的所述暴露的衬底区内形成掺杂的半导体结区;在所述结区上形成源和漏接触金属化层,所述接触金属化层的厚度小于所述栅形结构的厚度;在所述源和漏接触金属化区上选择性地形成介质帽盖层,其中所述介质帽盖层的上表面与所述牺牲栅形结构的上表面持平;除去所述牺牲栅形结构露出所述衬底下面的区域和所述源和漏接触金属化的侧壁;淀积栅介质以覆盖所述露出的衬底区域,但不覆盖所述源和漏接触金属化的侧壁和上部;在所述源和漏接触金属化层的所述侧壁上形成介质侧壁隔离层;在所述栅介质和所述源和漏接触金属化上形成导电层,所述导电层也填充了原先由牺牲栅形结构占据的体积;以及构图所述导电层限定栅介质。
在上述方法中,在所述源和漏接触金属化层的所述侧壁上形成介质侧壁间隔层的所述步骤还包括选择材料与所述牺牲栅形结构的不同的间隔层介质。
在上述方法中,在所述源和漏接触金属化层的所述侧壁上形成介质侧壁隔离层的所述步骤是通过选自氧化和氮化组成的组中的一种工艺。其中,所述氧化是热氧化或阳极氧化。
当结合附图阅读下面本发明的详细说明书时,本发明的这些和其他特点、目的和优点将变得很显然。
附图说明
图1为示出形成图5实施例的早期步骤的剖面图。
图2为腐蚀步骤后图1结构的剖面图。
图3为沿图2的线30-30的俯视图。
图4A-4H为形成图5所示实施例的其它步骤的剖面图。
图5为本发明的一个实施例的剖面图。
图6A-6D为由图2的结构制备图4A的浅结区域的两个方法的剖面图;这些方法包括离子注入之后激活或气体浸没激光掺杂。
图7A-7B为由图2的结构制备图4A的浅结区域的另一方法的剖面图;该方法包括空间选择性外延生长原位掺杂的半导体。
图8A-8C为示出制备图4A的浅结区域的另一方法的剖面图;该方法包括覆盖(blanket)外延生长的原位掺杂的半导体,之后从沟道上的区域选择性除去。
图9A-9E为示出形成自对准、绝缘密封升高的源/漏接触的本发明的优选方法的示意图。
具体实施方式
现在参考附图详细地介绍提供了一种形成具有亚微米栅长度并为T形的自对准MOSFET方法的本发明,其中图中类似和相应的元件使用了类似的参考数字。
参考附图,图1示出了衬底2上的牺牲层1和可选的抛光终止层3的剖面图。所述可选的抛光终止层3可以用一种或多种适于防止GILD处理期间激光照射造成的损伤的材料代替或补充。衬底2可以为单晶半导体材料,适于形成MOSFET的沟道。衬底2可以为例如硅、硅锗、锗、砷化镓、砷化铟镓、磷化铟、或铟镓砷磷。牺牲层1为可以相对于衬底2选择性腐蚀的材料,可选抛光终止层3为在化学机械腐蚀期间可以用做抛光终止的材料。牺牲层1可以为例如低温淀积的氧化物,例如使用四乙氧基硅烷(TEOS)作为初始物通过化学汽相淀积(CVD)淀积的SiO2,但不仅限于此。所述形成至少一个牺牲层的步骤包括从SiO2、四乙氧基硅烷(TEOS)的衍生氧化物、可流动氧化物和Si3N4组成的组中选择一下层材料,从SiO2、四乙氧基硅烷(TEOS)的衍生氧化物、可流动氧化物、和Si3N4、TiN和硅组成的组中选择一上层材料的步骤。可选抛光终止层3的例子包括TiN、Si3N4或多晶硅,但不限这些。
图2示出了牺牲层1和可选抛光终止层3已构图在沟道区28上留下牺牲的栅形结构26和未来的源/漏区22和24中的开口区域之后图1的结构。牺牲的栅形结构26的横向尺寸通常等于最小光刻尺寸。图3示出了该结构的示意性俯视图,线30-30对应于图2中剖面部分所示的区域。
图4A-4H为形成图5所示实施例的继续步骤的剖面图。图4A示出了形成浅结区域4之后图2的结构,图4B示出了形成可选介质侧壁间隔层5之后图4A的结构。介质侧壁间隔层5可以通过例如各向异性地腐蚀保形淀积的侧壁间隔层材料的薄层(20-50nm)形成。
图4C示出了淀积导电的源/漏接触合金层6和可选的介质帽盖层7之后图4B的结构。在所述结区上形成源和漏接触金属化层的所述步骤包括在所述结区上选择生长所述接触金属化材料的步骤。源/漏接触合金层6可以是例如单独的Co、Ni、Pd、Pt、Rh、Ta、Ti、W、导电金属硅化物、重掺杂的多晶硅、或重掺杂的多晶硅锗,或它们的组合,可以通过例如化学汽相淀积(CVD)、溅射、或蒸发淀积。可选的介质帽盖层7和介质侧壁间隔层5密封了源/漏接触合金层。可选的介质帽盖层7和介质侧壁间隔层5的材料可以相同或不同。所述介质帽盖层包括选自SiO2、四乙氧基硅烷(TEOS)的衍生氧化物、可流动氧化物和Si3N4组成的组中的平面化介质。优选材料包括如SiO2、或Si3N4的淀积介质,和介质金属氧化物或金属6的氮化物。在所述源和漏接触金属化上层形成介质帽盖层的所述步骤包括从平面化介质、介质氧化物和介质氮化物组成的组中选择介质材料的步骤。所述形成所述介质帽盖层的步骤包括通过选自氧化和氮化组成的组中的工艺在接触金属化层上表面上生长所述帽盖层的步骤。上述方法还包括通过自氧化和氮化组成的组中选择的工艺在所述源和漏接触金属化层的侧壁上生长介质侧壁间隔层的步骤。
图4D示出了除去了包括牺牲层1和可选帽盖3的牺牲栅形结构后图4C的结构。通过选择性腐蚀将源和漏接触金属化层的上表面开槽到低于牺牲栅形结构上表面下的水平。牺牲层1优选通过湿腐蚀除去以避免反应离子腐蚀(RIE)对沟道区28的损伤。对于可选的介质侧壁间隔层5的材料为金属6的氧化物或氮化物的情况,可选的介质侧壁间隔层优选在除去牺牲栅形结构后形成。如下面将介绍的,形成热栅氧化物后这种侧壁间隔层可以通过阳极氧化工艺、或通过氧化形成。然后,在沟通区28上的衬底2上形成栅介质8。在图4E中,栅介质8也形成在侧壁间隔层5和绝缘覆盖层帽盖7上。栅介质8的厚度在约2到约10nm的范围内。当不存在可选的介质侧壁间隔层5时,栅介质8可以形成在衬底2上的沟道区28上、源/漏接触合金层6的暴露的侧壁上、和介质帽盖层7上,如图4F所示。空间选择氧化或氮化步骤也可以用于形成栅介质10,如图4G所示。例如,如果源/漏合金层6密封在如氮化硅等的保护性防氧渗透介质中,那么使用热氧化可以形成沟道区28上的薄氧化物。此外,包括合金层的氧化物6的介质侧壁间隔层可以用形成栅介质使用的相同氧化步骤形成。
参考图4H,可以为例如Al、W、带或不带适当的扩散阻挡层和带或不带下面的多晶硅的栅材料11形成在栅介质8上,并光刻构图限定出T形栅12。T形栅12在可选的介质帽盖层7、栅介质8和源/漏接触合金层6上延伸。在光刻构图的工艺中使用负性光刻胶。
可以为例如二氧化硅或流动氧化物等的绝缘材料14可以形成在暴露的栅氧化物8和T形栅12上。穿过材料14可以钻出孔或开口16,并用导电性材料18填充,以提供用于电路互连的接触,如图5所示。材料18可以为例如钨、铜、铬等。
图6A-6C为同图2的结构制备图4A的浅结区域的优选的离子注入法的剖面图。施加如SiO2、氮化硅或氮化钛等的屏蔽材料的薄层32覆盖计划的源/漏结区22和24,如图6A所示。屏蔽层32的厚度在约10到约90nm的范围内,优选约50nm。用适当的离子注入源/漏区22和24制成浅结,使用栅形结构作为掩模。结区可以掺杂:对于p沟道MOSFET为p型,对于n沟道MOSFET为n型。所述p型和n型结可以通过适当的阻挡掩模形成在相同的晶片上。用屏蔽层32原位激活退火,通过如选择性湿法腐蚀等的工艺除去屏蔽层32,形成图6C的结构。
图6D为由图2的结构制备图4A的浅结区域的气体浸没激光掺杂法的剖面图。具有图2所示结构的样品放置在含有掺杂剂原子的气体或液体40的环境中。入射的激光辐射42暂时地融化了源和漏区22和24内衬底的薄表面层,在整个融化深度快速并局部地引入掺杂剂原子。入射的激光辐射42可以是例如波长约308nm和脉冲持续时间约30ns的XeCl准分子激光辐射的脉冲,掺杂剂气体40例如可以为PH3。可选的抛光终止层3优选由一种或多种可以防止激光照射的损伤的材料代替或补充。这种层包括铝(高反射性的)、在激光波长包括多层介质镜面的多层SiO2和Si3N4、或例如具有高激光损伤阈值的W的吸收材料。
图7A-7B为由图2的结构制备图4A的浅结区域的优选空间选择性外延生长法的剖面图。通过例如热氧化物生长和湿法深腐蚀等的工艺可选地将源/漏区22和24开槽制成图7A的结构,原位掺杂的半导体外延生长在暴露的半导体衬底区上形成源/漏结4,如图7B所示。用于硅衬底的优选原位掺杂的半导体材料包括原位掺杂的硅和原位掺杂的SiGe。
图8A-8C为示出制备图4A的浅结区域的另一方法的剖面图。此时可以从图8A的结构开始,包括衬底2、外延生长的原位掺杂的半导体9、牺牲层1、以及可选的抛光终止层3。然后构图层3和1制成栅形结构26,如图8B所示。图4B到4C显示的工艺之后,层9选择性地从沟道28上除去。湿法腐蚀为优选的除去工艺,以避免RIE对沟道28的损伤。
图9A-9E为示出由图4B的结构形成自对准、绝缘密封升高的源/漏接触的优选方法的示意图。源/漏接触合金层的材料15淀积在栅形结构26上产生图9A的结构,然后平面化抛光终止层3产生具有分离的源/漏接触6的图9B的结构。材料15的优选材料为CVD淀积的钨,优选的平面化方法为化学机械抛光(CMP)。然后通过如RIE等的工艺相对于抛光终止层3的上表面开出平面化的源/漏接触,产生图9C的结构。然后淀积介质帽盖层17形成图9D的结构,并通过如CMP等的工艺平面化形成具有介质帽盖层7位于源/漏区上的图9E的结构。介质帽盖层17可以是氮化硅、SiO2或可流动的氧化物。抛光终止层3可以为如TiN、Si3N4等的氮化物或多晶硅。选择抛光终止层3和介质帽盖层7的相对厚度,以便不必整个地除去介质帽盖层7就可以除去抛光终止3和栅形结构1。
通过在源/漏区内选择性生长材料15,可以由图4B的结构替代地形成图9C的结构。可以使用CVD工艺在包括硅区和如SiO2的第二材料区的衬底硅区上选择性地生长钨。
此外,可以通过在源/漏合金区6的上表面上选择性地生长介质,由图9C的结构形成图9E的结构。这可由氧化或氮化工艺完成。例如,钨的源/漏合金区6可以阳极氧化或热氧化制备介质WO3的表面层。
这里介绍的本发明可以用于制备场效应晶体管(FET),例如金属半导体FET、调制掺杂的FET、金属氧化物半导体FET和电路。与这种FET的现有工艺步骤相比,本发明的结构和工艺制备了大大减少的栅和源/漏电阻,增加了FET器件和电路的速度并降低了功耗。器件设计很容易地缩小到较小的栅宽度和面积,而不会负面影响栅电阻。
虽然已说明和示出了具有T形栅的FET结构,以及在形成自对准的栅介质和T形栅之前形成与原有结区自对准的的升高的源/漏接触的基础上制备这种结构的方法,显然本领域的技术人员可以做出修改和变形,而不脱离仅由附带的权利要求书的范围限定的本发明的最宽范围。
Claims (27)
1.一种形成场效应晶体管的方法,包括以下步骤:
在半导体衬底的至少一个表面上形成至少一个牺牲层,
构图所述至少一个牺牲层,形成由暴露的衬底区环绕的牺牲栅形结构,
在所述牺牲栅形结构的相对侧上的所述暴露的衬底区内形成掺杂的半导体结区,
在所述结区上选择性地形成源和漏接触金属化层,
在所述源和漏接触金属化层上选择性地形成介质帽盖,
除去所述牺牲栅形结构以露出所述衬底的下面的区域和所述源和漏接触金属化层的侧壁,
淀积栅介质覆盖所述露出的衬底区域和所述源和漏接触金属化层的侧壁和上部,
在所述栅介质的所有表面上形成导电层,所述导电层也填充了原先由牺牲栅形结构占据的体积,以及
构图所述导电层限定栅介质。
2.根据权利要求1的方法,特征在于所述半导体材料为选自由GaAs、InGaAs、InP、Si、InGaAsP和SiGe组成的组中的一种单晶材料。
3.根据权利要求1的方法,特征在于所述形成至少一个牺牲层的步骤包括从SiO2、四乙氧基硅烷(TEOS)的衍生氧化物、可流动氧化物和Si3N4组成的组中选择一下层材料,从SiO2、四乙氧基硅烷(TEOS)的衍生氧化物、可流动氧化物、和Si3N4、TiN和硅组成的组中选择一上层材料的步骤。
4.根据权利要求1的方法,特征在于所述形成源和漏接触金属化层的步骤包括从Co、Ni、Pd、Pt、Rh、Ta、Ti、W、这些金属的导电硅化物、重掺杂的多晶硅、或重掺杂的多晶硅锗组成的组中选择至少一个接触金属化材料的步骤。
5.根据权利要求1的方法,特征在于在所述源和漏接触金属化上层形成介质帽盖层的所述步骤包括从平面化介质、介质氧化物和介质氮化物组成的组中选择一种介质材料的步骤。
6.根据权利要求5的方法,特征在于所述介质帽盖层包括选自SiO2、四乙氧基硅烷(TEOS)的衍生氧化物、可流动氧化物和Si3N4组成的组中的一种平面化介质。
7.根据权利要求5的方法,特征在于所述介质帽盖层包括选自TiO2、Ta2O5和WO3组成的组中的一种介质氧化物。
8.根据权利要求1的方法,特征在于所述形成掺杂的半导体结的步骤包括离子注入和激活退火。
9.根据权利要求1的方法,特征在于所述形成掺杂的半导体结的步骤包括气体浸没激光掺杂。
10.根据权利要求1的方法,特征在于所述形成掺杂的半导体结的步骤包括在未由所述牺牲栅覆盖的所述暴露的衬底区上选择性外延生长掺杂的半导体结。
11.根据权利要求1的方法,特征在于在所述结区上形成源和漏接触金属化层的步骤包括覆盖(blanket)淀积所述接触金属化材料并平面化的步骤。
12.根据权利要求11的方法,特征在于通过化学机械抛光进行所述平面化。
13.根据权利要求11的方法,还包括通过选择性腐蚀将源和漏接触金属化层的上表面开槽到低于牺牲栅形结构上表面下的水平的步骤。
14.根据权利要求1的方法,特征在于在所述结区上形成源和漏接触金属化层的所述步骤包括在所述结区上选择生长所述接触金属化材料的步骤。
15.根据权利要求1的方法,特征在于所述形成所述介质帽盖层的步骤包括覆盖淀积并平面化所述介质帽盖材料的步骤。
16.根据权利要求1的方法,特征在于所述形成所述介质帽盖层的步骤包括通过选自氧化和氮化组成的组中的一种工艺在接触金属化层上表面上生长所述帽盖层的步骤。
17.根据权利要求16的方法,特征在于所述氧化为热氧化或阳极氧化。
18.根据权利要求1的方法,特征在于还包括在牺牲栅形结构上形成介质侧壁间隔层的步骤,所述侧壁间隔层由与所述牺牲栅形结构的材料不同的材料形成。
19.根据权利要求1的方法,特征在于还包括通过自氧化和氮化组成的组中选择的一种工艺在所述源和漏接触金属化层的侧壁上生长介质侧壁间隔层的步骤。
20.根据权利要求19的方法,特征在于所述氧化为热氧化或阳极氧化。
21.根据权利要求1的方法,特征在于:所述接触金属化层的厚度小于所述栅形结构的厚度,且
其中所述介质帽盖层的上表面与所述牺牲栅形结构的上表面持平。
22.一种场效应晶体管,包括:
半导体衬底,
两个隔开的掺杂的半导体区,形成源和漏结区,并限定出两者之间的沟道衬底区,
所述结区上的第一导电层,所述第一导电层形成源和漏接触金属化层,
所述接触金属化层的上表面上的第一介质层,
所述沟道衬底区上的栅介质,在所述接触金属化层的侧壁和上表面上延伸,以及
具有T形截面的栅,包括所述栅介质上的第二导电层,该层在第一介质层和部分源和漏接触金属化层上延伸。
23.根据权利要求22的结构的场效应晶体管,特征在于所述结构还包括置于栅介质和接触金属化层的侧壁之间的介质侧壁间隔层。
24.一种形成场效应晶体管的方法,包括以下步骤:
在单晶半导体衬底上形成至少一个牺牲层,
构图所述至少一个牺牲层,形成由暴露的衬底区环绕的牺牲栅形结构,
在所述牺牲栅形结构的相对侧上的所述暴露的衬底区内形成掺杂的半导体结区,
在所述结区上形成源和漏接触金属化层,所述接触金属化层的厚度小于所述栅形结构的厚度,
在所述源和漏接触金属化区上选择性地形成介质帽盖层,其中所述介质帽盖层的上表面与所述牺牲栅形结构的上表面持平,
除去所述牺牲栅形结构露出所述衬底下面的区域和所述源和漏接触金属化的侧壁,
淀积栅介质以覆盖所述露出的衬底区域,但不覆盖所述源和漏接触金属化的侧壁和上部,
在所述源和漏接触金属化层的所述侧壁上形成介质侧壁隔离层,
在所述栅介质和所述源和漏接触金属化上形成导电层,所述导电层也填充了原先由牺牲栅形结构占据的体积,以及
构图所述导电层限定栅介质。
25.根据权利要求24的方法,特征在于在所述源和漏接触金属化层的所述侧壁上形成介质侧壁间隔层的所述步骤还包括选择材料与所述牺牲栅形结构的不同的间隔层介质。
26.根据权利要求24的方法,特征在于在所述源和漏接触金属化层的所述侧壁上形成介质侧壁隔离层的所述步骤是通过选自氧化和氮化组成的组中的一种工艺。
27.根据权利要求26的方法,特征在于所述氧化是热氧化或阳极氧化。
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US08/989,042 US5955759A (en) | 1997-12-11 | 1997-12-11 | Reduced parasitic resistance and capacitance field effect transistor |
US989042 | 1997-12-11 |
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US5955759A (en) | 1999-09-21 |
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