TW442918B - Reduced parasitic resistance and capacitance field effect transistor - Google Patents

Reduced parasitic resistance and capacitance field effect transistor Download PDF

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TW442918B
TW442918B TW087120341A TW87120341A TW442918B TW 442918 B TW442918 B TW 442918B TW 087120341 A TW087120341 A TW 087120341A TW 87120341 A TW87120341 A TW 87120341A TW 442918 B TW442918 B TW 442918B
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Khalid Ezzeldin Ismail
Stephen Anthony Rishton
Katherine Lynn Saenger
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
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    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

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Description

4429 1 8 五、發明說明（1) 技術領域 本發明係關於半導體，且更明確地說，係關於自我校準 之金屬氧化物半導體（M0S)場效應電晶體（FET)，且該種 FET具有次微求之間極長度及—τ_型閘極。 以前技術 ^隶新技術之金屬氧化物半導體場效應電晶體（Fet) =2閘極長度至低於〇. 25微来。用以構成間極之標準 製程是沉積多晶矽層，蝕刻此層以界定所需之閘極長度， 使用哀夕0曰石夕層做為源極/没極淺佈植步釋之遮罩。緊 接在淺佈植步驟之後的是構成氮化物侧壁間隔層，佈植深 馱姆區於源極/,及極區，且接著構成一通往閘極與源極，汲 極佈植之金屬矽化物。因此，開極之電阻隨著閘極長度之 :低而增加’目為間極金屬矽化物具有相同於位於其下之 多晶石夕間極之閘極善。pq A t τ長度 閘極電阻使得裝置變慢，因為r c k間延遲。此外，可拉出皮各 π y + 了精由在氡化物層開啟一窗及使得金屬 圖樣化來構成一長於容S石々pq j L ^ 焚、夕Ba矽閘極之金屬閘極。此製程已產 生到目前為止所知之畏体壯_ 。 &取嵌夕裝置，但是需要針對啟始之多 晶石夕閘極進行高度關键之音虹“ & L , &山 關鍵之重新校準，且如果該重新校準失 敗，則會因為歐姆源拖/汲托 二丄⑷ , 你杜/及極接點而使閘極縮短》因此， 刖述製程不相容於半導體製造。 當MOS FET之閘極長卢缩鉑 . π ^ 货度雄知蚪，歐姆源極/汲極接點在深 度上必須加以松，封，以俘輯鬥^ — 一 L丄& ^ 乂保得間極長度相對於接面深度之長 沐比大於一。淺接面夕丨士成„τ„上 ^ rt ^ ^ s 此項氣永對於可自接面消耗以構成 低電阻性金屬石夕化物接％夕 物接^之砂之數量造成上限。相關於較 i :4429 1 8 J -—------ I五、發明說明（2) 薄之破化彳封丨馬/、 之 速度效能。~ ^極接點之較高電阻可進一步損害Fet 根據本發明’—話發明摘要& + 序列受到說明，且，，製造場效應电晶體之結構及製f 易，周整至次微求之大小 〈長度及足度皆可秦 /汲極接點，且守笪 、王h賴於福：忐描古+ ' ^ ^ ^ ^ ^ e, ^ ^， / ^ ^ ^ νΛν ^ ^ ^ Λ Λ
本發明提供—種降用低寄生問極電陡。 或金J ::無關鍵校準步驟之下構/之製程，且該種製箱 為降低之閘極電阻。 .型金屬閘極，及導致> 閘ϋ:進—步提供-種新製程，且 攻搞μ構成，且該等了—型閘極自我i该種新製程允許7一型 〇 2微牛點’而無需任何關鍵校準，：準於既存之淺源極/ 圍之閉極長度，本發明Λ如，對於屬於G.05至 +確度。 達成大約〇 · 2微米之校 遽i ΐ明進—步提供另一種新掣矛。 杧f屬/多晶矽級合來構成，且無1，其中間極是藉由金屬 2氐之閘極接點電阻。’、’、而住何矽化，且可造成 雉：發：進一步提供—種製程，其中4 極導卿之我杈準於既存之淺接面區，=導電性源極/汲極 祕v組之刖受到沉積。既存之〜技疋在閘極電介質及閘 植且接著實施退丄既;:：；=;最好是藉由離子佈 _ 潍邊化半導體之空間選 4 4 2 9 1 8. 五、發明說明（3) 擇性外延生長，或藉由一製程，例如氣浸雷射雜質化 (GILD)來構成，且在GILD中接面區受到高強度雷射光之照 射，在包含雜質原子之氣體之圍繞下。 本發明進一步提供許多用以封裝提高之源極/汲極接點 以使該等接點與閘極電氣隔絕之方法。 圖式之簡單說明 當參照附圖來閱讀本發明之下列詳細說明時應可明暸本 發明之該等及其他特點，目標，及優點，其中： 圖1是用以展示構成圖5之實例之早期步驟的橫截面圖。 圖2是在餘刻步驟以後之圖1結構之橫截面圖。 圖3是圖2沿線3 0 -3 0之頂視圖/ 圖4A-4H是用以展示構成圖5所示之實例之其他步驟的橫 截面圖。 圖5是本發明之一實例之橫截面圖。 圖6A-6D是用以展示二方法之橫截面圖，且該二方法是 利用圖2之結構來產生圖4 A之淺接面區；且該二方法包含 離子佈植及隨後之活化或氣浸雷射雜質化。 圖7A-7B是用以展示另一方法之橫截面圖，且該方法是 利用圖2之結構來產生圖4 A之淺接面區；且該方法包含原 址雜質化半導體之空間選擇性外延生長。 ί 圖8A-8C是用以展示另一方法之橫截面圖，且該方法是 用以產.生圖4 Α之淺接面區；且該方法包含原址雜質化半導 體之覆蓋外延生長，及隨後之自通道以上之區域選擇性去 除該覆蓋外延生長。
第6頁 4 429 1 8 五 '發明說明（4) 是用以展示本發明之—較佳方法之橫截面圖， / :極接=…以構成自我校準，絕緣之峨高源極 較佳實例說明 種更加詳細說明本發明，|本發明提供- 我校準之M〇S FET之方法，且該等MOS FET具 有次被米之閘極長度並是T _型，I巾 uu㈤α 其中相同之參考號碼是用 以畏不附圖之相同及對應組件。 現在請參看附圖，圖1展示基質2之犧牲層1及隨意之研 磨止塊3之橫截面圖。該隨意之研磨止塊3可利两特製成為 防止在GILD處理期間雷射造成損壞之—或更多材料來加以 取代或補強。基質2可為適合構成要建立之肋3 FET之通道 的單一晶體半導體材料。基質2可為，例如，矽’鍺化 矽，鍺，砷化鎵，砷化銦鎵，磷化銦，或磷砷銦鎵。犧牲 層1是一種可相對於基質2來選擇性蝕刻之材料，且隨意之 研磨止塊3是一種可在化學機械银刻期間做為研磨止塊之 材料。犧牲層1可為下列材料：例如，但不限於，低溫沉 積之氧化物’例如藉由使用TEOS做為先導劑之化學氣相沉 積（C V D )來；儿積之S i 02 °隨思之研磨止塊3之範例包含，但 不限於，T i N，S i 3 N4或多晶矽。 圖2展示圖1之結構’在犧牲層1及隨意研磨止塊3已受到 圖樣化以留下犧牲閘型結構2 6於通道區2 8之上，及開口區 於未來之源極/>及極區2 2及2 4之後。犧牲閘型結構2 6之橫 向大小一般而言等於最小之光刻大小，圖3展^該結構之
第7頁 4429l8 五、發明說明（5) :思了貝視圖，且線3 0 -3 〇對應於圖2之橫戴 域。 所展示之區 圖4A-4F是用以展示構成圖5所示之實例之 截面圖。圖“展示在構成淺接面區4以後其他步驟的橫 :仙展示在構成隨意之電介質側壁間隔層結構’ _ =構。電介質側壁間隔層5可，.例如，藉由^之圖4A的::薄層(2°-5〇奈幻之等形沉積側壁間隔：；方向性钱 战 屬材料來構 且 口兮b展不在沉籍道 質封蓋7以後之圖%型源極/汲極接點冶金6及卩左立命人 例如，c〇 p之結構。源極/汲極接點一逍思;丨 :物’摻高濃度雜質：广，Ta ’ Tl，W，導電型全屬石夕 化矽，無論是^雜貝之多晶矽，或摻高濃度雜料金屬\ 二可藉由，你“α ^ =種％質之任-，重*質或他：^ f :石， M沉積。隨意 學氣相沉積（CVD )…踐鍍，吱_ ，、且5 ， 極/沒極接机〜史電介質刼这7 R帝八断加—气游氣來加 極/沒祐、、之' 卷介·哲+, 欺乳求刃σ 極接合金。V:蓋7及電介質側壁⑽層5封裝源 同或不卜電介質封蓋7及電介質倒壁間隔層 或以州4 ,=。較佳之材料包含沉積之電介質， 之材科可相 例如S i 〇2 物〇 圖展示 及電介質金屬氧化物或金屬g 之氮化 牲閘型結構，4 C <結 來加以去除人到去吟 > 在包含犧牲層1及隨意封蓋3之犧 成損壞。對扒只避免^後。犧牲層1最好是藉由濕性蝕刻 化物或氮化4k蹲急 < =性離子蝕刻（RIE)對於通道區28造 63 氺免介質側壁間隔層5之材料是金屬氧 ^ ’隨意之電介質侧壁間隔層最好是
4429 ί8
ίίΓί:開型結構之後構成。此種側壁間隔展 來構成，::下^由在構成熱閉極氧化物之後藉由陽 下所述。拷签，關"is； + Λ 項^ Υ丁·"fb， ST，上。在圖4"，閘極電：二質也8Ϊί於基質2之通 I約】Γ奈緣/之層封蓋7。間極電介質8之厚度G ^壁間隔 5，開極電介質=。如果沒有隨意之·電介質倒辟、大約2至 極接點冶金構成於基質2之通道區28之上，=層 、 6之暴露側壁之上，座+ 源極/淡 4F所示。空間選擇性氧化或氮化與二介/物之上，如圖 示之間極電介質Η。例如也可用以構成圖4“斤 :=區28之上，如果源極 用薄層氧化 透乳電介質，例如氮化石夕，來加以二金6:利用保護型不 氧化糾.之電介質側壁間隔層可 另外、，包含冶金 夤之氣化步驟來加以構成。 目5於構成閘極電介 受二閘極材料11構成於閘極電介質8之上，且 為，Ϊ =化:界且定二， 層，且*下可呈有或，、有或曰不具*適當之擴散障礙 隨意之電介質封蓋7，閘極電 =極U延伸通過 金6。負光阻劑可用於光刻圖樣化之製及程原極/没極接點冶 絕2 :暴露之閘極氧化物8及「型閘極 ί 例如’二氧化石夕或可流動型氧化 牙孔或開口 1 6可穿越材料1 4，艿古次暹命k u " 提供用於電路連接之接點，如圖5所*。材料；可為？ 8:
第10頁 4429 1 8 五、發明說明（8) 有高度反射性），多層之S i 〇2及s i 3N4，或吸收材料’且該 等多層之5102及3丨3比，包含一在雷射波長之多層電介質 鏡，而該吸收材料可為，例如，鎢，且鎢具有極高之雷射 損壞臨限值。 圖7A -7B是用以展示一較佳之空間選擇性外延生長方法 之橫載面圖，且該方法是利用圖2之結構來產生圖4 Α之淺 接面區。在藉由一製程隨意地下四源極/ ί及極區2 2及2 4：以 產生圖7 Α之結構之後，且該製程·^為，例如’熱氧化物生 長及濕性回蝕，一原址雜質化半導體外延生長於暴露之半 導體基質區，以構成源極/汲極區4，如圖7 β所示。梦基質 之較佳原址雜質化半導體材料包含原址雜質化之矽及原址 雜質化之SiGe。 圖8A-8C是用以展示另一方法之橫截面圖，且該方法是 用以產生圖4 A之淺接面區。在此種情形之下，該方法開始 於圖8 A之結構，立該結構包含基質2 ’外延生長之原址雜 質化半導體9，犧牲層1，及隨意之研磨止塊3。層3及1接
著受到圖樣化以產生閘型結構26，如圖8B所示。在如圖4B 至4 C之處理之後’層9自通道2 8以上受到選擇性去除。濕 性餘刻是能夠避免r I E對於通道2 8造成損壞之較佳去除製 程。 圖9A-9E是用以展示一較佳方法之横截面圖，且該較佳 =去=用以產生自我杈準，絕緣封裝之提高源極/汲極接 二門m結構開㉟。源極’波極接點冶金之材料15沉 積於閘型結構26以產生圖9A之結構，且接著受到平坦化至
第11頁 4 429 t 8 _ 發明說明（9) :磨止塊3以產生圖⑽之結構，且離 點6。椅料1 5之一較佳MB 之源極/汲極接 佳之见 佳材科是藉由CVD來沉積之鎮，日牧 極接1坦化方法是化學機械研磨（CMP)。平扭化之为；^卓父 藉由一製程，例通，來相對於：：：= 及 G =以構成圖⑽之結構，且藉由一製程，例如⑽接考 極區：上;成圖9E之結構，且電介質封蓋7位於源極/汲 流動型氧彳卜Ϊ介質封蓋層17可為氮化矽，二氧化矽，或可 ，或多曰匕物.。研磨止塊3可為氮化物’例如TiN或以一 成為研Π。研磨止塊3及電介質封蓋7之相對厚度是選4擇 之下止塊3及閘型結構1可在未完全去除電介質封蓋7 卜文到去除α
圖9 C之杜摄D w構另外可藉由選擇性生長材料1 5於源極/汲極 跑及利用rsi y η 圖4β之結構來構成。CVD製程可用以選擇性生長 竭於~篇；@ & 恭貝之矽區’且該基質包含矽區及第二材料區，而 弟二材料可為，例#，二氧化珍。 圖9 E之沾加 。構另外可藉由選擇性生長一電介質於源極/汲 極冶金ρ? β ^ b之頂部表面及利用圖9 C之結構來構成。此可藉 由氧化或敗化製程來達成。例如，利用鎢製成之源極/汲 極’台金區6可受到陽極或熱氧化以產生電介質W03之一表面 層。 本案所描述之發明可用以製造場效應電晶體（F E T )’例 如金屬半導體FET，調變雜質化FET，金屬氧化物半導體 FET及電路。相較於此種FET之現有製程步驟，本發明之結 4 4 2 9 1 8 五、發明說明（ίο) 構及製程產生遠較小之閘極及源極/汲極電阻，而導致較 高之FET裝置及電路速度及較小之功率損耗。裝置設計可 輕易調整成為較小之閘極寬度及區域，而不致對於閘極電 阻造成負面影響。 雖然本案已經說明及展示一具有T -型閘極之FET結構， 及一種用以製造此種結構之方法，且該方法是基於，在構 成一自我校準之閘極電介質及T-型閘極之前，構成自我校 準於既存接面區之提高源極/汲極接點，熟悉本技術領域 者應可明瞭，在不脫離本發明之範疇之下，可進行修改及 變動，而本發明之範疇只受限於附加之申請專利範圍之範
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Claims (1)

  1. • 4429 1 8 Γ---------------\ I六、申請專利範圍 1, 一種用以構成場效應電晶體之方法，且該種方法包含 下列步驟： 構成至少一犧牲層於半導體基質之至少一表面； 使得該至少一犧牲層圖樣化以構成一犧牲閘型結 構’且該結構為暴露之基質區所圍繞； 構成捧雜質之半導體接面區於該等暴露之基質區之 該犧牲閘型結構的相對侧； 構成源極及汲極接點冶金於該等接面區，且該接點 冶金之厚度低於該間型結構之厚度； 選擇性構成一電介質封蓋層於該源極及汲極接點冶 金之諸區，其中該電介質封蓋層具有一頂部表面，且該頂 部表面幾乎與該犧牲閘型表面之頂部表面等高； 去除該犧牲閘型結構至該基質之該等暴露下區，與 該源極及汲極接點冶金之側壁； I 沉積一閘極電介質以覆蓋該等暴露之基質區，與該 1 : i源極及汲極接點冶金之侧壁及頂部； | 構成一導電層於該閘極電介質之所有表面，且該導丨 I電層也幾乎填滿先前為犧牲閘型結構所佔用之體積；及 j 使得該導電層圖樣化以界定一間電極。 j 2.如申請專利範圍第1項之方法，其中該半導體材料是 | 自包含 GaAs，InGaAs，InP，Si，InGaAsP 及 SiGe 之群組選 j出之早晶材料。 j 3 ·如申請專利範圍第1項之方法，其中構成至少一犧牲 |層之步驟包含選擇一底層材料及一頂層之步驟 > 且該底層
    第14頁 i • 4 429 1 8 I六、申請專利範圍 材料是自包含Si 02，TEOS，衍生型氧化物，可流動型氧化 物及S i3 N4之群組選出，而該頂層是自包含S i 02，TE0 S，衍 生型氧化物，及可流動型氧化物，S i 3 N4，T i N及梦之群組 選出。 4. 如申請專利範圍第1項之方法，其中構成源極及汲極 接點冶金之該步驟包含選擇至少一接點冶金材料之步驟， j 且該材料是自包含Co，Ni，Pd，Pt，Rh，Ta，Ti，W，該 等金屬之導電性矽化物，摻高濃度雜質之多晶矽，及摻高 濃度多晶矽鍺之群組選出。 5. 如申請專利範圍第1項之方法，其中構成一電介質封 蓋於該源極及汲極接點冶金之該步驟包含選擇一電介質材 料之步驟，且該電介質材料是自包含平坦化電介質，電介 質氧化物及電介質氮化物之群組選出。 6. 如申請專利範圍第5項之方法，其中該電介質封蓋包 [含一可平坦化電介質，且該可平坦化電介質是自包含 | S i 02，TE0S，衍生型氧化物，可流動型氧化物及S i3N4之群 丨组選出。 I ! 7.如申請專利範圍第5項之方法，其中該電介質封蓋包 I含一電介質氧化物，且該電介質氧化物是自包含Ti02， I Ta2 05及W03之群組選出。 | 8,如申請專利範圍第1項之方法，其中構成摻雜質之半 I導體接面之該步驟包含離子佈植及活化退火。 ! 9.如申請專利範圍第1項之方法，其中構成摻雜質之半 I導體接面之該步驟包含氣浸雷射雜質化。
    第15頁 4 429 1 8 六、申請專利範圍 10. 如申請專利範圍第1項之方法，其中構成摻雜質之 半導體接面之該步驟包含選擇性外延生長一摻雜質之半導 體於該犧牲閘未覆蓋之該等暴露基質區。 11. 如申請專利範圍第1項之方法，其中構成源極及汲 極接點冶金於該等接面區之該步驟包含用以進行該接點冶 金材料平坦化之覆蓋沉積之步驟。 12. 如申請專利範圍第1 1項之方法，其中該平坦化是藉 由化學機械研磨來執行。 13. 如申請專利範圍第11項之方法，且該方法進一步包 含下列步驟：藉由選擇性蝕刻使得源極及汲極接點冶金之 頂部表面下K至低於犧牲閘型結構之頂部表面之位準。 14. 如申請專利範圍第1項之方法，其中構成源極及汲 極接點冶金於該等接面區之該步驟包含選擇性生長該接點 冶金材料於該等接面區之步驟。 15. 如申請專利範圍第1項之方法，其中構成該電介質 封蓋層之該步驟包含下列步驟：該電介質封蓋之材料之覆 蓋沉積及平坦化。 16. 如申請專利範圍第1項之方法，其中構成該電介質 | 封蓋層之該步驟包含下列步驟：籍由一製程來生長該封蓋 | 層於接點冶金頂部表面，且該製程是自包含氧化及氮化之 群組選出。 17. 如申請專利範圍第1 6項之方法，其中該氧化是熱氧 化或陽極氧化。 I 18. 如申請專利範圍第1項之方法，且該方法進一步包 i
    第16頁 ] q I六、申請專利範圍 含構成電介質側壁間隔層於犧牲閘型結構之步驟，且該等 電介質間隔層是利用一材料來構成》而該材料極不同於該 犧牲間型結構之材料。 19. 如申請專利範圍第1項之方法，且該方法進一步包 含下列步驟：藉由一製程來生長電介質側壁間隔層於該源 極及汲極接點冶金之侧壁，且該製程是自包含氧化及氮化 之群組選出。 20. 如申請專利範圍第1 9項之方法，其中該氧化是熱氧 化或陽極氧化。 21. —種用以構成場效應電晶體之方法，且該種方法包 含下列步驟： . 構成至少一犧牲層於半導體基質之至少一表面； 使得該至少一犧牲層圖樣化以構成一犧牲閘型結 構’且該結構為暴露之基質區所圍繞； 構成摻雜質之半導體接面區於該等暴露之基質區之 I該犧牲閘型結構的相對侧； j 選擇性構成源極及汲極接點冶金於該等接面區； | | 選擇性構成一電介質封蓋於該源極及汲極接點冶 丨 丨金； 丨 ! 1 I 去除該犧牲閘型結構至該基質之該等暴露下區，與| I ' I該源極及汲極接點冶金之侧壁； 丨 ! ! | 沉積一閘極電介質.以覆蓋該等暴露之基質區，與該j 源極及汲極接點冶金之側壁及頂部； i 構成一導電層於該閘極電介質之所有表面，且該導i
    第17頁 、4 429 彳 8 六、申請專利範圍 電層也幾乎填滿先前為犧牲閘型結構所佔用之體積；及 使得該導電層圖樣化以界定一閘電極。 2 2. 一種場效應電晶體’且該種場效應電晶體包，含. 一半導體基質； 二分隔之摻雜質半導體區，且該二半導體區構成源 極及〉及極接面區’且界定位於該二區間之'一通道基質區， 位於該等接面區之上之第一導電層，且該第一導電 層構成源極及汲極接點冶金； 位於該接點冶金之頂部表面之第一電介質層； 一位於該通道基質區且延伸通過該接點冶金之侧壁 及頂部表面之閘極電介質；及 一具有T-型橫截面之閘極，且該閘極包含第二導電 層，而該第二導電層位於該閘極電介質，且延伸通過第一 電介質層與源極及汲極接點冶金之部份。 2 3. —種場效應電晶體，且該種場效應電晶體包含如申 請專利範圍第2 2項之結構，且該結構進一步包含位於閘極 電介質及接點冶金之侧壁間之電介質侧壁間隔層。 〜 2 4. —種場效應電晶體，且該種場效應電晶體包含如申 請專利範圍第2 2項之結構，且該結構在侧壁或源極/汲極 頂部未具有閘極電介質。 2 5. —種場效應電晶體’且該種場效應電晶體包含如申 請專利範圍第2 3項之結構=且該結構在侧壁或源極/汲極 頂部未具有閘極電介質。 2 6. —種用以構成場效應電晶體之方法，且該種方法包
    第18頁 4429 1 8 六、申請專利範圍 含下列步驟： 構成至少一犧牲層於一單晶半導體基質； 使得該至少一犧牲層圖樣化以構成一犧牲閘型結 構，且該結構為暴露之基質區所圍繞， 構成推雜質之半導體接面區於該等暴露之基質區之 該犧牲閘型結構的相對側； 構成源極及汲極接點冶金於該等接面區，且該接點 冶金之厚度小於該閘型結構之厚度； 選擇性構成一電介質封蓋層於該源極及汲極接點冶 金之諸區，其中該電介質封蓋層具有一頂部表面，且該頂 部表面幾乎與.該犧牲閘型表面之頂部表面等高； 去除該犧牲閘型結構至該基質之該等暴露下區，與 該源極及汲極接點冶金之侧壁； 沉積一閘極電介質以覆蓋該等暴露之基質區，但不 ] 覆蓋該源極及汲極接點冶金之侧壁； 構成電介質側壁間隔層於該源極及汲極接點冶金之 該等侧壁； 構成一導電層於該閘極電介質與該源極及汲極接點 冶金，且該導電層也幾乎填滿先前為犧牲閘型結構所佔用 之體積；及 | 使得該導電層圖樣化以界定一閘電極。 2 7.如申請專利範圍第2 6項之方法，其中構成該等電介 質侧壁間隔層於該源極及汲極接點冶金之側壁之該步驟進 一步包含選擇一間隔層電介質，且該間隔層電介質極為不 丨
    第19頁 4 42 9 1 8 々、申請專利範圍 同於該犧牲閘型結構之材料。 28. 如申請專利範圍第26項之方法，其中構成該等電介 質側壁間隔層於該源極及汲極接點冶金之侧壁之該步驟是 藉由一製程來達成，且該製程是自包含氧化及氮化之群組 選出。 29. 如申請專利範圍第2 8項之方法，其中該氧化是熱氧 化或陽極氧化。
    第20頁
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