CN112447699A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN112447699A CN112447699A CN202010069971.7A CN202010069971A CN112447699A CN 112447699 A CN112447699 A CN 112447699A CN 202010069971 A CN202010069971 A CN 202010069971A CN 112447699 A CN112447699 A CN 112447699A
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- semiconductor chip
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- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
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Abstract
实施方式提供提高了可靠性的半导体装置。实施方式的半导体装置具有:基体;设置在基体之上的半导体芯片;第1端子板,经由设置在基体之上的第1超声波接合部与半导体芯片电连接,具有与半导体芯片对置的第1面;以及第1粘接层,设置于第1面,包含第1粘接剂。
Description
关联申请
本申请享受以日本专利申请2019-161843号(申请日:2019年9月5日)为基础申请的优先权。本申请通过参照该基础申请,包含基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置。
背景技术
正在进行面向发电或送电、泵或鼓风机等旋转机、通信系统或工厂等的电源装置、基于交流马达的铁道、电动车、家庭用电产品等广阔领域的、MOSFET(Metal-Oxide-Semiconductor Field-Effect-Transistor,金属氧化物半导体场效应晶体管)或IGBT(Insulated Gate BipolarTransistor,绝缘栅双极型晶体管)等的、设计为电力控制用的功率半导体芯片的开发。
此外,正在进行使用了该功率半导体芯片的作为功率模块的半导体装置的开发。对于这样的半导体装置,要求高电流密度化、低损失化、高散热化等规格。
发明内容
本发明的实施方式提供可靠性高的半导体装置。
实施方式的半导体装置具备:基体;设置在基体之上的半导体芯片;第1端子板,经由设置在基体之上的第1超声波接合部而与半导体芯片电连接,具有与半导体芯片对置的第1面;以及第1粘接层,设置于第1面,包含第1粘接剂。
附图说明
图1是第1实施方式的半导体装置的示意截面图。
图2的(a)~图2的(d)是第1实施方式的第1半导体芯片以及第2半导体芯片的示意图。
图3是第1实施方式的电力变换装置的示意电路图。
图4是表示第1实施方式的半导体装置的制造方法的流程图。
图5是第1实施方式的比较方式的半导体装置的示意截面图。
图6是第2实施方式的半导体装置的示意截面图。
具体实施方式
以下,参照附图对本发明的实施方式进行说明。另外,以下的说明中,有对相同或类似的部件附加相同的标号的情况。此外,关于说明过一次的部件等,有适当省略其说明的情况。
本说明书中,为了表示部件等的位置关系,将附图的上方向记述为“上”,将附图的下方向记述为“下”。本说明书中,“上”、“下”的概念不一定是表示与重力方向的关系的用语。
(第1实施方式)
本实施方式的半导体装置具备:基体;设置在基体之上的半导体芯片;第1端子板,经由设置在基体之上的第1超声波接合部而与半导体芯片电连接,具有与半导体芯片对置的第1面;以及第1粘接层,设置于第1面,包含第1粘接剂。
图1是本实施方式的半导体装置100的示意截面图。
半导体装置100具备基材2、第1绝缘板12、第2绝缘板14、第1金属板16、第2金属板18、第3金属板20、第4金属板22、第5金属板24、第1半导体芯片26、第2半导体芯片28、第1接合材料30、第2接合材料32、第3接合材料34、第4接合材料36、焊丝38a、焊丝38b、第1超声波接合部50、第2超声波接合部52、第3超声波接合部54、第1粘接层60、第2粘接层62、第3粘接层64、第1金属片70、第2金属片72、第3金属片74、散热板80、热界面材料(TMI:ThermalInterfaceMaterial)82、壳体84、封固材料(凝胶)86、盖88、第1端子板90、第2端子板92、第3端子板94、螺钉96以及垫圈98。
散热板80在下部具有翅片81。散热板80用于将从后述的半导体芯片等产生的热进行散热。
基材2设置在散热板80之上。基材2由Cu(铜)或Al(铝)等金属形成。另外,基材2也可以由Cu类的合金、Al类的合金或其他合金形成。此外,基材2例如也可以是在Cu板材的表面进行Ni(镍)等的电镀而得到的。
第1基体40(基体的一例)具有第5金属板24、第2绝缘板14、第1金属板16以及第2金属板18。
第5金属板24例如使用第4接合材料36接合在基材2之上。第2绝缘板14设置在第5金属板24之上。第1金属板16以及第2金属板18设置在第2绝缘板14之上。
第2基体42具有第4金属板22、第1绝缘板12以及第3金属板20。
第4金属板22例如使用第2接合材料32接合在基材2之上。第1绝缘板12设置在第4金属板22之上。第3金属板20设置在第1绝缘板12之上。
第1绝缘板12以及第2绝缘板14是例如由AlN(氮化铝)或SiN(氮化硅)、Al2O3(氧化铝(矾土))等形成的板材。
第1金属板16、第2金属板18、第3金属板20、第4金属板22、以及第5金属板24是例如由Cu(铜)形成的金属板,被用作电路布线。例如,第3金属板20以及第4金属板22使用未图示的钎料等接合于第1绝缘板12的表面。第3金属板20接合于第1绝缘板12的一方的表面。第4金属板22接合于第1绝缘板12的另一方的表面。例如,第1金属板16、第2金属板18以及第5金属板24使用未图示的钎料等接合于第2绝缘板14的表面。例如,第1金属板16以及第2金属板18接合于第2绝缘板14的一方的表面。第5金属板24接合于第2绝缘板14的另一方的表面。
图2是本实施方式的第1半导体芯片26(半导体芯片的一例)以及第2半导体芯片28的示意图。图2的(a)是本实施方式的第1半导体芯片26的示意俯视图。图2的(b)是图2的(a)的A-A’截面中的本实施方式的第1半导体芯片26的示意截面图。图2的(c)是本实施方式的第2半导体芯片28的示意俯视图。图2的(d)是图2的(c)的B-B’截面中的本实施方式的第2半导体芯片28的示意截面图。
第1半导体芯片26以及第2半导体芯片28是例如使用Si(硅)的Si-IGBT。第1半导体芯片26具有第1发射极电极27a(第1电极的一例)、第1集电极电极27b(第2电极的一例)以及第1栅极电极27c(第1控制电极的一例)。例如,第1发射极电极27a以及第1栅极电极27c设置于第1半导体芯片26的上表面,第1集电极电极27b设置于第1半导体芯片26的下表面。第2半导体芯片28具有第2发射极电极29a、第2集电极电极29b以及第2栅极电极29c。例如,第2发射极电极29a以及第2集电极电极29b设置于第2半导体芯片28的上表面,第2集电极电极29b设置于第2半导体芯片28的下表面。
另外,第1半导体芯片26以及第2半导体芯片28也可以是Si-MOSFET、Si-FRD(Fast Recovery Diode)、使用了SiC(碳化硅素)的SiC-IGBT、SiC-MOSFET或SiC-SBD(Schottky Barrier Diode)、或者在III-V族半导体中使用了V族元素为氮的氮化物半导体的GaN-MOSFET等。
图1中,第1半导体芯片26例如使用第3接合材料34接合在第2金属板18之上。焊丝38b设置在第1半导体芯片26以及第2金属板18之上。并且,焊丝38b将第1发射极电极27a、第1集电极电极27b或第1栅极电极27c与第2金属板18电连接。焊丝38b例如由Al(铝)形成,包含Al。
图1中,第2半导体芯片28例如使用第1接合材料30接合在第3金属板20之上。焊丝38a设置在第2半导体芯片28之上以及第3金属板20之上。并且,焊丝38a将第2发射极电极29a、第2集电极电极29b或第2栅极电极29c与第3金属板20电连接。焊丝38a例如由Al(铝)形成,包含Al。
第1接合材料30、第2接合材料32、第3接合材料34以及第4接合材料36例如是焊料。作为第1接合材料30、第2接合材料32、第3接合材料34以及第4接合材料36,能够适当使用:例如利用了Pb(铅)、Ag(银)或Sn(锡)的、组分为Pb95Sn5或Pb95Ag1.5Sn3.5等且熔点为330℃左右的焊料;利用了Sn以及Sb(锑)的、组分为SnSb类且熔点为240℃左右的焊料;利用了Au(金)和Sn的、熔点为280℃左右的AuSn类的焊料;利用了Au和Si的、熔点为360℃左右的AuSi类的焊料;或者利用了Au和Ge(锗)的、熔点为360℃左右的AuGe类的焊料。另外,第1接合材料30、第2接合材料32、第3接合材料34以及第4接合材料36并不限定于上述的焊料,例如也可以是其他烧结材料等。
半导体装置100所具有的半导体芯片的数量如上所述,是第1半导体芯片26以及第2半导体芯片28这2个。但是,半导体芯片的数量并不限定于此。例如,半导体装置100所具有的半导体芯片的数量也可以是50个以上。
壳体84例如由树脂形成,例如在基材2之上以将第1半导体芯片26以及第2半导体芯片28包围的方式设置。壳体84使用螺钉96以及垫圈98而固定在基材2之上。在壳体84内封入公知的封固材料(凝胶)86而封固。在封固材料86(凝胶)之上配置有盖88。
热界面材料(TMI:Thermal Interface Material)82设置在基材2与散热板80之间。热界面材料82例如是润滑油状的部件。热界面材料82涂敷在散热板80之上。并且,在其之上以与热界面材料82接触的状态配置基材2。热界面材料82通过填埋基材2与散热板80之间的小的间隙或凹凸,将第1半导体芯片26以及第2半导体芯片28产生的热高效地传递给散热板80。
第1端子板90的一端使用通过超声波接合法形成的第1超声波接合部50连接在第2金属板18之上。并且,第1端子板90的一端经由第1超声波接合部50而与第1半导体芯片26的第1发射极电极27a、第1集电极电极27b或第1栅极电极27c电连接。
第1端子板90具有与第1半导体芯片26对置的第1面90a。并且,第1端子板90的另一端设置于壳体84的外部。
第2端子板92的一端通过利用超声波接合法形成的第2超声波接合部52接合在第1金属板16之上。并且,第2端子板92的一端经由第2超声波接合部52而与第1半导体芯片26的第1发射极电极27a、第1集电极电极27b或第1栅极电极27c电连接。
第2端子板92设置在第1端子板90之上,具有与第1端子板90对置的第2面92a。并且,第2端子板92的另一端设置于壳体84的外部。
第3端子板94的一端使用通过超声波接合法形成的第3超声波接合部54连接在第3金属板20之上。并且,第3端子板94的一端经由第3超声波接合部54而与第2半导体芯片28的第2发射极电极29a、第2集电极电极29b或第2栅极电极29c电连接。
第3端子板94具有与第2半导体芯片28对置的第3面94a。并且,第3端子板94的另一端设置于壳体84的外部。
对第1端子板90、第2端子板92以及第3端子板94而言,例如以下工序由于能够简单地制作,所以是优选的,该工序为,通过使用板金来成型例如厚度为1mm以上且1.5mm以下左右的Cu制的板,从而被形成为一体的部件。但是,第1端子板90、第2端子板92以及第3端子板94的制造方法并不限定于此。
第1超声波接合部50中包含第1端子板90以及第2金属板18所包含的金属材料。例如,在第1端子板90以及第2金属板18由Cu形成的情况下,第1超声波接合部50中包含Cu。
第2超声波接合部52中包含第2端子板92以及第1金属板16所包含的金属材料。例如,在第2端子板92以及第1金属板16由Cu形成的情况下,第2超声波接合部52中包含Cu。
第3超声波接合部54中包含第3端子板94以及第3金属板20所包含的金属材料。例如,在第3端子板94以及第3金属板20由Cu形成的情况下,第3超声波接合部54中包含Cu。
图3是本实施方式的电力变换装置200的示意电路图。实施方式的电力变换装置200是逆变器电路。并且,实施方式的半导体装置100被用作电力变换装置200的一部分或电力变换装置200。
电力变换装置200具有相互并联连接的多个高电平侧晶体管222a、222b以及222c和相互并联连接的多个低电平侧晶体管224a、224b以及224c。并且,高电平侧晶体管222a与低电平侧晶体管224a串联连接。同样,高电平侧晶体管222b与低电平侧晶体管224b串联连接,高电平侧晶体管222c与低电平侧晶体管224c串联连接。
高电平侧晶体管222a、222b以及222c、低电平侧晶体管224a、224b以及224c例如是IGBT,但也可以是MOSFET等。另外,高电平侧晶体管222a、222b以及222c的个数和低电平侧晶体管224a、224b以及224c的个数不受特别限定。作为高电平侧晶体管222a、222b以及222c、低电平侧晶体管224a、224b以及224c,使用第1半导体芯片26或第2半导体芯片28。
高电平侧晶体管222a、222b以及222c上经由正端子P连接着直流电源210的正极212以及平滑电容器220的一端。低电平侧晶体管224a、224b以及224c上经由负端子N连接着直流电源210的负极214以及平滑电容器220的另一端。
输出端子AC(U)连接在高电平侧晶体管222a与低电平侧晶体管224a之间,输出端子AC(V)连接在高电平侧晶体管222b与低电平侧晶体管224b之间,并且输出端子AC(W)连接在高电平侧晶体管222c与低电平侧晶体管224c之间。
例如,在第1端子板90与第1半导体芯片26的第1发射极电极27a电连接、第2端子板92与第1半导体芯片26的第1集电极电极27b电连接的情况下,或者在第1端子板90与第1半导体芯片26的第1集电极电极27b电连接、第2端子板92与第1半导体芯片26的第1发射极电极27a电连接的情况下,由第1半导体芯片26变换后的电力能够使用第1端子板90以及第2端子板92而连接到设置在壳体84外的负荷等而被使用。像这样,第1端子板90以及第2端子板92起到作为输出端子AC的主端子板的功能。
此外,例如在第1端子板90与第1半导体芯片26的第1栅极电极27c电连接、第2端子板92与第1半导体芯片26的第1发射极电极27a或第1集电极电极27b电连接的情况下,第1端子板90的另一端连接于未图示的栅极驱动电路。并且,通过由栅极驱动电路生成的信号,控制第1半导体芯片26。像这样,第1端子板90可以作为信号端子发挥功能。
此外,例如在第1端子板90与第1半导体芯片26的第1发射极电极27a或第1集电极电极27b电连接、第2端子板92与第1半导体芯片26的第1栅极电极27c电连接的情况下,第2端子板92的另一端连接于未图示的栅极驱动电路。并且,通过由栅极驱动电路生成的信号,控制第1半导体芯片26。像这样,第2端子板92可以作为信号端子发挥功能。
例如,在第3端子板94与第2半导体芯片28的第2发射极电极29a或第2集电极电极29b电连接的情况下,由第2半导体芯片28变换后的电力能够使用第3端子板94连接于设置在壳体84外的负荷等而被使用。像这样,第3端子板94可以起到作为输出端子AC的主端子板的功能。
此外,例如,在第3端子板94与第2半导体芯片28的第2栅极电极29c电连接的情况下,第3端子板94的另一端连接于未图示的栅极驱动电路。并且,通过由栅极驱动电路生成的信号,控制第2半导体芯片28。像这样,第3端子板94还能够作为信号端子发挥功能。
第1粘接层60设置于第1端子板90的第1面90a。作为第1粘接层60,例如可以优选使用利用了聚酰亚胺薄膜的带材的粘接层。例如,可以使用在双面设有粘接层的利用了聚酰亚胺薄膜的带材,使用设置于一面的粘接层将带材固定到第1面90a,将设置于另一面的粘接层作为第1粘接层60来使用。但是,作为第1粘接层60并不限定于此,例如也可以对第1面90a涂敷规定的粘接剂,作为第1粘接层60来使用。
聚酰亚胺薄膜耐受后述的回流炉内的热,因此优选被使用。另外,例如也可以优选使用利用了PEEK(聚醚醚酮)材料的薄膜或利用了PTFE(聚四氟乙烯)材料的薄膜等。
第1粘接层60包含第1粘接剂。作为第1粘接剂,优选使用丙烯酸类粘接剂,但并不限定于此。第1粘接剂优选的是不包含硅氧烷。
第2粘接层62设置于第2端子板92的第2面92a。作为第2粘接层62,例如可以优选使用利用了聚酰亚胺薄膜的带材的粘接层。例如,可以使用在双面设有粘接层的利用了聚酰亚胺薄膜的带材,使用设置于一面的粘接层将带材固定到第2面92a,将设置于另一面的粘接层作为第2粘接层62来使用。但是,作为第2粘接层62并不限定于此,例如也可以对第2面92a涂敷规定的粘接剂,作为第2粘接层62来使用。
第2粘接层62包含第2粘接剂。作为第2粘接剂,优选使用丙烯酸类粘接剂,但并不限定于此。第2粘接剂优选的是不包含硅氧烷。
第3粘接层64设置于第3端子板94的第3面94a。作为第3粘接层64,例如可以优选使用利用了聚酰亚胺薄膜的带材的粘接层。例如,可以使用在双面设有粘接层的利用了聚酰亚胺薄膜的带材,使用设置于一面的粘接层将带材固定到第3面94a,将设置于另一面的粘接层作为第3粘接层64来使用。但是,作为第3粘接层64并不限定于此,例如也可以对第3面94a涂敷规定的粘接剂,作为第3粘接层64来使用。
第3粘接层64包含第3粘接剂。作为第3粘接剂,优选使用丙烯酸类粘接剂,但并不限定于此。第3粘接剂优选的是不包含硅氧烷。
在第1粘接层60、第2粘接层62以及第3粘接层64分别附着有第1金属片70、第2金属片72以及第3金属片74。第1金属片70、第2金属片72以及第3金属片74包含第1超声波接合部50、第2超声波接合部52或第3超声波接合部54所包含的金属材料。
图4是表示本实施方式的半导体装置100的制造方法的流程图。
首先,作为“黏晶(diemount)”,准备接合了第4金属板22以及第3金属板20的第1绝缘板12。接着,使用第1接合材料30接合第3金属板20与第2半导体芯片28。此外,准备接合了第5金属板24、第1金属板16以及第2金属板18的第2绝缘板14。接着,使用第3接合材料34接合第2金属板18与第1半导体芯片26。这些接合例如在公知的回流炉内进行(S10)。
接着,作为“丝焊(Wire Bonding)”,使用焊丝38a将第2半导体芯片28与第3金属板20电连接。此外,使用焊丝38b将第1半导体芯片26与第2金属板18电连接(S20)。
接着,作为“电动分选”,例如使用市面上销售的半导体测试器对第1半导体芯片26以及第2半导体芯片28的电气特性进行测试(S30)。
接着,作为“基底安装”,使用第2接合材料32将基材2的上表面与第4金属板22接合。此外,使用第4接合材料36接合基材2的上表面与第5金属板24。(S40)。
接着,作为“基板间丝焊”,使用未图示的焊丝将第1半导体芯片26与第2半导体芯片28适当电连接(S50)。
接着,作为“壳体安装”,在基材2之上,以包围第1半导体芯片26、第2半导体芯片28的方式配置壳体84。并且,例如使用螺钉96以及垫圈98将壳体84固定在基材2之上(S60)。
接着,作为“信号端子接合”,例如在第1端子板90电接合于第1半导体芯片26的第1栅极电极27c的情况下,使用超声波接合法将第1端子板90与第2金属板18接合,形成第1超声波接合部50。由此,将第1端子板90与第1半导体芯片26的第1栅极电极27c电连接(S70)。
接着,作为“鼓风”,使用市面上销售的气枪等吹附空气,由此去除通过第1端子板90与第2金属板18的接合产生的金属片。另外,此时,也可以通过一并使用市面上销售的加振器等进行加振(使其振动),来除去通过第1端子板90与第2金属板18的接合产生的金属片。此外,上述的空气吹附或加振也可以将制造中途的半导体装置的朝向翻倒(S80)。
接着,作为“主端子板1接合”(S90)和“鼓风”(S100)、“主端子板2接合”(S110)和“鼓风”(S120)、“主端子板3接合”(S130)和“鼓风”(S140),重复与“信号端子接合”(S70)以及“鼓风”(S80)相同的工艺,使用超声波接合法将第2端子板92与第1金属板16接合,形成第2超声波接合部52。此外,使用超声波接合法将第3端子板94与第3金属板20接合,形成第3超声波接合部54。
接着,作为“胶封”,用封固材料(凝胶)86对壳体84内进行封固。并且,在封固材料86之上配置盖88(S150)。由此,得到作为功率模块的半导体装置100。
以下,记载本实施方式的半导体装置的作用效果。
图5是作为本实施方式的比较方式的半导体装置800的示意截面图。半导体装置800中没有设置第1粘接层60、第2粘接层62以及第3粘接层64。
关于端子板与金属板的接合,以前通过焊料来进行。但是,在如本实施方式的半导体装置那样因流过大电流而伴随于此的发热变大的情况下,有焊料因热而溶解的情况。因此,实施了如下措施:使用超声波接合法将端子板与金属板接合,来防止焊料因热而溶解。
但是,在使用超声波接合法的情况下,由于将端子板与金属板相互擦蹭而接合,因此端子板以及金属板中包含的屑可能作为金属片而产生。不知金属片会滞留在半导体装置内的哪个部分。因此,因上述金属片而可能产生流过半导体装置的电流的泄漏、短路或绝缘不良的情况,成为问题。
此外,问题是,即使为了去除上述金属片而进行“鼓风”、“加振”、使用了水类洗涤液等洗涤液的洗净也不能很好地除去。如上所述,半导体装置内的半导体芯片的数量有时为50个以上,非常多。这是为了使半导体装置100的额定电流尽可能大。但是,如果半导体芯片的数量增加,则端子板的数量也增加,金属片卡在端子板上而变得难以除去。特别是,在如图1所示第2端子板92覆盖在第1端子板90之上那样的构造的情况下,有金属片的除去变得愈来愈困难的问题。
因此,本实施方式的半导体装置100中,在第1端子板90的与第1半导体芯片26对置的第1面90a设置第1粘接层60。此外,在第2端子板92的与第1端子板90对置的第2面92a设置第2粘接层62。进而,在第3端子板94的与第2半导体芯片28对置的第3面94a设置第3粘接层64。由此,使金属片附着于第1粘接层60、第2粘接层62以及第3粘接层64而能够抑制流过半导体装置的电流的泄露、短路或绝缘不良。由此,能够提供可靠性高的半导体装置。
丙烯酸类粘接剂具有强粘接力,因此优选作为第1粘接剂、第2粘接剂以及第3粘接剂来使用。另一方面,第1粘接剂、第2粘接剂以及第3粘接剂优选的是不包含硅氧烷。这是因为有时不能良好地进行粘接。
根据本实施方式的半导体装置,能够提供可靠性高的半导体装置。
(第2实施方式)
本实施方式的半导体装置在如下点上与第1实施方式的半导体装置不同:基体具有绝缘板、设置在绝缘板之上的金属板,半导体芯片设置在金属板之上,还具备设置在没有设置半导体芯片的金属板的部分之上且包含第3粘接剂的第3粘接层。这里,省略与第1实施方式重复的内容的记载。
图6是本实施方式的半导体装置110的示意截面图。
在没有设置第1半导体芯片26的第1金属板16的部分之上,设有包含第4粘接剂的第4粘接层65以及包含第5粘接剂的第5粘接层66。
此外,在第2绝缘板14(绝缘板的一例)之上的第2金属板18(金属板的一例)之上,设有第2半导体芯片28(半导体芯片的一例)。并且,在没有设置第2半导体芯片28的第2金属板18的部分之上,设有包含第6粘接剂(第3粘接剂的一例)的第6粘接层67(第3粘接层的一例)以及包含第7粘接剂的第7粘接层68。
通过超声波接合法产生的金属片由于进行超声波接合时的重力,与端子板一侧相比,容易向基体(金属板)一侧下落而飞散。因此,通过在没有设置半导体芯片的金属板的部分之上设置粘接层,能够使这样的金属片附着而提供可靠性高的半导体装置。
对本发明的几个实施方式以及实施例进行了说明,但这些实施方式以及实施例是作为例子来提示的,并没有要限定发明的范围。这些新的实施方式能够以其他多种方式实施,在不脱离发明的主旨的范围内能够进行各种省略、置换、变更。这些实施方式及其变形包含在发明的范围及主旨中,并且包含在权利要求书中记载的发明及其等价的范围中。
Claims (8)
1.一种半导体装置,其中,具备:
基体;
半导体芯片,设置在上述基体之上;
第1端子板,经由设置在上述基体之上的第1超声波接合部与上述半导体芯片电连接,具有与上述半导体芯片对置的第1面;以及
第1粘接层,设置于上述第1面,包含第1粘接剂。
2.如权利要求1所述的半导体装置,其中,
还具备:
第2端子板,经由设置在上述基体之上的第2超声波接合部与上述半导体芯片电连接,设置于上述第1端子板之上,具有与上述第1端子板对置的第2面;以及
第2粘接层,设置于上述第2面,包含第2粘接剂。
3.如权利要求2所述的半导体装置,其中,
上述半导体芯片具有第1电极、第2电极以及第1控制电极;
上述第1端子板电连接于上述第1电极;
上述第2端子板电连接于上述第2电极。
4.如权利要求2所述的半导体装置,其中,
上述半导体芯片具有第1电极、第2电极以及第1控制电极;
上述第1端子板电连接于上述第1控制电极;
上述第2端子板电连接于上述第1电极或上述第2电极。
5.如权利要求1至4中任一项所述的半导体装置,其中,
在上述第1粘接层附着有金属片,该金属片包含上述第1超声波接合部所包含的金属材料。
6.如权利要求1至4中任一项所述的半导体装置,其中,
上述第1粘接剂包含丙烯酸类粘接剂。
7.如权利要求1至4中任一项所述的半导体装置,其中,
上述第1粘接剂不包含硅氧烷。
8.如权利要求1至4中任一项所述的半导体装置,其中,
上述基体具有绝缘板和设置在上述绝缘板之上的金属板;
上述半导体芯片设置在上述金属板之上;
上述半导体装置还具备包含第3粘接剂的第3粘接层,该第3粘接层设置在没有设置上述半导体芯片的上述金属板的部分之上。
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Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002151644A (ja) * | 2000-09-04 | 2002-05-24 | Fujitsu Ltd | 積層型半導体装置及びその製造方法 |
JP2003037260A (ja) * | 2001-07-25 | 2003-02-07 | Toppan Printing Co Ltd | 固体撮像装置 |
CN101261966A (zh) * | 2007-03-08 | 2008-09-10 | 富士电机电子设备技术株式会社 | 半导体装置及其制造方法 |
JP2009081289A (ja) * | 2007-09-26 | 2009-04-16 | Denso Corp | 半導体装置、その固定構造、及びその異物除去方法 |
CN103021979A (zh) * | 2011-09-21 | 2013-04-03 | 株式会社东芝 | 半导体装置 |
JP2013089784A (ja) * | 2011-10-19 | 2013-05-13 | Hitachi Ltd | 半導体装置 |
JP2014183157A (ja) * | 2013-03-19 | 2014-09-29 | Mitsubishi Electric Corp | 電力用半導体装置および電力用半導体装置の製造方法 |
CN105684147A (zh) * | 2014-04-30 | 2016-06-15 | 富士电机株式会社 | 半导体模块及其制造方法 |
CN109478521A (zh) * | 2016-07-26 | 2019-03-15 | 三菱电机株式会社 | 半导体装置 |
KR20190095998A (ko) * | 2018-02-08 | 2019-08-19 | 현대모비스 주식회사 | 전력용 반도체 모듈 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62156896A (ja) | 1985-12-28 | 1987-07-11 | 電気化学工業株式会社 | 大電流用回路基板の製造法 |
EP0661748A1 (en) * | 1993-12-28 | 1995-07-05 | Hitachi, Ltd. | Semiconductor device |
US6060772A (en) * | 1997-06-30 | 2000-05-09 | Kabushiki Kaisha Toshiba | Power semiconductor module with a plurality of semiconductor chips |
JP3445511B2 (ja) * | 1998-12-10 | 2003-09-08 | 株式会社東芝 | 絶縁基板、その製造方法およびそれを用いた半導体装置 |
JP3958156B2 (ja) * | 2002-08-30 | 2007-08-15 | 三菱電機株式会社 | 電力用半導体装置 |
EP1667508B1 (en) * | 2003-09-25 | 2012-07-11 | Kabushiki Kaisha Toshiba | Ceramic circuit board, method for making the same, and power module |
JP4371151B2 (ja) | 2007-05-28 | 2009-11-25 | 日立金属株式会社 | 半導体パワーモジュール |
US8154114B2 (en) * | 2007-08-06 | 2012-04-10 | Infineon Technologies Ag | Power semiconductor module |
US8018047B2 (en) * | 2007-08-06 | 2011-09-13 | Infineon Technologies Ag | Power semiconductor module including a multilayer substrate |
JP2010040615A (ja) * | 2008-08-01 | 2010-02-18 | Hitachi Ltd | 半導体装置 |
JP2010177608A (ja) * | 2009-02-02 | 2010-08-12 | Suzuka Fuji Xerox Co Ltd | 半導体装置の製造方法 |
JP5602095B2 (ja) * | 2011-06-09 | 2014-10-08 | 三菱電機株式会社 | 半導体装置 |
JP2013051366A (ja) * | 2011-08-31 | 2013-03-14 | Hitachi Ltd | パワーモジュール及びその製造方法 |
US9085685B2 (en) * | 2011-11-28 | 2015-07-21 | Nitto Denko Corporation | Under-fill material and method for producing semiconductor device |
JP6104407B2 (ja) * | 2013-12-04 | 2017-03-29 | 三菱電機株式会社 | 半導体装置 |
JP2015142045A (ja) * | 2014-01-29 | 2015-08-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
CN105934824B (zh) * | 2014-03-06 | 2018-06-15 | 三菱电机株式会社 | 电力用半导体装置 |
JP6293030B2 (ja) * | 2014-10-09 | 2018-03-14 | 三菱電機株式会社 | 電力用半導体装置 |
DE102014115847B4 (de) * | 2014-10-30 | 2018-03-08 | Infineon Technologies Ag | Verfahren zur Herstellung eines Leistungshalbleitermoduls |
JP2017041615A (ja) * | 2015-08-21 | 2017-02-23 | 株式会社フジクラ | 光学素子モジュール、光学素子モジュールの製造方法 |
JP6760127B2 (ja) * | 2017-02-24 | 2020-09-23 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法 |
JP6852011B2 (ja) * | 2018-03-21 | 2021-03-31 | 株式会社東芝 | 半導体装置 |
-
2019
- 2019-09-05 JP JP2019161843A patent/JP7346178B2/ja active Active
-
2020
- 2020-01-21 CN CN202010069971.7A patent/CN112447699A/zh active Pending
- 2020-01-29 US US16/775,423 patent/US11264348B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002151644A (ja) * | 2000-09-04 | 2002-05-24 | Fujitsu Ltd | 積層型半導体装置及びその製造方法 |
JP2003037260A (ja) * | 2001-07-25 | 2003-02-07 | Toppan Printing Co Ltd | 固体撮像装置 |
CN101261966A (zh) * | 2007-03-08 | 2008-09-10 | 富士电机电子设备技术株式会社 | 半导体装置及其制造方法 |
JP2009081289A (ja) * | 2007-09-26 | 2009-04-16 | Denso Corp | 半導体装置、その固定構造、及びその異物除去方法 |
CN103021979A (zh) * | 2011-09-21 | 2013-04-03 | 株式会社东芝 | 半导体装置 |
JP2013089784A (ja) * | 2011-10-19 | 2013-05-13 | Hitachi Ltd | 半導体装置 |
JP2014183157A (ja) * | 2013-03-19 | 2014-09-29 | Mitsubishi Electric Corp | 電力用半導体装置および電力用半導体装置の製造方法 |
CN105684147A (zh) * | 2014-04-30 | 2016-06-15 | 富士电机株式会社 | 半导体模块及其制造方法 |
CN109478521A (zh) * | 2016-07-26 | 2019-03-15 | 三菱电机株式会社 | 半导体装置 |
KR20190095998A (ko) * | 2018-02-08 | 2019-08-19 | 현대모비스 주식회사 | 전력용 반도체 모듈 |
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US20210074666A1 (en) | 2021-03-11 |
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