CN1124408A - 一种用于半导体器件的表面耐压区 - Google Patents

一种用于半导体器件的表面耐压区 Download PDF

Info

Publication number
CN1124408A
CN1124408A CN95108317A CN95108317A CN1124408A CN 1124408 A CN1124408 A CN 1124408A CN 95108317 A CN95108317 A CN 95108317A CN 95108317 A CN95108317 A CN 95108317A CN 1124408 A CN1124408 A CN 1124408A
Authority
CN
China
Prior art keywords
withstand voltage
voltage zone
surface withstand
impurity
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN95108317A
Other languages
English (en)
Other versions
CN1040814C (zh
Inventor
陈星弼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN 94111842 external-priority patent/CN1115909A/zh
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN95108317A priority Critical patent/CN1040814C/zh
Priority to US08/504,384 priority patent/US5726469A/en
Publication of CN1124408A publication Critical patent/CN1124408A/zh
Application granted granted Critical
Publication of CN1040814C publication Critical patent/CN1040814C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)

Abstract

一种用于半导体器件的表面耐压区，它位于第一种导电类型的衬底(1)之上形成的第二种导电类型(2)的中心部分周围，该耐压区的平均有效第二种导电类型的杂质密度随离开所述第二种导电类型(2)的中心部分的距离的增加而逐渐或阶梯式减少。此种表面耐压区可使n+-p-(或P+或n-)结的击穿电压达到用同样衬底所做成的平行平面单边突变结的击穿电压的90％，利用本发明可制作反应速度快、导通电压低、电流密度大的高压纵向器件及高压横向器件。

Description

一种用于半导体器件的表面耐压区
本发明涉及半导体高压器件及功率器件技术，特别是涉及一种用于半导体器件的表面耐压区。
众所周知，平面(planar)n+—p-(或p+—n-)结的击穿电压常受限于表面击穿。这里利用图1所示的n+—p结剖面，对此现象作一简单解释。
图中1为第一种导电类型区，如p-(或n-)型衬底，2为形成在第一种导电类型衬底上的第二种导电类型区，如n+(或p+)型区，当n+—p(或P+—n-)结加上反向偏压后，沿中间线只有纵向电场，其值在n+—p(或p-—n-)冶金结面最高，其沿线积分等于反向偏压。沿p(或n)区表面有一横向电场，其沿表面的积分也等于反向偏压。由于曲率效应，在n+(或p+)区表面附近的电场分布很不均匀，在n+(或p+)区附近有特别高的电场。此高电场使碰撞电离击穿电压远低于同衬底的单边突变平行平面结的碰撞电离击穿电压。
为了提高表面击穿电压，已有不少的有关技术可以利用。这种技术称为平面结终端技术，关于平面结终端技术可参考文献：B.J.Bali-ga.IEE Proc，Vol 129.pt I.No.5pp.173—179(1982)。在各种平面结终端技术中，可能使击穿电压达到同衬底的平行平面突变结90％的，只有结终端扩展(JTE)、可变表面掺杂(VLD)及电阻场板(RFP)。而结终端扩展不可能在最短的表面距离内达到最大的击穿电压；可变表面掺杂需采用结较深的扩散，且其制造方法与现代亚微米工艺不兼容；电阻场板则需要增加复杂的电阻膜制作，使工艺复杂，成本提高。此外，即使采用这三种技术，也不可能使表面耐压区同时成为横向器件中导通电阻较小的漂移区。
横向器件中为提高击穿电压和降低导通电阻，有偏置栅(offset-gate)及RESURF两种技术，见文献S.Ochi，et al.，IEEE Trans.Electron Devices Vol.ED—27 p.399(1980)；E.J.Wildi，et.al.，IEDM Digest p.268(1982)。但这两种技术一般都需要专门的离子注入工艺才能达到较好的效果，从而增加了工艺的复杂性。而且即使那样，也不能达到在同样击穿电压下提供比本发明具有更低的导通电阻(对MOS器件)及基极电阻(对双极型器件)的效果。
本发明的目的在于提供一种新的表面耐压区及其制作方法。利用本发明，可在一定电阻率的衬底上以最短的表面距离实现最高的击穿电压。此表面耐压区的结构使得在制作方法上有许多灵活性，便于和现代亚微米工艺兼容，基于此种灵活性使得BiCMOS工艺及CMOS工艺兼容的高压集成电路与功率集成电路能以更低的成本和更高的性能实现。
本发明是根据发明者关于最佳可变表面掺杂的理论构想而来的，见文献X.B.Chen等，Solid—State Eleetronics，Vol.35，pp.1365—1370(1992)(本发明受到中国国家自然科学基金资助)。
为了实现上述目的，本发明提供了一种半导体器件的表面耐压区，所述表面耐压区位于在第一种导电类型的衬底之上形成的第二种导电类型区的中心部分的周围，其中，该表面耐压区的第二种导电类型杂质的有效密度随着离开所述第二种导电类型区的中心部分的距离的增加而从约为NBWpp之值逐渐或阶梯式减少，这里NB是衬底掺杂浓度，Wpp指由该衬底构成的单边突变平行平面结在击穿电压下的耗尽层厚度，而所述杂质密度是指在第二种导电类型区的中心部分与第一种导电类型的衬底之间外加反向电压近于反向击穿电压而使表面耐压区全部耗尽的情况下，在横向尺寸远小于Wpp且大于该表面耐压区的厚度的面积内的第二种导电类型的电离杂质原子的总数减去第一种导电类型的电离杂质原子总数的差值除以所述面积所得的值。
本发明还提供了一种半导体器件的表面耐压区，其中此区中的掺杂密度的变化是通过既用第二种导电类型的杂质又再用第一种导电类型的杂质进行补偿的方法而得到的。
本发明还提供了利用此种补偿方法的下述结构的表面耐压区：
所述补偿掺杂的第一种导电类型杂质的掺杂密度在所述表面耐压区上层的多个连续的区域内随着离开所述第二种导电类型区的中心部分的距离的增加而阶梯式增加；
所述第一种导电类型杂质补偿掺杂的多个连续区域中，至少有一个由多个互相分隔开的小区构成；
所述补偿掺杂的第一种导电类型杂质杂在所述表面耐压区上层沿表面水平方向上的锯齿形区域内；
所述补偿掺杂的第一种导电类型杂质沿垂直方向至少分为互相隔开的两层掺于所述第二种导电类型的表面耐压区内。
上述第一种导电类型区中的杂质离子形成对第二种导电类型杂质离子的杂质补偿，本发明中此种杂质补偿是指当表面耐压区在击穿电压下为全耗尽时，反型杂质对峰值电场的抵偿作用。例如，表面耐压区中某处上层为p型，下层为n型，则受主对峰值电场的作用几乎全为其下层的施主的一部分所抵偿。
在现代亚微米技术中，上述第一种导电类型杂质的补偿区的宽度及相邻区的横向距离可做到小于3微米，半导体耐压层通常为1微米左右，而由同衬底构成的单边平行平面突变结在击穿电压下的耗尽层厚度约为20微米，因此本发明提供的表面耐压区结构易于用离子注入借助于适当的掩模而形成，使高压器件与亚微米工艺兼容具有可行性。
显然，如在第一种导电类型衬底与第二种导电类型区以及上述表面耐压区之间增加一层薄的绝缘层，只要衬底与表面耐压区的外边缘互相电连接，则电场分布并不会有重大变化。换言之，本发明也可用于半导体—绝缘体—半导体(SIS，如绝缘体为氧化层则为SOS)上以获得高压横向器件。
下面结合附图说明本发明。
图1为一般的n+—p(或p+—n)平面结构；
图2为本发明的表面耐压区中掺杂分布的示意剖面图；
图3是表面耐压区包括三段掺杂密度不同的连续区域的示意剖面图；
图4是表面耐压区包括二段掺杂密度不同的区域以及位于二段掺杂密度不同的区域之间的多个杂质密度相同的互相隔开的小区的示意剖面图；
图5是表面耐压区包括许多互相分隔开的杂质密度相同的小区的示意剖面图；
图6是表面耐压区为沿表面水平方向上的锯齿形区域有补偿杂质区的示意俯视图；
图7是表面耐压区包括沿垂直方向的多层补偿杂质区的示意剖面图；
图8是在表面耐压区与衬底之间有薄氧化层的结构的剖面示意图；
图9是表面耐压区利用互相分隔开而占空比随离开中心部分距离变化的小区以达到平均杂质密度连续变化的结构的剖面示意图。
图10是利用图3的表面耐压区构成的高压晶体管的示意剖面图；
图11是利用图3的表面耐压区构成的高压JFET的示意剖面图；
图12是利用图7的表面耐压区构成的高压MOST的示意剖面图；
图13是利用图3的表面耐压区构成的高压IGBT的示意剖面图。
现在结合图2说明本发明的表面耐压区能提高耐压的原理。图2中，1为第一种导电类型(如为p-型)的衬底，2为重掺杂的第二种导电类型(如为n+型)的区域，3、4和5分别为掺杂密度与区2不同的第二种导电类型的区域。为了提高平面结的击穿电压，使上述3、4和5区中的掺杂密度从3区逐渐或阶梯式地降低至5区。在外加反向偏压接近于平面结的击穿电压而使3、4和5区耗尽时，由于3区的掺杂密度约为NBWpp，故在其全耗尽时，其中电离施主(或受主)产生的附加电场在2、3区的交界处与2区产生的电场方向相反，从而使2区边缘处的电场大大下降。同理，3区在与4区交界处的电场由于4区的存在而比无4区存在时小了很多；4区在4、5区边界处的电场亦由于5区的存在而比无5区时小了许多。5区本身是掺杂密度很低的区域，加之外加偏压在表面大部分已被从2区边缘到5区的外边缘所吸收。在5区外边缘与衬底1之间只存在较小的电位差，所以，5区的边缘只有较弱的电场。因此，图2所示的结构就可以使平面结的击穿电压达到或超过理想平行平面结的90％。而且，在优化设计中，图2所示结构的表面耗尽区所占的距离仅为理想平行平面结的最大耗尽层厚度的1.8倍左右。由此可见，本发明的表面耐压区结构可在最短的水平距离内达到最高的击穿电压。
为了实现使表面耐压区的掺杂密度随着离开2区的中心部分的距离的增加而减少的设计思想，除了利用扩散、离子注入等方法分别直接得到掺杂密度阶梯式降低的3、4和5区的方法外，还可以通过先在衬底1上得到一个掺杂类型与衬底相反的高掺杂的2区，然后再用与衬底掺杂类型相同的杂质进行补偿的方法得到。
图3所示即为按上述方法得到的表面耐压区结构。图中，1为p-型衬底，2为n+掺杂区，6、7和8区是用p型杂质按依次增加的密度掺杂得到的区域。当2区中心部分与衬底1之间加上足够高的反向偏压后，6、7和8区以及其下部的那部分2区中的杂质离子将全部电离。6、7和8区之下的2区中的电离施主产生的一部分电力线立即终止于其上部的6、7、8区中的电离受主，其剩余部分的电力线密度相当于图2中3、4和5区的电力线密度。也就是说，用上述这种杂质补偿的方法得到的结构对沿2区与衬底1的冶金结面的总电场产生的作用与图2所示的3、4和5区所产生的作用相同。
图3中的9是一个与衬底1掺杂类型相同的纯p区，它与衬底1直接相连，使得外加偏压可直接加在2区中心部分和9区之上，而不是加在2区中心部分与衬底1的下端面上。
图4所示为图3所示结构的一种变型。在图4所示的结构中用多个互相隔开的小的8区来代替图3中的7区。通过适当选择这些小8区的占空比可使其平均受主密度与图3中的7区一致，甚至可使平均受主密度逐渐由6区增加至8区的值。由于小8区的掺杂密度和8区相同，故可以减少产生7区的工艺步骤，从而降低成本。
图4中还示出了一个重掺杂埋层区10，其作用是使9区与衬底1之间达到更好的电接触。
图5所示为另一种结构的表面耐压区的剖面图。在此结构中，用多个互相隔开的小8区来补偿2区中的掺杂，使表面耐压区中的杂质密度随着离2区中心部分的距离的增加而减少。通过适当选择这些小区的占空比随距离的变化，只有一种掺杂密度就可以实现表面耐压区杂质密度的逐渐变化。这种结构可省去产生6区及7区的两个工艺步骤，从而降低成本。
图6为另一种同用一种掺杂密度的区域实现表面有效掺杂密度随距离变化的结构的平面俯视图。将补偿掺杂用的第一种导电类型(如p型)的杂质掺在表面耐压区上层的锯齿形区域内，如此得到的结构可使平均受主密度随着离开2区的中心部分的距离的增加而逐渐增加。从而使有效施主的平均密度随离开2区中心部分的距离的增加而逐渐减少。
图中的9为与衬底相连的纯p区，其上的黑色区域为金属电极。
图7所示为本发明表面耐压区的又一种变型。在这种结构中，补偿掺杂用的第一种导电类型(如p型)的杂质是沿垂直方向分层掺杂于第二种导电类型的n区2内的。随着离开2区的中心部分的距离的增加，用于补偿2区施主密度的受主杂质层从一个6区增加到三个长度不同的6区。用这种方法同样可以使有效施主的平均密度随着离开2区中心部分的距离的增加而逐渐减少。
由上述结合附图3—7的说明可知，本发明的表面耐压区不仅能以最短的表面耐压区横向距离实现最高击穿电压，而且实施的工艺也可以有很大的灵活性。如果有三种产生适合于6、7、8区的掺杂密度的工艺，则可用图3所示的结构。如果有两种适合6和8区的掺杂密度的工艺，则可用图4所示的结构。如果只有一种能产生适合8区的掺杂密度的工艺，就可用图5和6所示的结构。如果只有一种适合于得到6区掺杂密度的工艺但可多次进行，则在2区的厚度足够厚时可以采用图7所示的结构。
图8所示为在衬底1和表面耐压区之间设置有一个薄的绝缘层15的结构。这种结构可用于SIS(如果用氧化层作为绝缘层则为SOS)结构的半导体器件。
图9为本发明表面耐压区的另一种结构。这种结构不使用衬偿掺杂工艺。通过在第一种导电类型的衬底上直接掺以第二种导电类型的杂质以形成多个互相隔开的掺杂密度相同的小区，使这些小区的占空比随着离开中心部分距离的增加而减少，就可达到使第二种导电类型杂质的平均掺杂密度随距离变化的要求。
在图3—图9的例子中，本发明的表面耐压区至少有三段平均施主(或受主)密度不同的区域，击穿电压可达到同衬底的平行平面结的90％以上。而常规的RESURF技术相当于只有一段恒定掺杂密度的区域，因此击穿电压远低于本发明的效果。
在图3—图9的例子中，表面耐压区均是在杂质密度均匀的n型掺杂区上加入不同的p型掺杂区。本领域的普通技术人员均可知道，如表面耐压区是密度不同的n型区，其上有均匀的p区，也可以得到有效施主密度随距离变化的效果。甚至可以在表面耐压区中既采用不同密度的p区也采用不同密度的n区，也可达到同样的效果。
以上的描述中设衬底1为p-型，2区为n+型掺杂。本领域的普通技术人员均可知道，当衬底1为n-型、2区为p+型掺杂时，本发明的构思是一样适用的。
下面再利用上述表面耐压区，通过制作器件的实施例进一步说明本发明。
实施例1：利用本发明的表面耐压区制作二极管。这只需要将附图3—图7中电极+(-)做成阳(阴)极，电极-(+)做成阴(阳)极。为了得到较好的欧姆接触，可在金属电极下另做导电类型与接触区相同的重掺区。这种重掺区在本发明各附图中均省略而未画出。
实施例2：利用本发明的表面耐压区来制作晶体管。这只需在图3—附图7的2区中央再做一个导电类型与2区相反的p+(或n+)区作发射区E，2区作为基区B，9区与衬底相连作为集电区C。
如附图10所示的是利用附图3的表面耐压区作高压晶体管的一例。
实施例3：利用本发明的表面耐压区来制作JFET。这只需将附图3—附图6的2区中央作为漏D，将表面耐压区外的2区作为源S，在表面耐压区的末端的8区上做一个p+型11区作为栅G。源与衬底相连。
如图11示出了利用附图3的表面耐压区作高压JFET的一例。
实施例4：利用本发明的表面耐压区来制作横向MOST。这只需将附图3—附图7的2区的中心部分作为漏D，在表面耐压区外部设置一小段无补偿掺杂的区，在这一小段之外设置一个纯为第一种导电类型的9区，其中又有一个与2区导电类型相同的重掺杂区13作为源S，在上述小段无补偿掺杂的2区与13区的交界部分之上形成一个薄氧化层12，其上覆盖金属作为栅G，即可得到用本发明的表面耐压区制作的横向MOST。
图12示出利用附图7的表面耐压区作高压横向MOST的例子。
发明者对图3的表面耐压区用一个0.8微米BiCMOS工艺作横向MOST的情形作了模拟。发现其导通电阻很低、反应速度快、电流密度大。其优值
Figure A9510831700111
为一般横向器件的250倍，如采用图7的表面耐压区，则导通电阻可以进一步降低。这是因为在导通时6区与2区大部分未耗尽。
实施例5：利用本发明的表面耐压区制作高压IGBT。这和制造横向MOST的区别是在2区中央顶部做一个导电类型与2区相反的重掺杂区14，该区是阴极K(或阳极)A)，横向MOST的源在这里是阳极A(或阴极K)。
图13所示为利用本发明的表面耐压区制作高压IGBT的实施例。
其工艺步骤举例如下：
1)利用掩模在杂质浓度为1×1515厘米-3的衬底上形成一个窗口，再离子注入硼(其剂量约为4·1012厘米-2)作为埋层区10；2)在整个衬底上外延一层轻掺杂的n区，其厚度约为1微米；3)利用掩模作磷离子注入以形成2区，其剂量约为3×1012厘米-2，n型杂质分布在经过整个工艺过程后为高斯型，峰值在深度为0.8微米处，半宽为0.4微米；4)利用掩模作硼离子注入以形成8区和9区，其剂量约为2×1012厘米-2，其p型杂质的分布在经过整个工艺过程后的峰值在表面附近，半宽为0.4微米；5)利用掩模对6区及9区作硼离子注入，其剂量约为1×1012厘米-2；6)利用掩模对7区作硼离子注入，其剂量约为1.5×1012厘米2；再经过本领域的常规工艺即可制成高压IGBT。在上述方法中，9区的形成利用了4)和5)两步工艺，再加上埋层10区的扩散，故9区为一个纯p型区。
虽然上述实施例均系结合横向器件所作了说明，本领域的普通技术人员均应理解，本发明的表面耐压区同样适用于纵向器件。
发明者还对叉指(interdigital)图形的器件在指端(Ends offingers)的击穿电压利用圆柱坐标作了研究。发现只要改变各区的相对长度或各小区的占空比而维特表面耐压区总长度不变，仍可达到上述耐压值。但指端不宜作为器件的有源区。
综上所述，本发明的优点是(1)提供了半导体器件高耐压的表面区和制造方法；(2)在工艺上与现代亚微米集成电路工艺兼容；(3)制作出的器件的导通电阻(对FET型管)或基极电阻(对晶体管)低。利用本发明不仅可制作分立器件，而且能以高性能、低成本实现高压集成电路及功率集成电路。

Claims (10)

1.一种用于半导体器件的表面耐压区，所述半导体器件是以第一种导电类型的衬底及其上形成的第二种导电类型重掺杂区为基础的，所述表面耐压区的特征在于：
当所述表面耐压区在所述衬底和所述重掺杂区之间所加电压接近反向击穿电压而全部耗尽时，该表面耐压区中第二种导电类型的电离杂质的有效平均密度随着离开重掺杂区中心的距离的增加从约为NB*Wpp逐渐或阶梯式地下降，这里，NB代表衬底的杂质浓度，Wpp代表由该衬底形成的单边突变平行平面结在其击穿电压下的耗尽层厚度，平均密度系指在一个表面横向尺寸远小于Wpp而又大于该表面耐压区厚度的面积内有效的第二种导电类型杂质总数除以该面积所得的值。
2.如权利要求1所述的表面耐压区，其特征在于：所述表面耐压区中第二种导电类型杂质随离开所述第二种导电类型区的中心部分的距离的增加而减少的平均密度是通过既用第二种导电类型的杂质进行掺杂，又用第一种导电类型的杂质进行补偿的方法而得到，其中，所述表面耐压区与衬底相邻的区域为第二种杂质类型区。
3.如权利要求2所述的表面耐压区，其特征在于：所述表面耐压区中第二种导电类型区的杂质密度为常数，而其上的第一种导电类型杂质在多个连续的区域内随着离开所述第二种导电类型区的中心部分的距离的增加而阶梯式增加。
4.如权利要求3所述的表面耐压区，其特征在于：所述多个连续的第一种导电类型杂质区域中至少有一个是由多个互相分隔开的小区构成的。
5.如权利要求2所述的表面耐压区，其特征在于：所述补偿杂质的第一种导电类型杂质是掺在所述表面耐压区上层的沿表面水平方向上的锯齿形区域内。
6.如权利要求2所述的表面耐压区，其特征在于：至少有两层以上的、具有不同长度的所述补偿杂质的第一种导电类型层沿垂直方向插入在所述第二种导电类型区之内。
7.如权利要求1—7所述的表面耐压区，其特征在于：在所述第一种导电类型的衬底与所述第二种导电类型的表面耐压区之间设置有一个薄的绝缘层。
8.如权利要示1所述的表面耐压区，其特征在于：包括多个具有同样的第二种导电类型杂质密度的掺杂小区，且这些区互相隔开。
9.用权利要求1—7所述的表面耐压区制造的半导体器件。
10.用权利要求8所述的表面耐压区制造的半导体器件。
CN95108317A 1994-07-20 1995-07-06 一种用于半导体器件的表面耐压区 Expired - Lifetime CN1040814C (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN95108317A CN1040814C (zh) 1994-07-20 1995-07-06 一种用于半导体器件的表面耐压区
US08/504,384 US5726469A (en) 1994-07-20 1995-07-19 Surface voltage sustaining structure for semiconductor devices

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN 94111842 CN1115909A (zh) 1994-07-20 1994-07-20 一种提供高压器件高耐压的表面区结构
CN94111842.8 1994-07-20
CN95108317A CN1040814C (zh) 1994-07-20 1995-07-06 一种用于半导体器件的表面耐压区

Publications (2)

Publication Number Publication Date
CN1124408A true CN1124408A (zh) 1996-06-12
CN1040814C CN1040814C (zh) 1998-11-18

Family

ID=25743467

Family Applications (1)

Application Number Title Priority Date Filing Date
CN95108317A Expired - Lifetime CN1040814C (zh) 1994-07-20 1995-07-06 一种用于半导体器件的表面耐压区

Country Status (2)

Country Link
US (1) US5726469A (zh)
CN (1) CN1040814C (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100576541C (zh) * 2008-05-14 2009-12-30 电子科技大学 一种半导体器件及其提供的低压电源的应用
CN102969356A (zh) * 2012-11-08 2013-03-13 电子科技大学 一种超结功率器件终端结构
US8460977B2 (en) 2008-08-11 2013-06-11 Cree, Inc. Mesa termination structures for power semiconductor devices and methods of forming power semiconductor devices with mesa termination structures
CN103280457A (zh) * 2013-05-14 2013-09-04 电子科技大学 一种超低比导通电阻的横向高压功率器件及制造方法
CN103413831A (zh) * 2013-08-30 2013-11-27 电子科技大学 一种横向高压器件及其制造方法
CN103413830A (zh) * 2013-08-16 2013-11-27 电子科技大学 一种横向高压mosfet及其制造方法
CN101981700B (zh) * 2008-02-26 2014-05-14 克里公司 用于碳化硅器件的双保护环边缘终端和制造具有双保护环边缘终端的碳化硅器件的方法
CN110379861A (zh) * 2019-08-12 2019-10-25 派恩杰半导体（杭州）有限公司 一种碳化硅异质结二极管功率器件
CN113690233A (zh) * 2021-09-22 2021-11-23 成都吉莱芯科技有限公司 一种可增强通流能力的单向esd保护器件及其制作方法

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59707158D1 (de) * 1996-02-05 2002-06-06 Infineon Technologies Ag Durch feldeffekt steuerbares halbleiterbauelement
US6207994B1 (en) * 1996-11-05 2001-03-27 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
US6168983B1 (en) * 1996-11-05 2001-01-02 Power Integrations, Inc. Method of making a high-voltage transistor with multiple lateral conduction layers
CN1099715C (zh) * 1998-07-23 2003-01-22 电子科技大学 一种用于有浮动电压端的半导体器件的表面耐压层
DE19840032C1 (de) * 1998-09-02 1999-11-18 Siemens Ag Halbleiterbauelement und Herstellungsverfahren dazu
WO2000035020A1 (de) * 1998-12-07 2000-06-15 Infineon Technologies Ag Laterales hochvolt-halbleiterbaulement mit reduziertem spezifischem einschaltwiderstand
DE19923466B4 (de) 1999-05-21 2005-09-29 Infineon Technologies Ag Junctionsisolierter Lateral-MOSFET für High-/Low-Side-Schalter
DE19947020B4 (de) * 1999-09-30 2006-02-23 Infineon Technologies Ag Kompensationsbauelement mit variabler Ladungsbilanz und dessen Herstellungsverfahren
US7786533B2 (en) * 2001-09-07 2010-08-31 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
US6635544B2 (en) 2001-09-07 2003-10-21 Power Intergrations, Inc. Method of fabricating a high-voltage transistor with a multi-layered extended drain structure
CN1189945C (zh) * 2002-08-29 2005-02-16 电子科技大学 用高介电系数膜的表面(横向)耐压结构
CN1311560C (zh) * 2003-10-16 2007-04-18 电子科技大学 横向低侧高压器件及高侧高压器件
US20090026586A1 (en) * 2005-04-22 2009-01-29 Icemos Technology Corporation Superjunction Device Having Oxide Lined Trenches and Method for Manufacturing a Superjunction Device Having Oxide Lined Trenches
US20060255401A1 (en) * 2005-05-11 2006-11-16 Yang Robert K Increasing breakdown voltage in semiconductor devices with vertical series capacitive structures
US20070012983A1 (en) * 2005-07-15 2007-01-18 Yang Robert K Terminations for semiconductor devices with floating vertical series capacitive structures
US7446018B2 (en) * 2005-08-22 2008-11-04 Icemos Technology Corporation Bonded-wafer superjunction semiconductor device
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US7728402B2 (en) * 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
CN101501859B (zh) * 2006-08-17 2011-05-25 克里公司 高功率绝缘栅双极晶体管
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
US7723172B2 (en) * 2007-04-23 2010-05-25 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US8580651B2 (en) * 2007-04-23 2013-11-12 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US20080272429A1 (en) * 2007-05-04 2008-11-06 Icemos Technology Corporation Superjunction devices having narrow surface layout of terminal structures and methods of manufacturing the devices
JP4375439B2 (ja) 2007-05-30 2009-12-02 株式会社デンソー ジャンクションバリアショットキーダイオードを備えた炭化珪素半導体装置
CN101868856B (zh) 2007-09-21 2014-03-12 飞兆半导体公司 用于功率器件的超结结构及制造方法
US8012806B2 (en) 2007-09-28 2011-09-06 Icemos Technology Ltd. Multi-directional trenching of a die in manufacturing superjunction devices
US7846821B2 (en) * 2008-02-13 2010-12-07 Icemos Technology Ltd. Multi-angle rotation for ion implantation of trenches in superjunction devices
US8030133B2 (en) * 2008-03-28 2011-10-04 Icemos Technology Ltd. Method of fabricating a bonded wafer substrate for use in MEMS structures
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
US8106487B2 (en) 2008-12-23 2012-01-31 Pratt & Whitney Rocketdyne, Inc. Semiconductor device having an inorganic coating layer applied over a junction termination extension
CN101494239B (zh) * 2009-02-27 2010-12-01 电子科技大学 一种高速igbt
CN101510549B (zh) * 2009-03-31 2010-12-01 电子科技大学 一种半导体横向器件
CN101521203B (zh) 2009-04-07 2010-08-04 电子科技大学 一种半导体横向器件和高压器件
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8637386B2 (en) 2009-05-12 2014-01-28 Cree, Inc. Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8629509B2 (en) * 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8541787B2 (en) * 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US8803277B2 (en) 2011-02-10 2014-08-12 Cree, Inc. Junction termination structures including guard ring extensions and methods of fabricating electronic devices incorporating same
CN102651392B (zh) 2011-02-28 2014-11-05 成都成电知力微电子设计有限公司 一种控制两种载流子的晶闸管
US9318623B2 (en) 2011-04-05 2016-04-19 Cree, Inc. Recessed termination structures and methods of fabricating electronic devices including recessed termination structures
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
EP2754177A1 (en) 2011-09-11 2014-07-16 Cree, Inc. High current density power module comprising transistors with improved layout
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US8946814B2 (en) 2012-04-05 2015-02-03 Icemos Technology Ltd. Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates
US9660053B2 (en) 2013-07-12 2017-05-23 Power Integrations, Inc. High-voltage field-effect transistor having multiple implanted layers
WO2016043247A1 (ja) * 2014-09-17 2016-03-24 富士電機株式会社 半導体装置
US9768274B2 (en) 2014-11-25 2017-09-19 Power Integrations, Inc. Laterally-graded doping of materials
CN104835868B (zh) * 2015-05-13 2017-06-06 北京科立兴光电技术有限公司 一种pn结终端补偿台阶结构
CN105161527B (zh) * 2015-06-26 2018-03-02 成都成电知力微电子设计有限公司 利用一种表面耐压层结构的绝缘栅双极型器件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5976466A (ja) * 1982-10-25 1984-05-01 Mitsubishi Electric Corp プレ−ナ形半導体装置
JPS60124865A (ja) * 1983-12-09 1985-07-03 Nec Corp 半導体装置
JPS60257572A (ja) * 1984-06-04 1985-12-19 Mitsubishi Electric Corp 半導体装置の製造方法
GB2167229B (en) * 1984-11-21 1988-07-20 Philips Electronic Associated Semiconductor devices
JPS63122277A (ja) * 1986-11-12 1988-05-26 Fuji Electric Co Ltd 縦型ｍｏｓｆｅｔ
JPS63156360A (ja) * 1986-12-19 1988-06-29 Matsushita Electric Works Ltd 静電誘導形半導体装置
JPH04260375A (ja) * 1991-02-15 1992-09-16 Toyota Autom Loom Works Ltd 半導体装置の製造方法
EP0571695A1 (en) * 1992-05-28 1993-12-01 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe High voltage resistor integrated on a semiconductor substrate
JP2760709B2 (ja) * 1992-07-15 1998-06-04 株式会社東芝 高耐圧のｌｄｄ構造を有する半導体装置及びその製造方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101981700B (zh) * 2008-02-26 2014-05-14 克里公司 用于碳化硅器件的双保护环边缘终端和制造具有双保护环边缘终端的碳化硅器件的方法
US9640609B2 (en) 2008-02-26 2017-05-02 Cree, Inc. Double guard ring edge termination for silicon carbide devices
CN100576541C (zh) * 2008-05-14 2009-12-30 电子科技大学 一种半导体器件及其提供的低压电源的应用
US8460977B2 (en) 2008-08-11 2013-06-11 Cree, Inc. Mesa termination structures for power semiconductor devices and methods of forming power semiconductor devices with mesa termination structures
CN102969356A (zh) * 2012-11-08 2013-03-13 电子科技大学 一种超结功率器件终端结构
CN102969356B (zh) * 2012-11-08 2015-05-27 电子科技大学 一种超结功率器件终端结构
CN103280457A (zh) * 2013-05-14 2013-09-04 电子科技大学 一种超低比导通电阻的横向高压功率器件及制造方法
CN103280457B (zh) * 2013-05-14 2016-03-23 电子科技大学 一种超低比导通电阻的横向高压功率器件及制造方法
CN103413830A (zh) * 2013-08-16 2013-11-27 电子科技大学 一种横向高压mosfet及其制造方法
CN103413830B (zh) * 2013-08-16 2016-08-31 电子科技大学 一种横向高压mosfet及其制造方法
CN103413831A (zh) * 2013-08-30 2013-11-27 电子科技大学 一种横向高压器件及其制造方法
CN110379861A (zh) * 2019-08-12 2019-10-25 派恩杰半导体（杭州）有限公司 一种碳化硅异质结二极管功率器件
CN113690233A (zh) * 2021-09-22 2021-11-23 成都吉莱芯科技有限公司 一种可增强通流能力的单向esd保护器件及其制作方法
CN113690233B (zh) * 2021-09-22 2024-03-08 江苏吉莱微电子股份有限公司 一种可增强通流能力的单向esd保护器件及其制作方法

Also Published As

Publication number Publication date
US5726469A (en) 1998-03-10
CN1040814C (zh) 1998-11-18

Similar Documents

Publication Publication Date Title
CN1040814C (zh) 一种用于半导体器件的表面耐压区
CN1314091C (zh) 具有内嵌的沟槽肖特基整流器的沟槽dmos晶体管
CN1240136C (zh) 横向半导体器件
CN1244160C (zh) 半导体器件
CN1035294C (zh) 具有异形掺杂岛的半导体器件耐压层
CN1211844C (zh) 功率mosfet及利用自对准体注入制作其的方法
CN100339959C (zh) 具有改善的较小正向电压损耗的半导体器件以及制作方法
CN1034453C (zh) 半导体器件
CN1311560C (zh) 横向低侧高压器件及高侧高压器件
CN1663049A (zh) 横向半导体器件
EP0851505A2 (en) semiconductor device having a high voltage termination structure with buried field-shaping region
US20020053695A1 (en) Split buried layer for high voltage LDMOS transistor
CN1695251A (zh) 具有伸入较深的以沟槽为基础的源电极的以沟槽为基础的交叉栅电极的垂直mosfet及其制造方法
CN1586009A (zh) 场效应晶体管半导体器件
CN1695255A (zh) 半导体部件及其制造方法
CN1130776C (zh) 具有线性电流电压特性的半导体元件
US5893736A (en) Methods of forming insulated gate semiconductor devices having spaced epitaxial JFET regions therein
CN2720641Y (zh) 高压组件
JP2003101022A (ja) 電力用半導体素子
CN1589499A (zh) 具有多晶硅源极接触结构的沟槽mosfet器件
CN109888005A (zh) 逆导型超结igbt器件及其制造方法
WO2021030490A1 (en) High density power device with selectively shielded recessed field plate
CN1258229C (zh) 具有多数载流子累积层作为子集电极的双极晶体管
JP2000349288A (ja) 縦型ｍｏｓｆｅｔ
CN1890815A (zh) Ldmos晶体管

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Expiration termination date: 20150706

Granted publication date: 19981118

EXPY Termination of patent right or utility model