CN1099715C - 一种用于有浮动电压端的半导体器件的表面耐压层 - Google Patents

一种用于有浮动电压端的半导体器件的表面耐压层 Download PDF

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CN1099715C
CN1099715C CN98116187.1A CN98116187A CN1099715C CN 1099715 C CN1099715 C CN 1099715C CN 98116187 A CN98116187 A CN 98116187A CN 1099715 C CN1099715 C CN 1099715C
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陈星弼
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Abstract

一种用于低端电压浮动的高压半导体器件的表面耐压层，它含有两个耐压区，第一个耐压区被第二个耐压区所包围。第一个耐压区与边缘的顶部的电压可以相对于衬底而浮动。利用本发明可在同一芯片上不用介质隔离或p-n结隔离技术而制作有浮动电压端的高端高压器件、与高端高压器件的浮动电压端等电位的盆以及串接的高端高压器件与低端高压器件。且与CMOS或BiCMOS工艺兼容。

Description

一种用于有浮动电压端的半导体 器件的表面耐压层
本发明涉及半导体高压器件及功率器件技术，特别是涉及一种用于高压集成电路及功率集成电路中有浮动电压端的半导体器件的表面耐压层。
常规的高压集成电路中高压(功率)器件的制造方法有介质隔离(DI)方法、p-n结隔离(JI)方法及自隔离(SI)方法。其隔离性能是DI优于JI，JI优于SI。而成本则一般说是反过来：SI最低，JI次之，DI成本最高。
如图1所示，常规的高压集成电路通常含有四个部分：低压控制电路、与地(衬底)相连的驱动电路、高压电平位移电路以及参考高压的驱动电路。由图中可见，上述四个部分中的参考高压驱动电路的低压端与其余三个部分的高压端相连。也就是说，这种常规的功率集成电路中存在着一个共用的浮动电压端，其中的一部分电路以此浮动电压端为低压端，而另一部分电路以衬底为低压端。用常规的高压集成电路工艺往往需要将这两部分电路分别做在两个芯片上。B.Murari等人在“灵巧型功率集成电路技术和应用”<1995>(以下称文献1)一文中披露了一种BCD技术，利用此技术可以把这两部分电路集成在一个芯片上。但这种BCD技术中使用了介质隔离和p-n结隔离技术，其工艺复杂，又需占用较大的芯片面积，因而其制造成本高昂。因此，如何能提供一种工艺简单、不耗费芯片面积、成本较低的半导体集成电路成为目前本领域的重要课题。同时，如图1所示，高压集成电路在使用时还至少要外接两个高压器件，一个是高端MOS，另一个是低端MOS。由于B.murari的BCD技术中的介质隔离和p-n结隔离技术不能与常规的CMOS或BiCMOS工艺兼容，而且在图1所示的高压集成电路应用中往往还必须带有分立的MOS器件，所以，B.murari的BCD技术不能将分立的MOS器件做到集成电路中去。这不仅使器件的制造成本增高，而且减少了对分立的MOS器件的保护功能，从而使器件的可靠性不能得到进一步的提高。
本发明人在美国专利US 5726469(下称文献2)中公开了一种在半导体器件中制造表面耐压区的技术，文献2的技术可不用DI及JI技术而得到电学性能优越的功率器件。而且由于实现这种表面结构有许多灵活性，从而可在工艺上与微米级或亚微米级CMOS或BiCMOS工艺全兼容，因而能以比DI和JI技术低得多的成本制造功率集成电路中的功率(高压)器件。图2是用文献2所代表的现有技术制作高压二极管的例子，图中p-衬底1上有n+层2，其上覆盖了两个p+层(3与4)，阴极k位于中央而阳极A通过p+层5与衬底相联。显然，这种方法中的阳极A必须与衬底等电位，而不可能有相对于衬底为可变(浮动)的高电压。即，这一表面耐压结构仅适用于包括一个与衬底相连的最低电压端和一个相对于衬底为高电压端的器件。
如前所述，在功率集成电路中会遇到不仅希望做以衬底为低压端的器件(下面称为低端器件)，还要做一种低压端的电压可变的(或称为浮动的)高压器件(下面称为高端器件)，而且此浮动电压可能相当高。图3所示的高端MOS器件就属于这种器件。而这种器件根据文献2所公开的技术是无法制造的。此外，半导体功率集成电路中常常需要做一些低压器件，这些器件都有一个共同端与含浮动端的高压器件的浮动端相连。图3所示的方框内的集成电路中的器件就是这种低压器件。这种电路是把许多器件做在一个“盆”中，盆的作用相当于一种衬底，该衬底与芯片的衬底之间存在着一个浮动电压，在盆区中所做的电压较低的各器件都有一个端与盆的浮动电压一致。盆区整体可以有浮动的电压而不影响形成在盆区中的器件的特性。常规的方法之一是将高端n-MOS(High-Side n-MOS)单独形成在一个芯片上，浮动耐压端的盆(Floating High-Voltage“TUB”)另用一个芯片。如果低端器件耐压超过500V，电流超过1A，那么它也常常是另用一个芯片制成一个单管。常规的方法之二是将这三者都做在同一个芯片上，但是需采用SI及JI技术，所以成本很高，消耗的芯片面积也大。在现有技术中还可以利用文献2的技术来制作图3所示的这种“盆”，如图4所示。图4和图2的不同是在中心周围有一个p型区12，它与n型区2通过电极SH相连，然后外接到含浮动端的高压器件的浮动端上。图中的虚线槽内是当SH加到击穿电压时都未耗尽的区域，即形成一个盆区。该盆区的用处的例子是：在未耗尽的n+区2内做低压p-MOS，在未耗尽的p区12内做低压n-MOS，其做法和在常规n阱(这里是n+区2)与p阱(这里是p区12)上做器件一样。用上述方法仍然存在着需另制作含浮动端的高端高压器件的缺点。
本发明的目的之一在于提供一种既不用DI及JI技术又与CMOS或BiCMOS工艺兼容的方法来制作性能优越的具有浮动低压端的高压器件的表面耐压层。
本发明的目的之二在于提供一种既不用DI及JI技术又与CMOS或BiCMOS工艺兼容的方法来制作既有浮动端的高端器件，又有一个电位与此浮动端相同的盆(Tub)区、且节省芯片面积的半导体集成电路。
本发明的目的之三在于提供一种不用DI及JI技术且与CMOS或BiCMOS工艺兼容的方法来制作的、既有浮动端的高端器件又有以此浮动端作为高压端而以衬底为低压端的低端器件的半导体集成电路。
(本发明受到中国国家自然科学基金及国防科工委基金资助)
为实现上述目的，本发明提供了一种半导体集成电路器件的表面耐压层，所述半导体器件包括第一种导电类型的衬底、形成在所述衬底上的第二种导电类型的重掺杂区，以及形成在所述重掺杂区上的浮动电压端和高电压端，其特征在于包括：位于所述第二种导电类型的重掺杂区中间的第一表面耐压区，所述高电压端位于其中央部位，所述第一表面耐压区上围绕所述高压端直至其边缘处在所述第二种导电类型的重掺杂区之上有杂质密度随离开中央距离的增加而逐渐或阶梯式地增加的第一种导电类型的层，所述浮动电压端位于其边缘处，且在第一种导电类型的区之上，以及，位于所述第二种导电类型的重掺杂区、并包围着所述第一表面耐压区的第二表面耐压区，其中，所述第二种导电类型杂质的有效电离杂质密度随离开中央距离的增加而逐渐或阶梯式地下降，所述有效电离杂质密度系指加在所述浮动电压端与衬底之间的电压接近反向击穿电压时，在一个表面横向尺寸远小于WPP的面积内有效的第二种导电类型的电离杂质总数除以该面积所得的值，其中，WPP代表由所述衬底形成的单边突变平行平面结在其击穿电压下的耗尽层厚度。本发明的所述表面耐压层的所述第一表面耐压区中在中央及第一种导电类型区之下的第二种导电类型杂质的密度最好不小于NBWPP，其中，NB代表所述衬底的杂质密度。
为了实现本发明的第二个目的，提供了一种半导体集成电路器件，该半导体集成电路器件包括一形成在上述表面耐压层的第一表面耐压区上、具有高压端及浮动端的高压半导体器件，以及形成在所述第二表面耐压区上与所述浮动端保持等电位的盆区。
为了实现本发明的第三个目的，提供了一种半导体集成电路器件，该半导体集成电路器件包括一形成在上述表面耐压层的第一表面耐压区上、具有高压端和浮动端的高压半导体器件，以及一形成在所述第二表面耐压区上、具有所述浮动端和以衬底为最低电压端的半导体器件。
利用本发明的技术，可以用通常CMOS或BiCMOS技术而不用DI及JI技术即可做成性能优越的含浮动低压端的高压高端器件在内的集成电路。而且根据本发明的表面耐压层的优值超过普通的横向器件；耐压可达到在相同衬底上所做的单边突变平行平面结的击穿电压的90％以上；且导通电压低、电流密度大。
本发明的优点之二是可以不用SI及JI技术，同时将以浮动端为低压端的高端器件、与浮动端保持等电位的盆以及以此浮动端为高压端的低端器件这三者和低压CMOS电路或BiCMOS电路做在一块芯片上，因而很节省芯片面积。
下面结合附图说明本发明。
图1是一种常规的高压集成电路及其应用的示意图。
图2是用文献2的方法制作的一种高压二极管的剖面示意图。
图3代表一种典型的高压集成电路的应用，它含有以浮动端为低压端的高端高压器件，以浮动端为高压端的低端高压器件，以及与浮动端保持等电位的盆区。
图4是用文献2的方法制作电压可变(浮动)的盆的示意图。
图5、图6、图7和图8是根据本发明制造的含有浮动阳极A的二极管的两种不同结构的剖面示意图。
图8、图9、图10、图11及图12是用本发明的表面耐压层制造的源电压可变(浮动)的高端高压MOS的四种不同结构的剖面示意图。
图13是根据本发明制造的既有源电压可变(浮动)的高端MOS又有与此源电压等位的盆区的剖面示意图。
图14是通过在根据本发明的两耐压区之间刻了槽而制造的既有高端高压MOS又有低端高压MOS的图腾柱结构的剖面示意图。
图15是利用一个栅区代替图14的槽来制造图腾柱结构的剖面示意图。
图16是用本发明在半导体-绝缘体-半导体(SIS)上实现图腾柱结构的示意图。
图17是利用本发明的技术做成的高压CMOS的剖面示意图。
在上述附图中，相同的参考号表示同一个或相应的区域或部件。
图5是用本发明的技术制作的高压二极管的剖面示意图。它含有两个表面耐压区。第一个表面耐压区是围绕着在p-型衬底1上形成的n+型区2的中心部分的区域，其中心是高端器件的高压端k，其周围直到高端器件的浮动端A。该第一耐压区的n+型区2除中央部分的狭小范围外，均覆盖有薄的p+型区3和4。使得在高压端加到击穿电压VB而浮动端为零电压时，n+型区2的平均电离施主密度被覆盖的p+型区3和4的电离受主密度补偿后，其平均有效电离施主密度随离开中心的距离的增加而从NBWPP之值逐渐或阶梯式地下降，最后变得很小。这里，NB是p-衬底1的掺杂浓度、WPP指由该衬底构成的单边突变平行平面结在击穿电压VB下的耗尽层厚度。本发明要求此第一表面耐压区中n+型区2的施主密度在各处均大于NBWPP。当阳极A与阴极k电位相等且均达到击穿电压VB时，由于覆盖的p+层3、4与其下面的n+型区2等电位、p+层3、4只电离了极小部分，用以建立与n+型区2之间的内建电势Vbi。这导致有效电离施主密度随离开中心k的距离不变。第一表面耐压区(即从中央k到p+区4的外侧)的n+区2与p-衬底1之间象一个平行平面结，n+区2的电离施主密度为NBWPP加上一个p+区4与n+区2之间存在内建电势Vbi而消耗的施主密度、后者一般远小于前者而可忽略不计。由于在本发明中要求p+区4下面的n+区2的施主密度大于NBWPP，故n+区2中还有一个从中央直到p+区4外侧均未电离的中性区，使电位从k到与A相连的p+区4之下均相等。这时，从p+层4(浮动端A)到p-衬底1之间的耐压靠的是本发明的第二表面耐压区。该第二表面耐压区是从p-衬底1之上围绕p+层4的n+区2直到与p-衬底1相连的p+型区5为止的区域。在p+区4之外的n+区6的施主密度小于NBWPP，n+区7的施主密度比n+区6的更小，使得在p+区4与p-衬底1之间所加电压达到击穿电压时有效电施主密度随着从A向外侧的距离的增加而逐渐或阶梯式地减小。这点和图2中k的电压为VB时有效电离施主密度随着离开中心的距离的增加而逐渐或阶梯式地减小一样。显然，图5的阳极A与衬底之间可承受直到其值为VB的反向偏压。
当阳极A(即浮动电压端)的电压为零时，阴极k到阳极A之间的p+区3与p+区4大部分被耗尽。这使得k到A这段距离内(第一表面耐压区)的有效电离施主密度随离开中心k的距离的增加而逐渐地或阶梯式地下降，故阴极k仍能承受很高的电压。这时由于p+区4有电离受主而其下的n+区2有电离施主，故p+区4下的n+区2有一个低于VB的电压。这个电压并不会导致击穿，因为从p+区4之外侧直到与衬底相连的p+区5存在着表面耐压层的第二个表面耐压区。
图6所示的二极管的耐压原理与图5相同，区别只在于第二耐压区中有效电离施主密度的减少是由p+型区8和9中电离受主的补偿作用来达到的。为了防止p+区4与p+区8之间直接联通，它们之间由一个n型区隔开。在图6中，该隔开p+区4与p+区8的区域就是n+区2的一部分。
当上述二极管的阳极A处的电压比阴极k处高出内建电势Vbi时，阳极与阴极导通，由于Vbi一般远小于VB，因此这时的耐压原理和两个电极均加以电压VB时相同。
在这种二极管中，为了防止阳极A向衬底1注入空穴而形成寄生晶体管效应，应使该晶体管的电流放大系数极小。这可以采取常规的减少晶体管电流放大系数的方法，例如，降低少子的寿命。
如上所述的高压二极管中，要求浮动端A与第一种导电类型的p+区4相连，因此，p+区4必须在n+区2的顶部。但这并不等于要求第一种导电类型的p+区3也必须形成在n+区2的顶部。图7示出了p+区3不在n+区2顶部的情况。在该图中，p+区3及p+区4下面的n+区2中的杂质密度大于NBWPP。当阴极k与阳极A的电压均接近VB时，p+区3及p+区4下面的n+区的杂质密度足以使其与衬底p-区1之间形成类似于一个平面结，可承受VB的电压而不致于击穿。此时，p+区3上面的n+区中的杂质只电离了极小一部分，用于形成该两区之间的内建电势Vbi。当阴极k的电压接近VB而阳极A的电压为零时，p+区3和其上的n+区都被耗尽，造成平均电离施主密度随离开中心的距离的增大而不断下降。从而，和图5所示的器件一样，在加同样的电压时也不会击穿。
实际上，由于MOS、BJT、JFET之类器件在有源区的工作原理都是设法向一个反偏p-n结注入载流子并控制这种注入，因此，利用上述有浮动阳极的二极管的原理，容易制得有浮动低压端的上述器件。图8、9、10、11和12是以本发明的表面耐压区构成不同的含有浮动低压端的高压n-MOS的例子。对于熟悉本领域的技术人员来说，可以毫无困难地将本发明用于其它的器件。而且正如文献2所述，表面耐压层的第一表面耐压区可以不限于只有3、4两个p+层，第二表面耐压区可以不限于只有8及9或6及7两个区。
图8、图9、图10、图11和图12中与图5或图6中高压端k相应的部分为高压n-MOS的漏电极DH，与浮动端A相应的部分为该n-MOS的源电极SH。在图8中，作为源衬底的p+区4的上部有一个作为源区的n+区(10)，它通过其上面的欧姆接触电极SH与p+区4相连。在从n+区10与p+区4相连的另一侧延伸跨过p+区4直到与p+区4相连的n+区2的顶部覆盖有一个氧化层11，其上覆盖金属或多晶硅作为n-MOS的栅极GH。当GH的电压超过阈值电压时，有电子从源区10通过p+区4在栅GH下面形成的反型层而流出，最后流向DH。
为了改变图8中栅GH下的电场分布，在栅下的n+区2中还可设置另一个p+区12，它可以不与源区4相连，如图9所示。也可以通过别的方式的外联使之与源区保持等电位。此外，也可以将n+源区10做在p+区12之内，如图10所示，这时的源电极SH需接在p+区12和n+区10之上。
如图11所示，图8中的6、7两区自然也可以采用在n+区2上覆盖两个p+层(8与9)来代替。不言而喻，这种替代方法也可用在图9及图10所示的结构中。
图12是利用图7的结构制造的以浮动端为低压端的高端n-MOS器件。和图8、9、10、11所示的器件相比，其优点是，当SH的电压接近DH、且DH的电压接近VB时，p+区3上面的n+区仍然是中性区，因此，导通电阻较小。
利用本发明不但可以制作有浮动端的高压器件，而且可以利用第一表面耐压区的末端作为盆区来制造既有带浮动端的高压器件、又有与此浮动端等电位的盆区的半导体集成电路，从而节省了芯片的面积。图13示出了本发明的又一个实施例。该器件利用图10的基本结构，扩大其p区12，并在p区12之内再做一个n区13。n区13与p区12通过顶部的欧姆接触17相连，使它们保持等电位。即使在SH端的电压加到VB时，这两个区也有未耗尽的区域，此未耗尽的区域即是要做的盆。在未耗尽的p区12或n区13内可制作含浮动端的低压n-MOS或p-MOS，其浮动端均与电极SH等电位。
在功率集成电路中常常需要做两个串接的器件(图腾柱)，其中连接最高电压的器件称为高端(High-Side)器件或称上边(Upper)器件，它的浮动端和一个低端(Low-Side)器件或称下边(Lower)器件的高压端相联，低端器件的低压端接固定电位(有时称为地)。根据本发明的技术，既可以制做性能优越的低端器件，又可以做出性能优越的高端器件。这些器件结构的例子已示于图8、图9、图10、图11和图12中。不仅如此，本发明还可提供将低端器件做在高端器件的第二表面耐压区中的技术，这样可以省去另外专做低端器件的面积。图14示出一个用本发明的方法同时制做高端n-MOS和低端n-MOS的示意图。它是在图11的基础上，用形成在p+区5内的n+区14作为低端n-MOS的源，n+区14与p+区5在顶部通过低端n-MOS的源电极SL相联。从n+区14到其邻近的n+区2的顶部覆盖有氧化层，其上为低端n-MOS的栅电极GL。为了防止该n-MOS导通时电子由SL直接流到高端n-MOS的漏DH，需要将高端n-MOS与低端n-MOS的漂移区2(即第一表面耐压区和第二表面耐压区)隔断。在隔断处的外侧做低端n-MOS的漏电极DL，它通过引线与高端的源电极SH相联。这种隔断的具体方法是在半导体表面刻出U形的槽。
隔离高端n-MOS与低端n-MOS的漂移区的方法也可以利用一个p-n结加反偏压来实现。如图15所示，这里在图14所示的U形槽的地方形成了一个n区15，其中又形成一个p区16。p区16的顶部做一个电极GI，称为隔离电极。我们注意到，即使SH电压为零，第一耐压区边缘的n+区2仍存在一个电压V2。这是因为，n+区2的掺杂密度须大于NBWPP，使n+区2与p-区1间在SH电压为VB时能承受此电压。这样大的掺杂密度使得当SH电压为零时，其下方的n+区2不能全耗尽而存在中性区，中性区到衬底1的耗尽区边缘的电压等于其到SH的电压V2。V2的值可根据具体结构求得，它大于DL下的电压V1。即，槽或n型区15两侧的电位不同。因为DL与SH同电位，在SH的电压为零时，V1＝0。由此可知，即使SH的电压不为零(V1≠0)，一般说也有V2＞V1的关系。如果在GI上加上足够的负电压，不仅将n区15耗尽而且形成一个电压低于V1的区域，那么这就形成了一个电子势垒，电子不可能从第二漂移区的n+区2直接流向第一漂移区的n+区2。另外，只要GI的负电压不是非常大，上述电压低于V1的区域所具有的电压又是大于零。那么这个区域也是阻挡空穴从p区16经n区15流向衬底的空穴势垒。
上述用于阻挡电子流动和空穴流动的区15、16的作用类似于通常的JFET或SIT被关断的机制。因此对于熟悉本领域的技术人员而言，实际上还存在其它的关断方法。
本发明也适用于表面耐压层与衬底间存在一个绝缘层的情形，即SIS的情形。在SIS的情形下，高端n-MOS的漂移区(第一表面耐压区)与低端n-MOS的漂移区(第二表面耐压区)的隔离可更容易地解决。图16示出一个用SIS做这种器件的例子。它和图15的区别是增加了一个氧化层17，取消了一个n区15。这时只要在隔离电极GI上加上对p区16两旁的n+区2均低于Vbi的电压，就不会有电子穿过p区16的问题。而由于氧化层17的存在，空穴不可能从GI电极流向衬底。
利用本发明还可以方便地做成一种高压CMOS。图17是一种利用此技术制做的高压CMOS的剖面示意图。它实际上只是将图11的栅电极GH延伸到p+区8，这个栅电极现称为G。而与图11的SH相对应的部位为电极S，它既是高端n-MOS的源，也是低端p-MOS的源。当G的电压超过p+区4表面形成n型反型层的阈值电压时，高端n-MOS导通。当G的电压低于其下n+区2的表面上形成p型反型层的阈值电压时，空穴可以从p+区4经过p型反型层流向p+区8，最后流到与衬底相联的p+区5的地电极，低端p-MOS导通。注意，这里只用了一个栅电极，和通常的的CMOS的两个管子有两个栅电极不同。
利用本发明的技术可以方便地将图3所示的电路做在同一芯片内，无需采用SI及JI技术，从而减小了芯片面积，降低了成本。
以上的例子均采用p-型衬底对单个器件进行了说明。显然，对本领域的普通技术人员来说，可将所述内容毫无困难地用到n-型衬底以及集成电路的情况。

Claims (8)

1.一种半导体集成电路器件的表面耐压层，所述半导体集成电路器件包括第一种导电类型的衬底、形成在所述衬底上的第二种导电类型的重掺杂区，以及形成在所述重掺杂区上的浮动电压端和高电压端，其特征在于包括：
位于所述第二种导电类型的重掺杂区中间部位的第一表面耐压区，所述高电压端位于其中央部位，所述第一表面耐压区上围绕所述高压端直至其边缘处有形成在所述第二种导电类型的重掺杂区之上杂质密度随离开中央距离的增加而逐渐或阶梯式地增加的第一种导电类型的层，所述浮动电压端位于其边缘处，且在第一种导电类型的区域之上；
位于所述第二种导电类型的重掺杂区、包围着所述第一表面耐压区的第二表面耐压区，其中，所述第二种导电类型杂质的有效电离杂质密度随离开中央距离的增加而逐渐或阶梯式地下降，所述有效电离杂质密度系指加在所述浮动电压端与衬底之间的电压接近反向击穿电压时，在一个表面横向尺寸远小于WPP的面积内有效的第二种导电类型的电离杂质总数除以该面积所得的值，其中，WPP代表由所述衬底形成的单边突变平行平面结在其击穿电压下的耗尽层厚度。
2.如权利要求1所述的表面耐压层，其特征在于：所述第一表面耐压区中第二种导电类型杂质的密度不小于NBWPP，其中，NB代表所述衬底的杂质密度。
3.如权利要求1所述的表面耐压层，其特征在于：所述第二表面耐压区中的第二种导电类型杂质随着离开中央的距离的增加而减少的有效密度是通过既用第二种导电类型的杂质进行掺杂，又用处于耐压层上部的第一种导电类型的杂质进行补偿的方法得到的。
4.如权利要求1所述的表面耐压层，其特征在于：在所述第一种导电类型的衬底与所述第二种导电类型的表面耐压层之间设置有一个薄的绝缘层。
5.如权利要求1所述的表面耐压层，其特征在于：在所述第一表面耐压区和第二表面耐压区之间设置有一窄的沟槽。
6.如权利要求1所述的表面耐压层，其特征在于：所述第一表面耐压区和第二耐压区之间形成有一个窄的半导体区域用来防止载流子直接从一个表面耐压区流向另一个表面耐压区。
7.一种半导体集成电路器件，其特征在于：包括一形成在如权利要求1所述的表面耐压层的第一表面耐压区上、具有高压端及浮动端的高压半导体器件，以及形成在所述第二表面耐压区上与所述浮动端保持等电位的盆区。
8.一种半导体集成电路器件，其特征在于：包括一形成在如权利要求1所述的表面耐压层的第一表面耐压区上、具有高压端和浮动端的高压半导体器件，以及一形成在所述第二表面耐压区上、具有所述浮动端和以衬底为最低电压端的半导体器件。
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