CN1123071C - 混合半导体衬底 - Google Patents
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Abstract
一种混合半导体衬底，它包含：带有平整表面的单晶半导体本体区；平整表面上绝缘区上的半导体；平整表面上的单晶半导体外延层；只制作在绝缘区上的半导体第一周边部位处的将绝缘区上的半导体连接于所述单晶半导体本体区的导电间隔，该间隔的电阻率比其所接触的任何半导体区的电阻率低。导电间隔将绝缘体上的半导体电连接到地以克服浮置体效应。在导电间隔的表面上可制作绝缘间隔以便使绝缘体上的半导体电隔离于本体区。
Description
技术领域
本发明一般涉及到半导体器件，更具体地说是涉及到一种带有本体芯片区和绝缘体上硅区的半导体衬底，其中被选定的绝缘体上硅区被电连接于晶片以便减轻浮置体问题，并涉及到这种衬底的制作方法。
背景技术
常规的即体半导体器件是在P型或N型材料中用注入不同类型材料的阱的方法而制作在半导体材料之中的。栅及源/漏扩散区则采用普通熟知的工艺来制造。这样制造的器件即金属-氧化物-半导体(MOS)场效应晶体管即FET。当一个给定的芯片采用P型与N型二者时，即为互补金属氧化物半导体(“CMOS”)。为了避免电路短路，这种器件中的每一个都必须与其它的器件电隔离。为使各种FET电隔离，需要相当大的表面积，这对于降低尺寸和提高集成度的当今趋势是不可取的。此外，由于源/漏扩散区到其它FET的源/漏扩散区和体衬底的物理贴近，也可能出现寄生通路和结电容问题。当试图将尺寸降低到更高集成度所需的程度时，这也导致很多困难。而且，亚阈值斜率与衬底灵敏度也在将体CMOS工艺缩小到低压应用的过程中导致困难。
为了处理这些问题，绝缘体上硅(“SOI”)已越来越流行。但SOI有自发热、静电放电敏感性、低击穿电压以及动态浮置体效应等在传输门(passgate)器件中存在的问题，而且器件要求麻烦的阈值电压控制。当器件体未被连接于固定电位时，会发生浮置体效应，器件因而根据其历史而带电荷。具体地说，在动态随机存取存储器(“DRAM”)中，由于传输晶体管处于“关断”状态以防止电荷从储存电容器中漏出是关键性的，故浮置体效应可能特别有害。SOI的另一特别问题是由于SOI的特定目的是降低结电容，故制作大容量电容器(例如为了去耦应用)非常困难。此外，薄层半导体使得难以产生静电放电(“ESD”)器件所需的低阻放电通路。
发明内容
由于这些缺点，已提出最好的方案当为将高性能支持器件的SOI区与邻近的用于低漏电存储阵列的体器件相合起来。但同时制作SOI区和本体区二者充其量也是困难的。
本发明提供了一种混合半导体衬底，它包含：带有平整表面的单晶半导体本体区；平整表面上绝缘区上的半导体；平整表面上的单晶半导体外延层；只制作在绝缘区上的半导体第一周边部位处的将绝缘区上的半导体连接于所述单晶半导体本体区的导电间隔，该间隔的电阻率比其所接触的任何半导体区的电阻率低。
借助于一开始提供一个含有体半导体衬底、衬底上表面上的氧化层、以及氧化层上表面上的单晶半导体材料薄层，可制造混合半导体衬底。淀积诸如氮化硅之类的抛光停止材料薄层(5-10nm)，接着淀积可选择性地刻蚀以停止抛光的诸如二氧化硅的牺牲材料层(100nm)。在氧化层上形成窗口图形，且刻蚀穿过氮化物、SOI和背氧化物而停止于衬底表面。间隔材料被淀积于整个表面上，然后进行反应离子深刻蚀以便在窗口的侧壁上形成间隔。然后外延生长单晶硅。再用化学机械抛光方法整平整个结构的表面。然后可对单晶外延硅区及SOI区进行加工以便在平坦的表面上制作恰当的器件。
因此，本发明的优点是，为了制作本体/SOI混合物，可在平整的表面上制作体器件和SOI器件而没有光刻聚集深度问题所引起的布局问题。
另一优点是此方法能够选择性地制作可根据器件要求而隔离或连接的各个区域。
再一个优点是SOI器件可电连接于衬底或地以便消除浮置体效应并提高静电放电器件的效能。
附图说明
从本发明、附图及所附权利要求的下列详细描述中，可更清楚地了解本发明的其它大量优点和特征。
为了了解本发明的性质和优点，应结合附图参照下列详细描述，在这些附图中：
图1是实施本发明的方法中第一步骤的剖面示意图；
图2是实施本发明的方法中第二步骤的剖面示意图；
图3是实施本发明的方法中第三步骤的剖面示意图；
图4是实施本发明的方法中第四步骤的剖面示意图；
图5是本发明的俯视示意图；
图6是根据本发明的一个变通成品的剖面示意图。
具体实施方式
如图1所示，提供了一个标准的绝缘体上硅(“SOI”)衬底。此标准SOI是一个带有基本平坦表面的单晶半导体，且包含平坦表面上第一表面区中的一个绝缘层14和一个半导体薄层16以及平坦表面第二表面区中的一个本体区12。本体区12是一个晶体结构与平坦表面基本相同的单晶区。绝缘层14一般是氧化硅，而单晶半导体材料通常是硅。此衬底可用多种不同的方法来制造，包括：用氧化物注入硅(“SIMOX”，其中的本体晶片被大剂量氧高能注入)；键合和深刻蚀(“BE-SOI”，其中二个本体晶片有生长在表面上的氧化物，并在一个晶片中形成了杂质分布以用作记号层，二个氧化表面被键合在一起，然后将一个晶片深刻蚀至记号掺杂层)；或所谓的“智能切割”法(其中在第一晶片键合到第二晶片之前，一个晶片被注入氢，二晶片被键合在一起，然后用硅结构中的氢来引起恰当程度的裂纹或用其它制造SOI的适当方法来剥去一个晶片的过量硅。一旦制作了SOI衬底，就在硅的薄层上淀积厚度通常为～5nm-～10nm的氮化硅的薄的抛光停止层18)(见图2)。然后如图2所示，在氮化物薄层18上淀积牺牲层，此时是厚度通常约为100nm的氧化层20。此氧化层20用来为后续生长的外延(“epi”)硅提供缓冲区。此缓冲区避免了氮化物层上的外延过生长，从而改善了阵列区边缘处的晶体质量，以下将进一步解释。
如图3所示，用通常的方法，一般是用光抗蚀剂材料光刻确定区域然后刻蚀所确定的区域的方法，在氧化层中制作窗口22。材料被刻蚀穿过氧化物20、氮化物18、SOI和背氧化层14和16，停止于本体衬底12的顶部。这些窗口将形成DRAM之类产品中的阵列区。然后可在隔离区上的半导体周边部位周围的选定位置中制作诸如氮化物的电隔离间隔或诸如多晶硅的导电间隔24。若采用导电间隔24，则由于间隔的电阻率比它所接触的任何一个半导体区的电阻率都低得多，它就被用来将SOI区的半导体16电连接到衬底。用作导电间隔的典型材料包括(但不局限于)：铝、钨、多晶硅、铜、铝铜、钛、硅化钛、硅化镍或硅化钴。间隔24用已知的方法借助于淀积一层所需的间隔材料然后对此材料进行定向刻蚀以形成间隔的方法来制作。若希望只在一侧有间隔24，则可用一阻挡掩模来保护所需的间隔而将另一个间隔刻蚀掉。
在SIMOX SOI情况下，刻蚀至硅衬底顶区内部以清除背隔离层与单晶硅区之间被高剂量氧注入所损伤的过渡区，从而为后续的外延生长提供良好基底可能是可取的。然后从衬底表面生长一个P型外延层30。外延层30可以选择性地或非选择性地生长。若生长是非选择性的，则生长在焊点氧化层上的硅可用抛光整个表面的方法清除。为了易于控制反应条件并节省时间，可选取非选择性生长。生长条件调整成外延层的顶表面至少与薄的抛光停止层18的上表面同样高。抛光前的衬底示于图3。
然后抛光整个衬底以得到图4所示的结构。对外延生长硅区的抛光需要使用对氧化物与氮化物抛光停止层有选择性的抛光液。抛光垫最好是刚性的以避免外延层相对于抛光停止层表面过大的凹槽。当外延层延伸于顶部氧化层上方时，抛光过程可能涉及二个抛光步骤。第一步骤是用氧化层作为抛光停止层来抛光外延层。通常这会使外延层30的表面凹下低于氧化层表面。若外延生长被很好地控制成足以停止于氧化层顶部之前，则此第一步骤没有必要。在第一抛光之后，第二外延抛光将采用氮化物作为抛光停止层。在第二步骤中可使用与第一抛光中所用的相同的抛光垫和抛光液。此步骤将外延层30整平到氮化物18的顶部。抛光时间取决于外延生长量。外延层30的高度越接近于氮化物停止层18的高度，所需的抛光就越少。说明均匀性和缺陷的某些过生长的一个理想的淀积目标可能是氧化物停止层的中点。由于外延层的顶表面应在氮化物层顶部数百埃以内，故可能出现的任何凹陷都应是不重要的，且不会引起阵列区相对于SOI区的聚焦深度问题。
如图5所示，SOI的区域100完全被本体区102围绕，反过来又完全被SOI 104区围绕。第一即导电间隔105沿二边即内部SOI 100的第一周边部提供。第二即绝缘间隔107沿一边即本体区102的第二周边部提供。在其余的周边部位中，外延生长硅与SOI区直接接触。由于对任一边都有一种这样的选择，故此图用来表示本发明的灵活性。间隔类型的不同组合可用来满足使用中的具体体接触、隔离和热沉要求。例如，外延层可生长在与所有邻近SOI区相接触的窗口中。这就为与窗口邻接的SOI区提供了体接触。这可以用于可能因浮置体效应而受到损害的关键电路，诸如传输门金属氧化物半导体场效应晶体管(MOSFET)或诸如读出放大器或静态随机存取存储器(SRAM)元件的要求严格匹配的器件。完全接触的外延层可产生带有接触体的完全耗尽的SOI器件和用于如DRAM陈列或低噪声应用的体器件的衬底。
SOI各侧上的绝缘间隔使未接触的体SOI器件可制作在体器件附近。当有害的浮置体效应不足以用来引起器件稳定性的丧失时，这提供了SOI的最大性能优点，即以一般低于1.5V的低电源工作的接地源器件。
绝缘间隔可用于SOI的一边上而在任何其它边上没有间隔。这种安排为制作彼此靠近的接触体SOI、本体和浮置体SOI器件提供了布局灵活性。
导电间隔(可能是金属)可提供在SOI区的各侧上。这种安排提供了非常低的电阻和从SOI体到衬底的热通路。对于为体电流可能相当大的高压应用提供稳定性来说，这是有用的。比起外延层生长成与SOI区相接触的安排来，这也为SOI提供了改进的功率耗散能力。
图6示出了另一个变通安排。制作了导电间隔124以提供SOI区120到衬底的非常低的电阻通路，而绝缘间隔126制作在导电间隔124上以提供SOI区120与相邻的体器件区122之间的介电隔离。在同一步骤中还可在不出现导电间隔124的选定周边部位制作绝缘间隔126，也可不在出现导电间隔124的选定周边部位中制作绝缘间隔126，这取决于所需要的各种参量器件的结构与功能。能够包括电接触于衬底的二个部分同时又介电隔离于外延层，对于低噪声和混合模拟/数字应用来说是有用和重要的。
虽然已参照其最佳实施例具体描述了本发明，但本技术领域熟练人员应了解可作出其它形式和细节的改变而不超越本发明的构思与范围。
Claims (19)
1.一种混合半导体衬底，它包含：
(a)带有平整表面的单晶半导体本体区；
(b)平整表面上绝缘区上的半导体；
(c)平整表面上的单晶半导体外延层；
(d)只制作在绝缘区上的半导体第一周边部位处的将绝缘区上的半导体连接于所述单晶半导体本体区的导电间隔，该间隔的电阻率比其所接触的任何半导体区的电阻率低。
2.权利要求1的半导体衬底，其特征是单晶半导体本体区是硅片。
3.权利要求1的半导体衬底，其特征是导电间隔的材料选自铝、钨、多晶硅、铜、铝铜、钛、硅化钛、硅化镍或硅化钴。
4.权利要求1的半导体衬底，其特征是外延层是硅材料。
5.权利要求1的半导体衬底，其特征是还包含绝缘区上的半导体和外延层上的多个器件，且为了绝缘区上的半导体上多个器件的较高压应用而在绝缘区上的半导体的整个周边处制作导电间隔。
6.权利要求1的半导体衬底，其特征是还包含只制作在绝缘区上半导体的第二周边部位处的使绝缘区上的半导体介电隔离于第二周边部位中的外延层的绝缘间隔。
7.权利要求6的半导体衬底，其特征是绝缘区上的半导体直接接触不在第一周边部位和第二周边部位中的其余周边中的外延层。
8.权利要求1的半导体衬底，其特征是第一周边部位是整个周边。
9.权利要求1的半导体衬底，其特征是第一周边部位是周边的一部分且绝缘区上的半导体直接接触其余周边中的外延层。
10.权利要求1的半导体衬底，其特征是外延层具有与平整表面相同的晶体结构。
11.权利要求10的半导体衬底，还包含：
制作在导电间隔上的半导体的选定周边部位处、从而将绝缘区上的半导体电隔离于所述外延层的绝缘间隔。
12.权利要求11的半导体衬底，其特征是单晶半导体本体区是硅片。
13.权利要求11的半导体衬底，其特征是导电间隔的材料选自铝、钨、多晶硅、铜、铝铜、钛、硅化钛、硅化镍或硅化钴。
14.权利要求11的半导体衬底，其特征是外延层是硅材料。
15.权利要求11的半导体衬底，其特征是还包含绝缘区上的半导体和外延层上的多个器件，且为了绝缘区上的半导体上多个器件的较高压应用，第一周边部位是绝缘区上的半导体的整个周边。
16.权利要求11的半导体衬底，其特征是还包含只制作在绝缘区上的半导体的第二周边部位处使绝缘区上的半导体介电隔离于第二周边部位中的外延层的绝缘间隔。
17.权利要求16的半导体衬底，其特征是绝缘区上的半导体直接接触不在第一周边部位和第二周边部位中的其余周边中的外延层。
18.权利要求11的半导体衬底，其特征是第一周边部位是整个周边。
19.权利要求11的半导体衬底，其特征是第一周边部位是周边的一部分，且绝缘区上的半导体直接接触其余周边中的外延层。
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| US878225 | 1997-06-18 | ||
| US878,225 | 1997-06-18 | ||
| US08/878,225 US5894152A (en) | 1997-06-18 | 1997-06-18 | SOI/bulk hybrid substrate and method of forming the same |
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| CN1202736A CN1202736A (zh) | 1998-12-23 |
| CN1123071C true CN1123071C (zh) | 2003-10-01 |
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| JP (1) | JP2980586B2 (zh) |
| KR (1) | KR100289830B1 (zh) |
| CN (1) | CN1123071C (zh) |
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| JP5505367B2 (ja) | 2011-05-11 | 2014-05-28 | 信越半導体株式会社 | 基板の一部に絶縁層を有する貼り合わせ基板の製造方法 |
| US8916426B2 (en) | 2012-03-27 | 2014-12-23 | International Business Machines Corporation | Passive devices for FinFET integrated circuit technologies |
| US9059041B2 (en) | 2013-07-02 | 2015-06-16 | International Business Machines Corporation | Dual channel hybrid semiconductor-on-insulator semiconductor devices |
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| US5273915A (en) * | 1992-10-05 | 1993-12-28 | Motorola, Inc. | Method for fabricating bipolar junction and MOS transistors on SOI |
| US5554870A (en) * | 1994-02-04 | 1996-09-10 | Motorola, Inc. | Integrated circuit having both vertical and horizontal devices and process for making the same |
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| US3943555A (en) * | 1974-05-02 | 1976-03-09 | Rca Corporation | SOS Bipolar transistor |
| JPS6358817A (ja) * | 1986-08-29 | 1988-03-14 | Toshiba Corp | 複合半導体結晶体構造 |
| JPS6412543A (en) * | 1987-07-07 | 1989-01-17 | Toshiba Corp | Manufacture of semiconductor device |
| US5374576A (en) * | 1988-12-21 | 1994-12-20 | Hitachi, Ltd. | Method of fabricating stacked capacitor cell memory devices |
| US5032529A (en) * | 1988-08-24 | 1991-07-16 | Harris Corporation | Trench gate VCMOS method of manufacture |
| JPH0834261B2 (ja) * | 1992-06-17 | 1996-03-29 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Ｂｉｃｍｏｓ集積回路用のｓｏｉ構造体およびその製造方法 |
| EP0610599A1 (en) * | 1993-01-04 | 1994-08-17 | Texas Instruments Incorporated | High voltage transistor with drift region |
| US5364800A (en) * | 1993-06-24 | 1994-11-15 | Texas Instruments Incorporated | Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate |
| JPH07254706A (ja) * | 1993-11-29 | 1995-10-03 | Texas Instr Inc <Ti> | 高電圧デバイス構造およびその製造方法 |
| US5399507A (en) * | 1994-06-27 | 1995-03-21 | Motorola, Inc. | Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications |
| US5581101A (en) * | 1995-01-03 | 1996-12-03 | International Business Machines Corporation | FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures |
| US5818069A (en) * | 1997-06-20 | 1998-10-06 | Advanced Micro Devices, Inc. | Ultra high density series-connected transistors formed on separate elevational levels |
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1997
- 1997-06-18 US US08/878,225 patent/US5894152A/en not_active Expired - Lifetime
-
1998
- 1998-04-21 TW TW087106112A patent/TW405220B/zh not_active IP Right Cessation
- 1998-05-14 KR KR1019980017441A patent/KR100289830B1/ko not_active IP Right Cessation
- 1998-05-15 CN CN98108451A patent/CN1123071C/zh not_active Expired - Lifetime
- 1998-05-15 MY MYPI98002182A patent/MY117502A/en unknown
- 1998-06-09 JP JP10160221A patent/JP2980586B2/ja not_active Expired - Fee Related
- 1998-11-05 US US09/187,292 patent/US6107125A/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5273915A (en) * | 1992-10-05 | 1993-12-28 | Motorola, Inc. | Method for fabricating bipolar junction and MOS transistors on SOI |
| US5554870A (en) * | 1994-02-04 | 1996-09-10 | Motorola, Inc. | Integrated circuit having both vertical and horizontal devices and process for making the same |
Also Published As
| Publication number | Publication date |
|---|---|
| US6107125A (en) | 2000-08-22 |
| CN1202736A (zh) | 1998-12-23 |
| JPH1117001A (ja) | 1999-01-22 |
| JP2980586B2 (ja) | 1999-11-22 |
| US5894152A (en) | 1999-04-13 |
| TW405220B (en) | 2000-09-11 |
| KR19990006452A (ko) | 1999-01-25 |
| MY117502A (en) | 2004-07-31 |
| KR100289830B1 (ko) | 2001-12-12 |
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