CN111630654A - 多层配线的形成方法和存储介质 - Google Patents
多层配线的形成方法和存储介质 Download PDFInfo
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- CN111630654A CN111630654A CN201980009315.3A CN201980009315A CN111630654A CN 111630654 A CN111630654 A CN 111630654A CN 201980009315 A CN201980009315 A CN 201980009315A CN 111630654 A CN111630654 A CN 111630654A
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- wafer
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
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- C25D3/38—Electroplating: Baths therefor from solutions of copper
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- Organic Chemistry (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemically Coating (AREA)
Abstract
实施方式的多层配线的形成方法是埋入型的多层配线的形成方法,其包括:在通孔(70)中配线(50)露出的底面(73)形成单分子膜(80)的工序,其中该通孔(70)在设置于基片的配线(50)上的绝缘膜(60)的规定的位置形成并贯通至配线(50);在通孔(70)的侧面(72)形成阻挡膜(81)的工序;除去单分子膜(80)的工序;将露出于通孔(70)的底面(73)的配线(50)作为催化剂,从通孔(70)的底面(73)起形成无电解镀膜(82)的工序。
Description
技术领域
本发明的实施方式涉及多层配线的形成方法和存储介质。
背景技术
一直以来,作为在当做基片(基板)的半导体晶片(以下,称为晶片。)形成多层配线的方法,已知有在设置于配线上的绝缘膜形成的通孔的内面层叠阻挡层和种子层,然后实施电解镀敷处理以填埋通孔的内部的方法(例如,参照专利文献1)。
现有技术文献
专利文献
专利文献1:日本特开2013-194306号公报
发明内容
发明要解决的技术问题
然而,在现有的多层配线的形成方法中,在通孔的深宽比高的情况下,阻挡层和种子层相对于通孔的比例变高而通孔变得细长,因此在电解镀敷处理中难以良好地填埋通孔的底部附近。由此,在通孔的底部附近等可能形成空隙(void)、裂缝(seam)等不良部位,所以存在半导体装置的可靠性降低的可能性。
实施方式的一方式是鉴于上述情况完成的,其目的在于,提供能够在深宽比高的通孔的底部附近形成良好的金属配线的多层配线的形成方法和存储介质。
用于解决技术问题的技术手段
实施方式的一方式的多层配线的形成方法是埋入型的多层配线的形成方法,其包括:在通孔中上述配线露出的底面形成单分子膜的工序,其中上述通孔在设置于基片的配线上的绝缘膜的规定的位置形成并贯通至上述配线;在上述通孔的侧面形成阻挡膜的工序;除去上述单分子膜的工序;和将露出于上述通孔的底面的上述配线作为催化剂,从上述通孔的底面起形成无电解镀膜的工序。
发明效果
依照实施方式的一方式,能够在深宽比高的通孔的底部附近形成良好的金属配线。
附图说明
图1是表示实施方式的多层配线形成系统的概要结构的示意图。
图2是表示实施方式的无电解镀敷处理单元的结构的截面图。
图3是表示实施方式的电解镀敷处理单元的结构的截面图。
图4A是用于说明实施方式的多层配线的形成处理的示意图(1)。
图4B是用于说明实施方式的多层配线的形成处理的示意图(2)。
图4C是用于说明实施方式的多层配线的形成处理的示意图(3)。
图4D是用于说明实施方式的多层配线的形成处理的示意图(4)。
图4E是用于说明实施方式的多层配线的形成处理的示意图(5)。
图4F是用于说明实施方式的多层配线的形成处理的示意图(6)。
图4G是用于说明实施方式的多层配线的形成处理的示意图(7)。
图5是表示实施方式的多层配线的形成处理中的处理顺序的流程图。
具体实施方式
以下,参照所附的附图,对本发明公开的多层配线的形成方法和存储介质的实施方式详细地进行说明。此外,通过以下所示的实施方式并不能够限定该发明。此外,附图是示意性的图,需要注意,存在各要素的尺寸的关系、各要素的比例等与现实不同的情况。而且,也存在在附图彼此之间,包含彼此的尺寸的关系、比例不同的部分的情况。
<多层配线形成系统的概要>
首先,参照图1,对实施方式的多层配线形成系统1的概要结构进行说明。图1是表示实施方式的多层配线形成系统1的概要结构的图。以下,为了明确位置关系,规定彼此正交的X轴、Y轴和Z轴,将Z轴正方向作为铅垂向上方向。
如图1所示,多层配线形成系统1包括送入送出站2(工位)和处理站3。送入送出站2与处理站3相邻地设置。
送入送出站2包括承载器载置部11和输送部12。在承载器载置部11,载置将多个半导体晶片W(以下,称为晶片W。)以水平状态收纳的多个承载器C。
输送部12与承载器载置部11相邻地设置,在内部设有基片输送装置13和交接部14。基片输送装置13包括保持晶片W的晶片保持机构。此外,基片输送装置13能够在水平方向和铅垂方向上移动以及以铅垂轴为中心旋转,使用晶片保持机构在承载器C与交接部14之间进行晶片W的输送。
处理站3与输送部12相邻地设置。处理站3包括输送部15、多个单分子膜形成处理单元16、多个成膜处理单元17、多个无电解镀敷处理单元18和多个电解镀敷处理单元19。
多个单分子膜形成处理单元16、多个成膜处理单元17、多个无电解镀敷处理单元18和多个电解镀敷处理单元19并排地设置于输送部15的两侧。此外,图1所示的单分子膜形成处理单元16、成膜处理单元17、无电解镀敷处理单元18和电解镀敷处理单元19的配置、个数为一例,并不限于图示的情况。
输送部15在内部设有基片输送装置20。基片输送装置20包括保持晶片W的晶片保持机构。此外,基片输送装置20能够在水平方向和铅垂方向上移动以及以铅垂轴为中心旋转,使用晶片保持机构在交接部14、单分子膜形成处理单元16、成膜处理单元17、无电解镀敷处理单元18与电解镀敷处理单元19之间进行晶片W的输送。
单分子膜形成处理单元16对由基片输送装置20输送的晶片W进行规定的单分子膜形成处理。单分子膜形成处理单元16例如是具有加热部的真空腔室。
成膜处理单元17对由基片输送装置20输送的晶片W进行规定的成膜处理。成膜处理单元17例如是PVD(Physical Vapor Deposition:物理气相沉积)装置、CVD(ChemicalVapor Deposition:化学气相沉积)装置等的干式处理装置。
无电解镀敷处理单元18对由基片输送装置20输送的晶片W进行规定的无电解镀敷处理。对无电解镀敷处理单元18的结构例在后文说明。
电解镀敷处理单元19对由基片输送装置20输送的晶片W进行规定的电解镀敷处理。对电解镀敷处理单元19的结构例在后文说明。
另外,多层配线形成系统1包括控制装置4。控制装置4例如是计算机,包括控制部21和存储部22。
控制部21包含具有CPU(Central Processing Unit:中央处理单元)、ROM(ReadOnly Memory:只读存储器)、RAM(Random Access Memory:随机存取存储器)、输入输出端口等的微型计算机、各种电路。
该微型计算机的CPU通过读取并执行存储于ROM的程序,来实现输送部12和/或输送部15、单分子膜形成处理单元16、成膜处理单元17、无电解镀敷处理单元18、电解镀敷处理单元19等的控制。
此外,该程序也可以记录于计算机可读取的存储介质,从该存储介质安装到控制装置4的存储部22。作为计算机可读取的存储介质,例如有硬盘(HD)、软盘(FD)、光盘(CD)、磁光盘(MO)、存储卡等。
存储部22例如由RAM、闪存(Flash Memory)等半导体存储元件、或者、硬盘、光盘等的存储装置实现。
如上述那样构成的多层配线形成系统1中,首先,送入送出站2的基片输送装置13从载置于承载器载置部11的承载器C取出晶片W,将取出的晶片W载置在交接部14。载置于交接部14的晶片W由处理站3的基片输送装置20从交接部14取出,送入单分子膜形成处理单元16。
被送入到单分子膜形成处理单元16的晶片W由单分子膜形成处理单元16实施了规定的单分子膜形成处理后,由基片输送装置20从单分子膜形成处理单元16送出,并送入成膜处理单元17。
被送入到成膜处理单元17的晶片W由成膜处理单元17实施了规定的阻挡膜形成处理后,由基片输送装置20从成膜处理单元17送出,并送入无电解镀敷处理单元18。
被送入到无电解镀敷处理单元18的晶片W由无电解镀敷处理单元18实施了规定的单分子膜除去处理和无电解镀敷处理后,由基片输送装置20从无电解镀敷处理单元18送出,并送入成膜处理单元17。
被送入到成膜处理单元17的晶片W由成膜处理单元17实施了规定的种子膜形成处理后,由基片输送装置20从成膜处理单元17送出,并送入电解镀敷处理单元19。
被送入到电解镀敷处理单元19的晶片W由电解镀敷处理单元19实施了规定的电解镀敷处理后,由基片输送装置20从电解镀敷处理单元19送出,并载置到交接部14。然后,载置于交接部14的已处理的晶片W由基片输送装置13送回承载器载置部11的承载器C。
<无电解镀敷处理单元的概要>
接着,参照图2,对无电解镀敷处理单元18的概要结构进行说明。图2是表示实施方式的无电解镀敷处理单元18的结构的截面图。无电解镀敷处理单元18例如构成为对晶片W逐一进行处理的单片式的处理单元。
无电解镀敷处理单元18如图2所示,包括壳体30、基片旋转保持机构31、处理液供给机构32、杯状体33和液排出机构34~36。
基片旋转保持机构31在壳体30的内部旋转并保持晶片W。基片旋转保持机构31具有旋转轴31a、转台31b、晶片吸盘31c和未图示的旋转机构。
旋转轴31a是中空圆筒状的,在壳体30内上下地延伸。转台31b安装于旋转轴31a的上端部。晶片吸盘31c设置于转台31b的上表面外周部,支承晶片W。
而且,基片旋转保持机构31由控制装置4的控制部21控制,用旋转机构对旋转轴31a进行旋转驱动。由此,能够使支承于晶片吸盘31c的晶片W旋转。
处理液供给机构32对基片旋转保持机构31所保持的晶片W的表面供给规定的处理液。处理液供给机构32包括对晶片W的表面供给第1处理液的第1处理液供给机构32a和对晶片W的表面供给第2处理液的第2处理液供给机构32b。
该第1处理液例如为TMAH(Tetramethyl ammonium hydroxide:四甲基氢氧化铵)。此外,第2处理液例如为无电解镀液(非电解浸镀液)。
另外,处理液供给机构32具有喷头32c,在该喷头32c安装喷嘴32d、32e。该喷嘴32d、32e分别是与第1处理液供给机构32a和第2处理液供给机构32b对应的喷嘴。
喷头32c安装在臂32f的前端部。该臂32f能够在上下方向上移动,并且固定在由未图示的旋转机构旋转驱动的支承轴32g,能够旋转。
利用这样的构成,处理液供给机构32可将规定的处理液经由喷嘴32d、32e从所希望的高度释放到晶片W表面的任意的部位。
杯状体33承接从晶片W飞散的处理液。杯状体33构成为具有3个排出口33a~33c,通过未图示的升降机构在上下方向能够驱动。3个排出口33a~33c分别与液排出机构34~36连接。
液排出机构34~36将聚集到排出口33a~33c的处理液排出。液排出机构34包括由流路切换器34a切换的回收流路34b和废弃流路34c。回收流路34b例如是用于回收第1处理液以进行再利用的流路,废弃流路34c是用于废弃第1处理液的流路。
液排出机构35包括由流路切换器35a切换的回收流路35b和废弃流路35c。回收流路35b例如是用于回收第2处理液以进行再利用的流路,废弃流路35c是用于废弃第2处理液的流路。
另外,在回收流路35b的出口侧,在第2处理液为无电解镀液的情况下,设置冷却该无电解镀液的冷却缓冲器35d。此外,在液排出机构36仅设置废弃流路36a。
此外,在实施方式中使用喷嘴32d、32e以将处理液供给到晶片W上,不过将处理液供给到晶片W上的机构并不限于喷嘴,可以使用其他各种机构。
<电解镀敷处理单元的概要>
接着,参照图3,对电解镀敷处理单元19的概要结构进行说明。图3是示出实施方式的电解镀敷处理单元19的构成的截面图。电解镀敷处理单元19例如构成为对晶片W逐一进行处理的单片式的处理单元。
电解镀敷处理单元19包括基片保持部40、电解处理部41、电压施加部42和处理液供给机构43。
基片保持部40具有保持晶片W的功能。基片保持部40包括晶片吸盘40a和驱动机构40b。
晶片吸盘40a例如是保持晶片W并使其旋转的旋转吸盘。晶片吸盘40a为大致圆板状,具有在俯视时直径比晶片W的直径大且在水平方向上延伸的上表面40c。在该上表面40c,例如设置有吸引晶片W的吸引口(未图示),利用由吸引口进行的吸引,能够将晶片W保持在晶片吸盘40a的上表面40c。
在基片保持部40,还设置有具有电动机等的驱动机构40b,能够使晶片吸盘40a以规定的速度旋转。此外,在驱动机构40b设置有缸等的升降驱动部(未图示),能够使晶片吸盘40a在铅垂方向上移动。
此处在说明的基片保持部40的上方,与晶片吸盘40a的上表面40c相对地设置电解处理部41。电解处理部41包括基体41a、直接电极41b、接触端子41c和移动机构41d。
基体41a由绝缘性材料构成。基体41a为大致圆板状,具有在俯视时直径比晶片W的直径大的下表面41e和设置在该下表面41e的相反侧的上表面41f。
直接电极41b由导电性材料构成,设置在基体41a的下表面41e。直接电极41b以与基片保持部40所保持的晶片W大致平行地相对的方式配置。而且,在进行电解镀敷处理时,直接电极41b与供给(盛放)到晶片W上的电解镀敷液直接接触。
接触端子41c在基体41a的边缘部从下表面41e突出地设置。接触端子41c由具有弹性的导电体构成,向下表面41e的中心部弯曲。
接触端子41c在基体41a设置2个以上,例如在基体41a设置32个,俯视时在基体41a的同心圆上等间隔地配置。而且,所有接触端子41c的前端部以该前端部构成的假想面与基片保持部40所保持的晶片W的表面大致平行的方式配置。
该接触端子41c在进行电解镀敷处理时,与晶片W的外周部接触,对该晶片W施加电压。此外,接触端子41c的数量、形状并不限于上述的实施方式。
直接电极41b和接触端子41c连接到电压施加部42,能够对分别接触的电解镀敷液和晶片W施加规定的电压。
在基体41a的上表面41f侧设置移动机构41d。移动机构41d例如具有缸等升降驱动部(未图示)。而且,通过该升降驱动部,移动机构41d能够使电解处理部41整体在铅垂方向上移动。
电压施加部42具有直流电源42a、开关42b、42c和负载电阻42d,连接到电解处理部41的直接电极41b和接触端子41c。具体而言,直流电源42a的正极侧经由开关42b与直接电极41b连接,并且直流电源42a的负极侧经由开关42c和负载电阻42d与多个接触端子41c连接。此外,直流电源42a的负极侧接地。
而且,通过将开关42b、42c同时切换成接通状态或者断开状态,电压施加部42能够对直接电极41b和接触端子41c施加脉冲状的电压。
在基片保持部40与电解处理部41之间,设置处理液供给机构43。该处理液供给机构43具有喷嘴43a、43b和移动机构43c。喷嘴43a将DHF(Diluted HydroFluoric acid:稀氢氟酸)等清洗液供给到晶片W上。喷嘴43b将电解镀敷液供给到晶片W上。
移动机构43c能够使喷嘴43a、43b在水平方向和铅垂方向上移动。即,喷嘴43a、43b构成为相对于基片保持部40能够进退。
另外,喷嘴43a构成为与贮存清洗液的未图示的清洗液供给源连通,能够从该清洗液供给源对喷嘴43a供给清洗液。喷嘴43b构成为与贮存电解镀敷液的未图示的镀敷液供给源连通,能够从该镀敷液供给源对喷嘴43b供给电解镀敷液。
此外,在实施方式中使用喷嘴43a、43b将处理液供给到晶片W上,不过将处理液供给到晶片W上的机构并不限于喷嘴,可以使用其他各种机构。
<多层配线的形成处理的详情>
接着,参照图4A~图4G,对实施方式的多层配线的形成处理的详情进行说明。图4A~图4G是用于说明实施方式的多层配线的形成处理的示意图(1)~(7)。
此外,在图4A~图4G所示的晶片W已经形成了未图示的元件。然后,在该元件形成后的配线形成工序(所谓的BEOL(Back End of Line:线末端)),形成于配线50上的绝缘膜60的通孔70由金属配线填埋,下面对这样的各种处理进行说明。
如图4A所示,在晶片W形成金属的配线50,并且在该配线50上设置绝缘膜60。配线50例如是包含Cu、Co、Ni或者Ru的导电性的材料。
绝缘膜60例如包括氧化膜61和氮化膜62。而且,在配线50上以规定的厚度形成氮化膜62,在该氮化膜62上以规定的厚度形成氧化膜61。氮化膜62例如当配线50由在Cu等的氧化膜61内扩散的元素构成的情况下,作为用于使该元素不向氧化膜61内扩散的阻挡膜发挥作用。
此外,在晶片W,在绝缘膜60的规定的位置形成通孔70。该通孔70从绝缘膜60的上表面63贯通至配线50地形成。而且,通孔70具有内面71,该内面71包含侧面72和配线50露出的底面73。
此处,作为在晶片W的绝缘膜60形成通孔70的方法,能够从现有公知的方法中采用适当的方法。具体而言,例如作为干蚀刻技术,能够应用使用了氟系或者氯系气体等通用的技术。
尤其是,作为形成深宽比(深度相对于直径的比率)大的通孔70技术,能够采用可进行高速的深掘蚀刻的ICP-RIE(Inductively Coupled Plasma Reactive Ion Etching:电感耦合等离子体-反应性离子蚀刻)的技术。
例如,可以优选采用反复进行使用六氟化硫(SF6)的蚀刻步骤和使用C4F8等特氟龙(注册商标)系气体的保护步骤的、所谓的博世工艺。
如图4A所示,在配线50上的绝缘膜60形成有通孔70的晶片W,被送入上述的单分子膜形成处理单元16,进行规定的单分子膜形成处理。该单分子膜形成处理在真空腔室内使硅烷偶联剂、钛偶联剂等偶联剂气化并使其吸附。
由此,如图4B所示,在露出于通孔70的底面73的配线50上,形成单分子膜80。此外,该单分子膜80由于使用仅吸附在金属的偶联剂来形成,因此仅形成在配线50上,不形成在绝缘膜60的表面。
即,依照实施方式,通过使用偶联剂形成单分子膜80,能够在通孔70的底面73选择性地形成单分子膜80。
此外,在实施方式中,给出了在真空腔室内吸附偶联剂来形成单分子膜80的例,但是形成单分子膜80的方法并不限于该例。例如,也可以将溶解了偶联剂的处理液释放到晶片W上,通过使被释放了该处理液的晶片W旋转来形成单分子膜80。
接着,形成有单分子膜80的晶片W被送入上述的成膜处理单元17,进行规定的阻挡膜形成处理。该阻挡膜形成处理使用PVD法、CVD法等通用的技术来进行。
由此,如图4C所示,在通孔70的侧面72、绝缘膜60的上表面63,形成由Co-W-B合金等构成的阻挡膜81。此处,在单分子膜80的表面阻碍阻挡膜81的形成,因此在通孔70的底面73不形成阻挡膜81。
此外,在实施方式中给出了阻挡膜81由Co-W-B合金构成的例,不过阻挡膜81并不限于Co-W-B合金,由后述的能够防止无电解镀膜82(参照图4E)、电解镀膜84(参照图4G)所含的元素向氧化膜61内扩散的材料构成即可。
另外,在实施方式中,给出了阻挡膜81通过PVD法、CVD法等干式处理形成的例,不过阻挡膜81并不限于通过干式处理形成的情况,例如也可以通过无电解镀敷处理等湿式处理形成。
接着,形成有阻挡膜81的晶片W被送入上述的无电解镀敷处理单元18,先进行规定的单分子膜除去处理。该单分子膜除去处理例如使用无电解镀敷处理单元18的第1处理液供给机构32a将作为第1处理液的TMAH释放到晶片W上。
由此,如图4D所示,将形成于通孔70的底面73的单分子膜80溶解并除去。此外,在实施方式中给出了用TMAH除去单分子膜80的例,不过进行除去的处理液并不限于TMAH。此外,在单分子膜除去处理中,可以用高热将单分子膜80热分解来除去,也可以用等离子体使单分子膜80飞起来除去。
接着,对除去了单分子膜80的晶片W进行规定的无电解镀敷处理。该无电解镀敷处理例如使用无电解镀敷处理单元18的第2处理液供给机构32b将作为第2处理液的无电解镀液释放到晶片W上。
由此,如图4E所示,将露出于通孔70的底面73的配线50作为催化剂,从通孔70的底面73自下而上地形成无电解镀膜82。此外,在实施方式中,在包含通孔70的底部附近的下部形成无电解镀膜82。
这样一来,通过将露出于底面73的配线50作为催化剂,从底面73自下而上地形成无电解镀膜82,能够在深宽比大且难以形成金属配线的通孔70的底部附近,形成不含空隙、裂缝等的良好的金属配线。
另外,在实施方式中,由于将配线50作为催化剂形成无电解镀膜82,因此无需借助阻挡膜、种子膜等,能够使配线50与无电解镀膜82直接接触。由此,能够降低在通孔70的内部形成的金属配线的电阻。
在实施方式中,无电解镀膜82可以包含Cu、Co、Ni或者Ru。由此,将包含Cu、Co、Ni或者Ru的配线50作为催化剂,能够从通孔70的底面73起高效地形成无电解镀膜82。
接着,形成有无电解镀膜82的晶片W被送入上述的成膜处理单元17,进行规定的种子膜形成处理。该种子膜形成处理使用PVD法、CVD法等通用的技术进行。
由此,如图4F所示,在通孔70的内面71、绝缘膜60的上表面63形成种子膜83。种子膜83由后述的形成电解镀膜84(图4G参照)时作为催化剂发挥作用的材料构成。例如,在电解镀膜84为Cu或者Cu合金的情况下,种子膜83可以包含Cu,在电解镀膜84为Co或者Co合金的情况下,种子膜83可以包含Co。
接着,形成有种子膜83的晶片W被送入上述的电解镀敷处理单元19,先进行规定的清洗处理。该清洗处理例如使用处理液供给机构43的喷嘴43a将作为清洗液的DHF释放到晶片W上。
由此,由于形成于种子膜83的表面的自然氧化膜、附着物等被除去,因此能够使种子膜83的表面成为清洁的状态。
接着,对进行了清洗处理的晶片W进行规定的电解镀敷处理。该电解镀敷处理例如首先使用图3所示的电解镀敷处理单元19中的处理液供给机构43的喷嘴43b,将电解镀敷液供给到晶片W上。
接着,通过移动机构41d使电解处理部41整体靠近基片保持部40所保持的晶片W,使接触端子41c的前端部与晶片W的外周部接触。此外,此时,使直接电极41b直接接触被供给到晶片W的电解镀敷液。
然后,通过将电压施加部42的开关42b和开关42c同时从断开状态改变为接通状态,以使直接电极41b成为阳极,使晶片W成为阴极的方式对晶片W和电解镀敷液施加电压,使电流在直接电极41b与晶片W之间流动。
由此,在晶片W的表面将金属离子还原,如图4G所示,将种子膜83作为催化剂在种子膜83的表面析出电解镀膜84,通孔70的内部被电解镀膜84填埋。例如,能够通过使用含有Cu的电解镀敷液来形成含有Cu的电解镀膜84,通过使用含有Co的电解镀敷液能够形成含有Co的电解镀膜84。
通过此处说明的各种处理,依照实施方式,能够将深宽比高的通孔70的内部用良好的金属配线填埋。
<多层配线的形成处理的详情>
接着,参照图5,对实施方式的多层配线的形成处理的详情进行说明。图5是表示实施方式的多层配线的形成处理中的处理顺序的流程图。
此外,图5所示的多层配线的形成处理通过如下方式来执行:控制部21读取从实施方式的存储介质安装到存储部22的程序,并且控制部21基于读出的命令来控制输送部15和/或单分子膜形成处理单元16、成膜处理单元17、无电解镀敷处理单元18、电解镀敷处理单元19等。
首先,将在配线50上的绝缘膜60形成有通孔70的晶片W从承载器C经由基片输送装置13、交接部14和基片输送装置20,向单分子膜形成处理单元16的内部输送。
接着,控制部21控制单分子膜形成处理单元16,对晶片W进行单分子膜形成处理,在通孔70的底面73形成单分子膜80(步骤S101)。该单分子膜形成处理例如通过在真空腔室内使硅烷偶联剂、钛偶联剂等偶联剂气化并使其吸附来进行。
接着,控制部21控制基片输送装置20,将晶片W从单分子膜形成处理单元16输送到成膜处理单元17。然后,控制部21控制成膜处理单元17对晶片W进行阻挡膜形成处理,在通孔70的侧面72、绝缘膜60的上表面63形成阻挡膜81(步骤S102)。
该阻挡膜形成处理例如通过使用PVD法、CVD法等通用的技术,在晶片W形成Co-W-B合金等的阻挡膜81来进行。
接着,控制部21控制基片输送装置20,将晶片W从成膜处理单元17输送到无电解镀敷处理单元18。然后,控制部21控制无电解镀敷处理单元18对晶片W进行单分子膜除去处理,从通孔70的底面73起除去单分子膜80(步骤S103)。
该单分子膜除去处理例如通过将TMAH释放到晶片W上,利用该TMAH使形成在通孔70的底面73的单分子膜80溶解来进行。
接着,控制部21控制无电解镀敷处理单元18,对晶片W进行无电解镀敷处理,从通孔70的底面73起形成无电解镀膜82(步骤S104)。
该无电解镀敷处理例如通过以下方式来进行:将无电解镀液释放到晶片W上,将露出于底面73的配线50作为催化剂,利用所释放的无电解镀液从底面73自下而上地形成无电解镀膜82。
接着,控制部21控制基片输送装置20,将晶片W从无电解镀敷处理单元18输送到成膜处理单元17。然后,控制部21控制成膜处理单元17,对晶片W进行种子膜形成处理,在通孔70的内面71、绝缘膜60的上表面63形成种子膜83(步骤S105)。
该种子膜形成处理例如通过使用PVD法、CVD法等通用的技术,在晶片W形成包含Cu、Co等的种子膜83来进行。
接着,控制部21控制基片输送装置20,将晶片W从成膜处理单元17输送到电解镀敷处理单元19。然后,控制部21控制电解镀敷处理单元19,对晶片W进行清洗处理,清洗晶片W(步骤S106)。
该清洗处理例如通过将DHF释放到晶片W上,利用该DHF除去形成于种子膜83的表面的自然氧化膜、附着物等来进行。
接着,控制部21控制电解镀敷处理单元19,对晶片W进行电解镀敷处理,将通孔70的内部用电解镀膜84填埋(步骤S107)。
该电解镀敷处理例如将电解镀敷液供给到晶片W上,使接触端子41c的前端部与晶片W的外周部接触并且使直接电极41b直接接触到电解镀敷液。
然后,电解镀敷处理通过以下方式进行:以使直接电极41b为阳极,使晶片W为阴极的方式对晶片W和电解镀敷液施加电压,使电流在直接电极41b与晶片W之间流动。当该电解镀敷处理完成时,对晶片W的多层配线的形成处理完成。
以上,对本发明的实施方式进行了说明,但是本发明并不限于上述实施方式,只要不超出其主旨就能够进行各种改变。例如,在上述的实施方式中,给出了在通孔70的底部附近形成无电解镀膜82,然后用电解镀膜84填埋了通孔70的内部的例,不过也可以仅用无电解镀膜82填埋通孔70的内部。
另外,在上述的实施方式中,给出了将电解镀敷液供给到晶片W上来进行电解镀敷处理的例,但是电解镀敷处理并不限于该例。例如,也可以通过使晶片浸渍在贮存有电解镀敷液的电解槽内来进行电解镀敷处理。
而且,在上述的实施方式中,也可以在形成了无电解镀膜82、电解镀膜84后,通过用热板等实施规定的焙烧处理,来降低无电解镀膜82、电解镀膜84的电阻。
实施方式的多层配线的形成方法是埋入型的多层配线的形成方法,其包括:在通孔70中配线50露出的底面73形成单分子膜80的工序(步骤S101),该通孔70在设置于基片(晶片W)的配线50上的绝缘膜60的规定的位置形成并贯通至配线50;在通孔70的侧面72形成阻挡膜81的工序(步骤S102);除去单分子膜80的工序(步骤S103);和将露出于通孔70的底面73的配线50作为催化剂,从通孔70的底面73起形成无电解镀膜82的工序(步骤S104)。由此,能够在深宽比高的通孔70的底部附近,形成不含空隙、裂缝等的良好的金属配线。
另外,在实施方式的多层配线的形成方法中,单分子膜80由偶联剂形成。由此,能够在通孔70的底面73选择性地形成单分子膜80。
另外,在实施方式的多层配线的形成方法中,无电解镀膜82含有Cu、Co、Ni或者Ru。由此,能够将含有Cu、Co、Ni或者Ru的配线50作为催化剂,从通孔70的底面73起高效地形成无电解镀膜82。
另外,实施方式的存储介质是存储有在计算机上运行的控制多层配线形成系统1的程序的计算机可读取的存储介质,程序在执行时使计算机控制多层配线形成系统1,以进行以上记载的多层配线的形成方法。由此,能够在深宽比高的通孔70的底部附近,形成不含空隙、裂缝等的良好的金属配线。
进一步的效果、变形例,对于本领域技术人员而言能够容易地推导出。因此,本发明的更广泛的方式并不限于如上述那样示出且记述的特定的详情和代表性的实施方式。所以,在不超出由所附的权利要求的范围及其等同物定义的总体性的发明的概念的精神或者范围的情况下,能够进行各种各样的改变。
附图标记说明
W 晶片
1 多层配线形成系统
16 单分子膜形成处理单元
17 成膜处理单元
18 无电解镀敷处理单元
21 控制部
50 配线
60 绝缘膜
70 通孔
72 侧面
73 底面
80 单分子膜
81 阻挡膜
82 无电解镀膜。
Claims (4)
1.一种埋入型的多层配线的形成方法,其特征在于,包括:
在通孔中基片的配线露出的底面形成单分子膜的工序,其中所述通孔形成在设置于所述配线上的绝缘膜的规定位置并贯通至所述配线;
在所述通孔的侧面形成阻挡膜的工序;
除去所述单分子膜的工序;和
将露出于所述通孔的底面的所述配线作为催化剂,从所述通孔的底面起形成无电解镀膜的工序。
2.如权利要求1所述的多层配线的形成方法,其特征在于:
所述单分子膜由偶联剂形成。
3.如权利要求1或2所述的多层配线的形成方法,其特征在于:
所述无电解镀膜含有Cu、Co、Ni或者Ru。
4.一种计算机可读取的存储介质,其存储有在计算机上运行的控制多层配线形成系统的程序,所述存储介质的特征在于:
所述程序在执行时使计算机控制所述多层配线形成系统,以进行如权利要求1~3中任一项所述的多层配线的形成方法。
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- 2019-01-23 WO PCT/JP2019/002070 patent/WO2019151078A1/ja active Application Filing
- 2019-01-23 CN CN201980009315.3A patent/CN111630654A/zh active Pending
- 2019-01-23 TW TW108102500A patent/TW201936986A/zh unknown
- 2019-01-23 JP JP2019569045A patent/JP6903171B2/ja active Active
- 2019-01-23 KR KR1020207024983A patent/KR20200111253A/ko not_active Application Discontinuation
- 2019-01-23 US US16/938,047 patent/US20210358767A1/en not_active Abandoned
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Also Published As
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WO2019151078A1 (ja) | 2019-08-08 |
TW201936986A (zh) | 2019-09-16 |
JP6903171B2 (ja) | 2021-07-14 |
JPWO2019151078A1 (ja) | 2021-01-14 |
KR20200111253A (ko) | 2020-09-28 |
US20210358767A1 (en) | 2021-11-18 |
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