TW201708609A - 鍍敷處理方法及記憶媒體 - Google Patents

鍍敷處理方法及記憶媒體 Download PDF

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TW201708609A
TW201708609A TW105113836A TW105113836A TW201708609A TW 201708609 A TW201708609 A TW 201708609A TW 105113836 A TW105113836 A TW 105113836A TW 105113836 A TW105113836 A TW 105113836A TW 201708609 A TW201708609 A TW 201708609A
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layer
plating
substrate
electroless plating
wiring layer
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Nobutaka Mizutani
Mitsuaki Iwashita
Takashi Tanaka
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Tokyo Electron Ltd
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Abstract

使用鹼性且包含錯合材之無電解鍍敷液而對 由鋁或其合金所構成之Al層上施予無電解鍍敷。 鍍敷處理方法具備：準備在表面(例 如，TSV(12)之底部表面)露出有由鋁或鋁合金所構成之Al層(22)之基板(10)的工程；之後對基板施予鋅酸鹽處理，且在Al層之表面形成鋅酸鹽皮膜(30)之工程；及之後使用鹼性且包含錯合劑之無電解鍍敷液(例如，Co系鍍敷液)，在Al層之表面形成第1無電解鍍敷層(例如，Co阻障層(14a))之第1無電解鍍敷工程。

Description

鍍敷處理方法及記憶媒體
本發明係關於在例如半導體裝置之Al配線層等之Al層之表面上形成Co鍍敷的技術。
在LSI等之半導體裝置之BEOL中被使用的配線材料大多為銅(Cu)。為了形成Cu配線層，需要形成用以防止Cu在絕緣層中擴散的阻障層，及為了順暢地進行Cu之電鍍，在阻障層上藉由無電解Cu鍍敷形成晶種層等，而增加了成本。因此，針對配線材料不要求像Cu般之低電阻的部分，使用低成本之鋁(Al)配線材料。
於形成被連接於Al配線層之Cu配線層之時，必須形成阻障層，以使Cu不擴散至Cu配線層之周圍之由矽系材料所構成之絕緣層。
作為將Cu配線層掩埋至TSV等之深孔內之前，在該孔之內表面形成阻障層之方法，所知的有使用PVD等之成膜裝置的方法(參照專利文獻1)。作為在深孔內表面形成阻障層之另外的方法，所知的也有無電解鍍 敷法。可以藉由無電解鍍敷法來形成，並且作為具有相對於Cu較高之阻障性的實用材料之一，有鈷或鈷合金(以下，也稱為Co系材料)(參照專利文獻2)。
本發明研究被連接於Al配線層之Cu配線層用的阻障層適用Co系之無電解鍍敷之結果，顯然有以下之問題點。即是，Co系無電解鍍敷液係容易侵蝕鋁之鹼性，包含對鋁攻擊性非常強之錯合材。因此，就算要在鋁配線層上直接施予Co系之無電解鍍敷，基底之鋁的溶解較鍍敷之生長優先產生，事實上不可能形成Co系鍍敷層。
〔先行技術文獻〕 〔專利文獻〕
〔專利文獻1〕日本專利第4246706號公報
〔專利文獻2〕日本特開2013-194306號公報
本發明之目的在於提供使用鹼性且包含錯合材之無電解鍍敷液而在由鋁或其合金所構成之Al層上施予無電解鍍敷的技術。
若藉由本發明之一實施型態，提供一種鍍敷 處理方法，具備：在表面露出有由鋁或其合金所構成之鋁層的基板之工程；之後，對上述基板施予鋅酸鹽處理，在上述鋁層之表面形成鋅酸鹽皮膜之工程；和之後，使用鹼性且包含錯合劑之無電解鍍敷液，在上述鋁層之上述表面形成第1無電解鍍敷層之工程。
若藉由本發明之其他實施型態時，為一種記錄有程式的記憶媒體，該程式係於藉由用以控制鍍敷處理系統之動作之電腦而被實行之時，上述電腦控制上述鍍敷處理系統而使上述鍍敷處理方法實行。
若藉由本發明時，由於無電解鍍敷皮膜之生長藉由鋅酸鹽皮膜快速進行，故就算又有鋁層藉由無電解鍍敷液而受損，亦可以無問題地在鋁層之上形成無電解鍍敷層。
10‧‧‧基板
12‧‧‧凹部(TSV)
22‧‧‧Al層(Al配線層)
30‧‧‧鋅酸鹽皮膜
14a(14)‧‧‧第1無電解鍍敷層(Co阻障層)
14b(14)‧‧‧第2無電解鍍敷層(Co阻障層)
16‧‧‧Cu鍍敷(Cu配線層)
32‧‧‧觸媒層
100‧‧‧鍍敷處理系統
120‧‧‧控制裝置
122‧‧‧記憶媒體
圖1為簡化表示藉由與本發明之一實施型態有關之鍍敷處理方法而被處理的半導體裝置之一例之構成的剖面圖。
圖2為針對上述鍍敷處理方法之工程而說明之TSV附近之概略剖面圖。
圖3為概略性地表示用以實施上述鍍敷處理方法之鍍 敷處理系統之構成的圖示。
以下，參照圖面針對本發明之較佳實施型態進行說明。
在以下說明之實施型態係關於形成由鈷或鈷合金所構成之Co阻障層14，和由銅或銅合金所構成之Cu配線層(埋入配線)16之方法，該Co阻障層14係藉由無電解鍍敷法被形成在屬於被形成在基板10之凹部的TSV12(Through Silicon Via)內，該Cu配線層16係藉由鍍敷法所形成。
在圖1中，左半邊表示在TSV12內形成Co阻障層14及Cu配線層16之前之狀態，右半邊表示形成Co阻障層14及Cu配線層16之後的狀態。
圖1為將構成適用3次元高積體化(3DI)技術之半導體記憶裝置之複數層之晶片中之一個予以大幅度地單純化表示的圖示。該晶片具有以FEOL(front end of line)形成之電晶體等之電路元件18，和藉由BEOL(back end of line)形成的配線層20。
在配線層20包含由鋁或鋁合金所構成(通常為含有數%程度之Cu的鋁合金)之Al配線層22和由銅或銅合金所構成之Cu配線層24。雖然實際上存在阻障層、晶種層等以作為Cu配線層24之下層，但是因為簡化圖面，在圖1中無顯示。也如本說明書之開頭的先前技術 之欄中敘述般，由於Al配線層22可以利用比較低之成本來形成，故藉由配線容積充分等之理由，被使用於無必要使用雖然低電阻但價格高之銅的部位上。
製造表示在圖1左半邊之裝置構造的方法由於係該項技藝者熟知者，故在本說明書中省略其說明。以下，在本說明書中，僅針對與朝TSV12內之Co阻障層14及Cu配線層16關連之技術性事項進行說明。
TSV12係通過作為構成基板10之基材的矽基板(矽晶圓)26及被形成在矽基板26之下面上的TEOS層28之中而延伸。矽基板26及TEOS層28皆由含有矽之絕緣性材料(介電性材料)所構成。即使設置SiO2層或SiOC層以取代TEOS層28亦可。
由於在如此含矽絕緣性材料中銅容易擴散，故在TSV12內埋入Cu配線層16之時，必須形成銅擴散防止用之阻障層。如之前的先前技術之欄敘述般，作為可以確實地形成在屬於高縱橫比之凹部的TSV12內，並且具有銅擴散防止功能之阻障層，已提案有使用藉由無電解鍍敷法所形成之由鈷或鈷合金所構成之Co阻障層14之方法(參照專利文獻2(日本特開2013-194306號公報))。
在TSV12之底面露出有Al配線層22。也如之前的先前技術之欄敘述般，難以在Al配線層22上藉由無電解鍍敷法形成Co阻障層14。本實施型態係關於可以解決其問題之鍍敷處理方法。
以下參照圖2，針對在TSV12內形成Co阻障層14及Cu配線層16之一連串的工程進行說明。另外，在圖2中，表示較圖1簡化TSV12附近之構造。即是，圖2(a)係表示更簡化圖1之左側之TSV12周圍的圖示。
〔氧化皮膜除去工程〕
首先，對基板10供給鹼性洗淨液(以NaOH為主成分)，而除去位在露出於TSV12內之Al配線層22之表面的氧化皮膜。之後，進行藉由純水(DIW)之沖洗處理，且從基板10除去鹼性洗淨液及反應副生成物。
〔污垢除去工程〕
接著，對基板10供給污垢除去用之酸性藥液，藉由氧化皮膜除去工程，除去產生在Al配線層22之表面的污垢(Al(OH)3)。之後，進行藉由純水之沖洗處理，且從基板10除去酸性藥液及反應副生成物。
而且，半導體裝置之Al配線層22(埋入配線層)通常使用含有數%程度之Cu的鋁合金。因此，由於污垢不含有Si、Mg等之雜質，故在此所使用之污垢除去用之酸性藥液無須包含(通常含在一般的污垢除去用的藥液)氟酸，即使為以水稀釋硝酸亦可。此係降低對矽基板26及TEOS層28的損傷之意，具有效果。污垢除去工程可以例如藉由維持基板10之表面被常溫之濃度30%之硝 酸(HNO3(aq))覆蓋30秒左右之期間的狀態來實施。
〔鋅酸鹽處理工程〕
接著，對基板施予鋅酸鹽處理，且在Al配線層22之表面形成鋅(Zn)皮膜(鋅酸鹽皮膜)30(參照圖2(b))。在此，設為進行雙重鋅酸鹽處理。
雙重鋅酸鹽處理係由下述工程所構成：第1鋅酸鹽工程，其係對基板10供給鋅酸鹽處理液，且使Al配線層22之表面析出Zn粒子；第1沖洗工程，其係之後，藉由純水從基板10除去鋅酸鹽液及反應副生成物；Zn棒工程，其係之後對基板供給硝酸(即使與在污垢除去工程中所使用者相同亦可)，使在第1鋅酸鹽工程中析出的Zn粒子暫且剝離；第2沖洗工程，其係之後，藉由純水從基板10除去硝酸及反應副生成物；第2鋅酸鹽工程，其係對基板10供給鋅酸鹽處理液，且使Al配線層22之表面析出Zn粒子；及第3沖洗工程，其係之後，藉由純水從基板10除去鋅酸鹽液及反應副生成物。
藉由進行雙重鋅酸鹽處理，比起進行單鋅酸鹽處理之時(至第1沖洗工程為止結束鋅酸鹽處理之時)，可以更緻密地析出更微細之Zn粒子。形成高品質之Zn皮膜以進行雙重鋅酸鹽處理為佳，即使進行單鋅酸 鹽處理亦可。
單鋅酸鹽處理係在由鋁或鋁合金所構成之基底上形成由鎳或鎳合金所構成之Ni鍍敷(不管電解、無電解)之時被廣泛使用。藉由發明者之實驗，確認出以實質上與當作Ni鍍敷之前處理的鋅酸鹽處理相同之條件，進行從氧化物除去工程至鋅酸鹽處理工程為止的工程(處理條件為眾知)，在由鋁或鋁合金所構成之基底上，可以以良好之狀態形成Co系無電解鍍敷。
〔Co阻障層形成工程(第1次)〕
接著，對基板10供給Co系無電解鍍敷液，在Al配線層22之表面形成Co阻障層14之一部分(14a)(參照圖2(c))。在此，藉由例如包含鎢(W)及硼(B)之CoWB系之鍍敷形成Co阻障層14a。
此時，覆蓋Al配線層22之表面的Zn皮膜30被置換成鈷(或鈷合金)，在Al配線層22之表面上析出鈷(或鈷合金)。此時，藉由鹼性，且包含對鋁之攻擊性高的錯合劑之Co系無電解鍍敷液，Al配線層22之表面雖然受到些許損傷，但是由於Co阻障層14a以非常高速度析出而覆蓋Al配線層22之表面，故可以在Al配線層22之表面無問題地形成Co阻障層14。於形成Co阻障層14a之後，之後進行藉由純水之沖洗處理，從基板10除去鍍敷液及反應副生成物等之殘渣。
在Co阻障層形成工程中，僅在Al配線層22 之表面形成鋅酸鹽皮膜(Zn粒子)，並且由於在矽基板26及TEOS層28之表面，在不形成鋅酸鹽皮膜之狀態下進行無電解鍍敷，故在TSV12內，Co阻障層14a僅從Al配線層22之表面生長。在矽基板26及TEOS層28之表面不析出Co阻障層。
當Co阻障層形成工程(第1層)結束時，因容易被侵入Co系無電解鍍敷液之Al配線層22之表面並不係早已露出TSV12內，故之後的處理(下述之觸媒層形成工程以後之工程)可以以眾知之通常之手段來進行。
〔觸媒層形成工程〕
接著，在TSV12內形成觸媒層32(參照圖2(d))。觸媒層係可以藉由順序實行例如對基板10供給矽烷耦合劑或鈦耦合劑等之適當的耦合劑，形成SAM(自己組織化單分子膜)之工程，和之後對基板10供給氯化鈀液等之觸媒離子含有液之工程，和之後對基板供給DMAB(二甲基胺硼烷)等之還原劑之工程來進行。藉由該觸媒層形成工程，在包含TSV12之內表面(包含露出於TSV12內之矽基板26及TEOS層28之表面)之基板10之表面全體形成觸媒層32。於形成觸媒層之後，進行藉由純水之沖洗處理，從基板10除去最後使用之藥液(DMAB)及反應副生成物。觸媒層32之形成方法並不限定於上述者，可以採用眾知之任意方法。觸媒層32所包含之觸媒金屬並不限定於鈀，即使為無電解鍍敷之還原 析出反應之觸媒而能發揮機能之其他金屬，例如金(AU)、白金(Pt)、釕(Ru)等亦可。
〔Co阻障層形成工程(第2次)〕
接著，對基板10供給Co系無電解鍍敷液，藉由無電解鍍敷法在TSV12內形成Co阻障層14中之另一部分(14b)(參照圖2(e))。即是，在露出於TSV12內之矽基板26及TEOS層28之表面析出Co阻障層14b。另外，此時在已被形成於Al配線層22之表面的Co阻障層14a上，更析出Co阻障層14b。再者，由於在基板10之表面全體形成有觸媒層，故在基板10之表面全體形成Co阻障層14b。於形成Co阻障層14b之後，進行藉由純水(DIW)之沖洗處理，從基板10除去鍍敷液及反應副生成物等之殘渣。
〔Cu配線層形成工程〕
接著，對基板10供給Cu系無電解鍍敷液，而使Co阻障層14上析出作為晶種層之銅或銅合金(以下，記載成Cu)(參照圖2(f))。接著，藉由電解鍍敷，以Cu鍍敷埋入TSV12內而形成Cu配線層16。由於在基板10之全表面形成有Co阻障層14，故在基板10之全表面形成Cu配線層16。另外，視孔或凹部(TSV12)之尺寸而定，即使僅藉由無電解鍍敷形成Cu配線層16亦可，於形成Cu配線層16之後，進行藉由純水之沖洗處理，從基板 10除去鍍敷液及反應副生成物等之殘渣。
之後，藉由CMP(化學機械研磨)，除去位於基板10之表面(TSV12之外側)的不需要的Cu鍍敷。藉由上述，一連串之工程結束，成為顯示於圖1之右側的狀態。
若藉由上述實施型態時，可以藉由無電解鍍敷法無問題地形成藉由進行鋅酸鹽處理難以形成在鋁或其合金之表面的由鈷或其合金所構成之鍍敷皮膜。
因此，可以將露出於形成在半導體裝置之絕緣層內之高縱橫比之凹部之內表面的Al配線層，經由Co阻障層14，與被埋入凹部之Cu配線層16良好地電性連接。
針對用以實行從上述氧化皮膜除去工程至Co阻障層形成工程(第1次)為止之工程(即是，Al配線層22完全被Co阻障層14a覆蓋為止之工程)之鍍敷處理系統之構成例簡單進行說明。作為第1例，鍍敷處理系統可以組合分批式液處理槽而構成。此時，如圖3概略性表示般，鍍敷處理系統100具備氧化皮膜除去工程用之鹼洗淨槽102、污垢除去工程及Zn棒工程用之酸洗淨槽104、用以進行第1及第2鋅酸鹽工程之鋅酸鹽處理槽106、Co阻障層形成工程(第1次)用之Co無電解鍍敷槽108、上述各藥液處理工程之後的沖洗工程用之複數沖洗處理槽110。
各槽可以採用與在半導體裝置製造，尤其係 藥液洗淨、在濕蝕刻等之領域中廣泛被使用之分批式液處理槽相同的構成。即是，在各槽中，設置有在以豎立姿勢在水平方向隔著間隔保持複數片之基板10(半導體晶圓)之稱為晶舟等的基板保持具(無圖示)，在維持著基板保持具中之晶圓之配列狀態之狀態下，基板搬運機112之機械臂在各槽之基板保持具間進行基板10之搬運及收授。在藉由基板保持具被保持之狀態下，僅以預先設定之時間順序浸漬於被儲存於各槽之處理液(藥液、沖洗液、鍍敷液等)，對基板10實施上述各工程。
上述鍍敷處理系統100之全體之動作係藉由由電腦所構成之控制裝置120被控制。控制裝置120藉由讀出被記錄於記憶媒體122之各種程式而實行，控制鍍敷處理系統100之各部之動作，使實行上述各工程。記憶媒體122，儲存有為了實行上述一連串之工程所需要的製程配方及控制程式等之各種程式。作為記憶媒體122，可以使用以電腦能夠讀取之ROM或RAM等之記憶體裝置、硬碟、CD-ROM、DVD-ROM、軟碟等之碟片記憶媒體等之任意者。
即使使用一個或兩個以上之單片式之液處理單元(無圖示)，進行從上述氧化皮膜除去工程至Co阻障層形成工程(第1次)為止之一連串的處理亦可。單片式之液處理單元可以具備以水平姿勢保持基板10而使旋轉之旋轉夾具、對藉由旋轉夾具保持並旋轉之基板10供給上述藥液、沖洗液、鍍敷液等之處理液的噴嘴而構成。 即使藉由一個液處理單元進行從上述氧化皮膜除去工程至Co阻障層形成工程(第1次)為止之一連串的處理亦可，即使使複數之液處理單元分擔進行亦可。
12‧‧‧凹部(TSV)
22‧‧‧Al層(Al配線層)
30‧‧‧鋅酸鹽皮膜
14a(14)‧‧‧第1無電解鍍敷層(Co阻障層)
14b(14)‧‧‧第2無電解鍍敷層(Co阻障層)
16‧‧‧Cu鍍敷(Cu配線層)
32‧‧‧觸媒層
26‧‧‧矽基板
28‧‧‧TEOS層

Claims (6)

  1. 一種鍍敷處理方法，具備：準備在表面露出有由鋁或鋁合金所構成之Al層之基板的工程；之後，對上述基板施予鋅酸鹽處理，在上述Al層之表面形成鋅酸鹽皮膜之工程；及之後，使用鹼性且包含錯合劑之無電解鍍敷液，而在上述Al層之上述表面形成第1無電解鍍敷層之第1無電解鍍敷工程。
  2. 如請求項1所記載之鍍敷處理方法，其中上述第1無電解鍍敷層係由鈷或鈷合金所構成之Co鍍敷層。
  3. 如請求項2所記載之鍍敷處理方法，其中上述基板之上述表面具有凹部，上述Al層具有露出於上述凹部之底面之表面的Al配線層，第1無電解鍍敷工程係在露出於上述凹部之底面之上述Al配線層之表面形成上述第1無電解鍍敷層。
  4. 如請求項3所記載之鍍敷處理方法，其中更具備：於上述第1無電解鍍敷工程之後，在上述凹部之至少側面形成觸媒層之工程；及之後，在上述凹部之上述底面及上述側面，形成由鈷或鈷合金所構成之Co鍍敷層以作為第2無電解鍍敷層的第2無電解鍍敷工程。
  5. 如請求項4所記載之鍍敷處理方法，其中 更具備於上述第2無電解鍍敷工程之後，在上述凹部之內部埋入由銅或銅合金所構成之Cu鍍敷的工程。
  6. 一種記憶媒體，記錄有程式，該程式當藉由用以控制鍍敷處理系統之動作的電腦實行時，上述電腦控制上述鍍敷處理系統而實行請求項1至5中之任一項所記載之鍍敷處理方法。
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