CN1524292A - 集成电路制造中用于电解电镀和无电电镀金属的表面处理装置和方法 - Google Patents

集成电路制造中用于电解电镀和无电电镀金属的表面处理装置和方法 Download PDF

Info

Publication number
CN1524292A
CN1524292A CNA028118081A CN02811808A CN1524292A CN 1524292 A CN1524292 A CN 1524292A CN A028118081 A CNA028118081 A CN A028118081A CN 02811808 A CN02811808 A CN 02811808A CN 1524292 A CN1524292 A CN 1524292A
Authority
CN
China
Prior art keywords
layer
substrate
seed
metal
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA028118081A
Other languages
English (en)
Other versions
CN1319145C (zh
Inventor
智华・曾
智华·曾
希卡尔马内
维奈·希卡尔马内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1524292A publication Critical patent/CN1524292A/zh
Application granted granted Critical
Publication of CN1319145C publication Critical patent/CN1319145C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1619Apparatus for electroless plating
    • C23C18/1632Features specific for the apparatus, e.g. layout of cells and of its equipment, multiple cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/34Pretreatment of metallic surfaces to be electroplated
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76856After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888By rendering at least a portion of the conductor non conductive, e.g. oxidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Plasma & Fusion (AREA)
  • Sustainable Development (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemically Coating (AREA)

Abstract

在集成电路制造中,一种用于电解电镀或无电电镀金属的处理衬底表面的方法和装置。在一个实施例中,所述方法包括在衬底上形成阻挡层(16)。然后,在所述阻挡层上形成金属-晶种层(17)。为了在所述金属-晶种层(17)上形成钝化层(18),所述方法继续对所述金属-晶种层实施原位表面处理。在本发明的另一方法实施例中,将衬底提供进电镀工具室内。所述衬底具有在其上形成的阻挡层、在所述阻挡层上形成的金属晶种层和在所述金属晶种层上形成的钝化层。所述方法继续在合成气中退火所述衬底,以减少所述钝化层(18)。使用电解电镀或无电电镀工艺,在所述衬底上沉积导电材料。

Description

集成电路制造中用于电解电镀和无电电镀金属的表面处理装置和方法
技术领域
本发明涉及集成电路制造,更具体地涉及一种用于电解电镀或无电电镀金属或其他导电材料的衬底表面处理的装置和方法。
背景技术
现代集成电路(IC)使用导电互连(conductive interconnections)来连接芯片上的单个设备,或者发送和接收芯片外信号。普通类型的互连包括:耦合至单个设备的铝(Al)合金互连线和铜(Cu)互连线,包括其他互连线,通过通道(via)的互连。为了提高互连速度和可靠性,半导体制造企业正在放弃铝基金属化的覆盖沉积和蚀刻,转向铜基金属化的单重镶嵌和双重镶嵌互连结构。
镶嵌技术涉及:在介电材料中形成通向诸如晶体管或互连线这样的下层电路设备的通道和覆盖在其上的沟槽。然后,通道和沟槽内衬有难熔材料的阻挡层。阻挡层通常是为了抑制接着将在通道内形成的互连材料扩散进介电材料中。下一步,合适的晶种(seed)材料沉积在通道的壁上和底部上。用于沉积铜互连材料的合适的晶种材料包括铜和镍。晶种材料沉积后,在含有氩或氮的气氛中冷却晶片。下一步,使用例如电镀工艺,沉积足够量的诸如铜的这类互连材料来填充通道和沟槽。沉积互连材料后,使用化学机械抛光或者蚀刻工艺来移除沟槽外存在的任意互连材料。如果将互连金属同时填充沟槽和其下的通道,该工艺即双重镶嵌工艺。
随着IC设计扩展至亚微米范围,例如小于等于0.18微米,铜和铜基合金互连的可靠性对于合适的IC设备操作,则变得至关重要。常规的铜基金属化工艺生产充满凹点缺陷的晶片,而这最终导致IC设备可靠性不够。
附图说明
通过例子和附图来图解说明本发明,但并不限于这些附图:
图1a是半导体设备用的互连结构的横截面图,表示形成两个用于铺设线路线(wiring line)的沟槽,其中一个沟槽内具有用于互连至下部金属层的下层通道开口,被内层介电(ILD)层与形成的沟槽隔开。
图1b是图1a中的结构的横截面图,其中在ILD上和沟槽开口和通道开口内形成阻挡层。
图1c是图1b中的结构的横截面图,其中在ILD上和沟槽开口和通道开口内形成的阻挡层上形成金属晶种层,例如铜晶种层。
图1d是图1c中的结构的横截面图,为了钝化金属晶种层表面,在阻挡-晶种工具沉积室内原位表面处理了图1c中的结构。
图1e是图1d中的结构的横截面图,为了移除金属晶种层上形成的任何杂质,在电镀工具附带的退火室内晶种退火图1d中的结构。
图1f是图1e中的结构的横截面图,其中在已退火的金属晶种层上无电沉积或电解沉积金属或其他导电材料。
图1g是图1f中的结构的横截面图,其中无电沉积或电解沉积在ILD上的的多余金属被移除,例如铜。
图2a是根据本发明的实施例,在沉积金属晶种层之后,处理图案化的和/或裸露的衬底表面的工艺。
图2b是根据本发明的实施例,在图2a中示出的处理工艺后,实施一体化的晶种退火和对图案化的和/或裸露的衬底表面电镀的工艺。
图3a示意性地示出了一个本发明的用于原位衬底表面处理的装置的典型实施例。
图3b示意性地示出了一个本发明的用于一体化的晶种退火/电解电镀或无电电镀金属或其他导电材料的的装置的典型实施例。
具体实施方式
这里描述了一种为了电解电镀或无电电镀金属或其他导电材料而实施衬底表面处理的装置和方法。相对于当前的铜基金属化工艺,本发明的装置和方法具有显著的优点,例如包括:大大降低或消除了电解电镀或无电电镀后的缺陷;改善了润湿和促进了无砂眼电解电镀或无电电镀填充高宽比(aspect ratio)较高的通道和沟槽;通过实施原位处理金属晶种层,减少了IC处理成本;提高了可靠性。
在下面的详细描述中,为了提供对本发明的更彻底的理解,提到许多具体细节,例如具体材料、结构、化学制品、工艺等。然而,对于本发明相关的领域的技术人员,显然没有这些具体细节也可以实施本发明。在其他情况下,为了防止不必要地混淆本发明的有关方面,公知的设备、方法、工序和单个组件都没有详细描述。
现在参考附图,其中相同单元用同样的标记表示,图1a-1g和图2a和2b示出了本发明中的用于电解电镀或无电电镀金属或其他导电材料的衬底表面处理的实施例,其中金属或其他导电材料用来制造具有金属互连的集成电路。图1a-1g是在图2a和图2b中示出的制造工艺的实施例的过程中各个阶段的半导体结构的示意性横截面图。与图1a-1d相关的图2a,表示本发明的工艺实施例:沉积金属晶种层之后,处理图案化的(patterned)和/或裸露的衬底表面,以使金属晶种层上形成保护钝化层,例如金属晶种氧化物层或金属晶种氮化物层。与图1e-1g相关的图2b表示本发明的工艺实施例:在图2a中示出的处理工艺之后,实施一体化的晶种退火和对图案化的和/或裸露的衬底表面电镀。
原位表面处理
图1a示出了具有在硅衬底20上并被ILD层12所覆盖的金属层11的示例性半导体衬底结构10。金属层11代表多金属级半导体设备的其中一个金属层。层12是通常的ILD层,用于分隔不同的金属层。通过化学气相沉积(CVD)、物理气相沉积(PVD)或者其他适合的方法,可以在结构10上形成ILD层12,它可以由诸如硼磷硅酸盐玻璃(BPSG)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、二氧化硅、掺氟氧化物、低介电常数材料或者旋压介电材料一类的材料组成。
应该理解的是,结构10仅是半导体晶片上存在的许多结构的一部分。随着在沟槽14下的用于互连至下部金属层11的通道开口13的形成,沟槽14和15也在结构10中形成。利用本领域公知的单重或双重镶嵌工艺可以制造结构10或类似结构。
参考图1a和2a,工艺开始,为了在衬底结构上形成阻挡层,向例如铜-阻挡晶种沉积工具310(图2a中方框210)的半导体设备处理第一工具310(图3a中示出)中提供衬底结构10。如后面详细讨论的,铜-阻挡晶种沉积工具一般包括几个室,其中在不破坏真空的条件下实施衬底处理。衬底结构10的表面可以是裸露的,例如,衬底结构10仅包括衬底20。在另一个实施例中,衬底结构10可以包括衬底20,衬底20具有金属层11和/或至少一个ILD层12上图案化了的沟槽14、15和通道13。衬底结构10的其他构造或设置也在本发明的范围内。
参考图1b和2a,在一个实施例中,在ILD层12上和沟槽开口14、15和通道开口13内形成阻挡层16,以使阻挡层16覆盖在ILD层12上和衬在沟槽14、15和通道13的内部(图2a的方框220)。为了优化互连性能和防止金属互连材料扩散进衬底内,金属互连材料通常与阻挡层一起使用,例如阻挡层16。
阻挡层16可以由钽(Ta)、氮化钽(TaN)、钛(Ti)、氮化钛(TiN)、氮化钨(WN)、钨-钽(WTa)、氮化钽硅或其他三元化合物形成。然而,可以理解,实施本发明中,其他材料也可用于阻挡层16。利用公知的膜沉积技术,例如CVD、PVD、电解电镀或无电电镀,来形成阻挡层16。如果阻挡层16是TiN,那么可以使用CVD或PVD来沉积TiN。如果阻挡层16是Ta,那么可以使用PVD来进行Ta的保形沉积(conformal deposition)。实施PVD的普通常例是通过喷镀。一般,阻挡层16沉积厚度在约150-300埃的范围内,然而,其他阻挡厚度也可以在本发明的范围内实施。在一个实施例中,阻挡层16沉积厚度约为200埃。
参考图1c和2a,工艺继续,在覆盖在ILD层12和衬在沟槽14、15和通道13内部的阻挡层16上形成金属晶种层17,例如铜-晶种层17(图2a的方框230)。金属晶种层17可以通过使用下列材料来沉积或形成:金属、金属合金、金属化合物、多层金属或使被用于在沟槽和通道内形成互连的金属能够成核和生长的任意衬底。一般,金属晶种层17由金属或金属合金组成,可以包括、但并不限于铜、铜合金、镍、银、金和钴。
当衬底结构10还在例如铜阻挡-晶种沉积工具310的第一半导体设备处理工具310(图3a中示出)内时,利用定向沉积技术,沉积/形成金属晶种层17。定向沉积技术,是本领域公知的,包括:有或无偏差电压的对准喷镀、等离子加强化学气相沉积和离子化物理气相沉积。一般,晶种层17沉积厚度在约1000-3000埃的范围内。在一个实施例中,晶种层17沉积厚度约为2000埃。
参考图1d和2a,工艺继续,在衬底上电解电镀/无电电镀导电材料之前,物理或化学处理金属晶种层。一般,在电解电镀/无电电镀导电材料之前,使用液体或具有化学活性或惰性的气体,原位(in-situ)或异位(ex-situ)完成物理和/或化学处理金属晶种层17。例如,在一个实施例中,金属晶种层表面17可以暴露在本领域公知的一定温度和浓度范围的气体中,如氩气(Ar)、氦气(He)、氧气(O2)、氢气(H2)、氢气和氦气、氢气和氮气(N2)、氢气和氩气等。在另一实施例中,在衬底结构10的沟槽14、15和通道13内电解电镀/无电电镀导电材料之前,金属晶种层表面17暴露在液态介质中,如酸、碱、溶剂和去离子水。
在本发明的一个实施例中,为了在金属晶种层17上形成晶种钝化层18,例如金属氧化物层18,通过对衬底结构10实施原位晶种表面钝化(或金属晶种层处理),完成金属晶种层17的处理,其中衬底结构10上具有金属晶种层17和阻挡层16(图2a中方框240)。当衬底结构10还在金属阻挡-晶种沉积工具310的一个室内时(图3a中示出),实施原位晶种表面钝化(或晶种处理)。根据本发明的一个实施例,为了实施原位晶种表面钝化(或晶种处理),在第一特定时间段t1内,第一衬底处理工具(例如铜-阻挡晶种沉积工具)的含有衬底结构10的室内填充气体。气体环境可以包括,但并不限于惰性气体、氢气、含氟气体、合成气体、氧气、氮气等。然后,为了在金属晶种层17上形成钝化层18,例如,金属氧化物层18,在第二特定时间t2内,在低压室内,特定温度T下,其上具有金属晶种层17和阻挡层16的衬底结构10在气体(例如,氧气)环境中冷却。一般,在金属晶种层17上形成的钝化层18的厚度在约5-100埃的范围内。
根据本发明的一个实施例,在第一特定时间t1约15-25秒内,优选约20秒内,铜-阻挡晶种沉积工具的低压室内填充在约2托的压力下流动的纯氧气。在第二特定时间t2约5-15秒内,优选约10秒内,在压力约为2托、特定温度T约为15-20℃的范围内低压室内的纯氧气流动环境中,冷却其上具有金属晶种层17和阻挡层16的衬底结构10。一般,在以上的条件下,形成厚度在约5-100埃的范围内的金属氧化物层18,例如氧化铜18。本领域的技术人员将认识到,根据金属晶种层使用的材料类型、引入室内的气体类型、设备规格、制造偏好以及其他考虑,可以修改工艺方法的特征/参数,例如,第一特定时间t1、第二特定时间t2、温度T、铜-阻挡晶种沉积工具室内的压力等。
在铜-阻挡晶种沉积工具内原位处理衬底表面后,衬底/晶片暴露在空气中,等待在电镀工具上的处理。
应该注意的是,当在阻挡层16上使用铜形成金属晶种层,且使用氧作为室内气体时,铜-晶种层17的原位晶种钝化(或晶种表面处理)形成一层氧化铜(CuO2)。因为该CuO2层是在阻挡-晶种沉积工具的高真空室内形成的,例如生长,所以该CuO2层18下没有杂质。当从金属-阻挡晶种沉积工具移出衬底结构10,暴露在大气条件下时,杂质(可以包括另一CuO2层18)通常将沉积在真空条件下形成的CuO2层18上面。因此,真空条件下形成的CuO2层18是充当衬底结构10及其金属晶种层17的保护覆盖层的。
一体化的晶种退火-无电/电解电镀
现在转向图1e-1g和2b,它们图解说明了图2a中示出的衬底表面处理工艺后,实施一体化的晶种退火和对图案化的和/或裸露的衬底表面电镀的本发明的工艺实施例。因为在下面的段落(图2b的方框250-270)中描述的作业是在例如电镀工具320(图3b中示出)的同一处理工具320内实施的,所以该工艺是一体化(integrated)的。
参考图1e和2b,金属晶种层的原位(或异位)晶种表面钝化后,例如在铜阻挡-晶种沉积工具内原位表面钝化铜基晶种层后,具有在结构ILD12的沟槽14、15和通道13内形成的阻挡层16、例如铜-晶种层17的金属晶种层17和例如铜-晶种氧化层18(CuO2)的金属晶种钝化层18的衬底结构/晶片10被提供至例如电镀工具320的第二半导体设备处理工具320的杂质移除室322内,例如,退火室322(图3b中示出)内(图2b的方框250)。在电镀工具的杂质移除室或退火室内,为了去除或减少晶种钝化层18,如金属晶种氧化物层18,而且也为了去除或减少衬底上的任意杂质,在合成气中退火衬底结构10(图2b的方框260)。
一般,金属晶种退火工艺包括:在第三特定时间t3内,在特定晶种退火温度T晶种退火下,合成气或其他气体混合物流进电镀工具的杂质移除或退火室内。在本发明的一个实施例中,晶种退火工艺使用的合成气包括95%氮气(N2)和5%氢气(H2),在第三特定时间t3约30秒内,在特定晶种退火温度T晶种退火为约250℃下流进晶种退火室。在一个实施例中,N2以每分钟约19标准升(slm)的流速进入退火室,而H2以约1slm的流速进入退火室。
晶种退火工艺(图2b中的方框260)还包括:在第四特定时间t4内,在晶种退火冷却温度T晶种退火冷却下,在合成气或其他气体混合物中冷却已退火的衬底结构10。在本发明的一个实施例中,在95%N2和5%H2的合成气中冷却衬底结构包括:在第四特定时间t4约25秒内,合成气在约15-20℃的晶种退火冷却温度T晶种退火冷却下流进晶种退火室。N2一般以约19slm的流速进入退火室,而H2以约1slm的流速注入退火室。
参考图1f和2b,金属晶种退火工序后,为了将导电材料19,如金属或合金,沉积进衬底结构10的沟槽14、15、通道13和覆盖层21内,通过对衬底结构10实施无电电镀或电解电镀,继续一体化的晶种退火/电镀工艺(图2b中的方框270)。被沉积的导电材料将形成用于与下部金属层11互连的金属互连22。
用来形成金属互连22的无电电镀和电解电镀工艺是本领域公知的。
电解电镀包括:根据以下的一般原理:
通过阴极还原沉积来自电解液的金属。
一般,衬底/晶片是阴极终端(阴极),其上发生金属沉积。外加电源为阴极提供电子。
无电电镀包括通过化学还原,沉积来自电解液的金属。电解液中的还原剂(如,Red)是电子的来源。衬底/晶片是催化表面,根据以下的一般原理,其上发生金属沉积:
在本发明的实施例中,为了形成金属互连,可以利用电镀或无电电镀技术,将导电材料沉积进衬底结构10的沟槽14、15、通道13和覆盖层21。使用硫酸铜(结果是镀铜)、硝酸银(结果是镀银)或氰化金(结果是镀金)溶液可以完成电镀。作为示例,在常规的铜电镀工艺中,通过在溶液存在的条件下,在晶种材料层17和电镀单元阳极之间施加电流,在pH值为中性的铜基溶液中,例如基于硫酸铜的溶液中的金属离子可以被还原为金属态。金属铜沉积在晶种材料层17上,从而填塞沟槽14、15和通道13,形成铜互连线22。
作为示例,在无电电镀铜工艺中,通过将衬底结构/晶片10浸渍在渡槽中,或者向结构/晶片10上喷射镀液的方法,衬底结构/晶片10暴露在第一镀液中。第一镀液是酸的水溶液,如氢氟酸或硫酸,和可以溶解在所用酸中的金属盐或化合物。溶液中的金属离子之间发生氧化还原反应,例如,铜离子(Cu2+)和还原剂,还原剂导致金属离子还原,接着镀在铜晶种层17上。反应通常在室温下进行一段时间,直至形成导电互连/级。根据影响反应速度的需要,可以调整时间和温度,这是本领域公知的。
参考图1g和2b,作为可选作业,无电电镀或电解电镀衬底结构10之后,可以实施化学机械抛光(CMP)工艺或化学蚀刻移除工艺。CMP或化学蚀刻移除法磨光或者移除ILD层12上多余的铜材料19和阻挡层17,以便在沟槽14、15和通道13中仅余下铜和阻挡层(图1g中示出)。
转向图3a和3b,图中示意性地说明了根据本发明,用于实施原位或异位晶种表面处理(图3a中系统310)和用于实施一体化的晶种退火和电解电镀或无电电镀金属或其他导电材料(图3b中系统320)的系统的示例性实施例。
参考图3a,一般,系统310是金属阻挡晶种沉积工具310,如铜-阻挡晶种沉积工具310。铜-阻挡晶种沉积工具310可以有各种构造和设置,这取决于使用的衬底制造工艺、制造偏好等。在示例性的实施例中,铜-阻挡晶种沉积工具310包括图2a中说明的各个阶段的工艺使用的多个室312、314、316、318。例如,铜-阻挡晶种沉积工具310的室312可作为阻挡层沉积室,而真空室314可作为例如铜晶种层的金属晶种层的沉积室。室316可以是铜-阻挡晶种沉积工具(CBS)310中的冷却室,用于在真空条件下实施原位表面处理晶种层,以形成钝化层,例如金属晶种氧化物层。室318充当铜阻挡晶种沉积工具310的负荷锁定室。
参考图3b,一般,系统320是电镀工具320。电镀工具320也可以有各种构造和设置,这取决于使用的衬底制造工艺、制造偏好等。在示例性实施例中,电镀工具320包括图2b中说明的工艺的各个阶段使用的多个室322、324、326。例如,电镀工具320的室322可以是杂质移除室,例如晶种退火室,用来减少或消除晶种钝化层,例如在铜阻挡晶种沉积工具310的室316内形成的金属晶种氧化物层。为了将合成气导入室322中,以移除或减少晶种钝化层和任意吸收的杂质,气体传输系统350可以耦合至电镀工具320。室324可以是示例性电镀室,而室326可以作为加载/卸载晶片盒室。如上所述,电镀工具320的设置允许实施单个晶片/衬底的一体化的金属晶种退火/电镀工艺。
因而,这里描述了一种用于电解电镀或无电电镀金属或其他导电材料的衬底表面处理的方法和装置。虽然这里描述的是特定实施例,包括特定设备、参数、方法和材料,本领域的普通技术人员在阅读本公开的基础上,显然可以对已公开的实施例进行各种改进。因此,应该理解的是,该实施例仅仅是说明性的,而非限制本发明,并且本发明并不限于已经示出和描述的特定实施例。

Claims (30)

1.一种方法,包括:
向第一工具的一个室内提供衬底结构;
在所述衬底结构上形成阻挡层;
在所述阻挡层上形成金属晶种层;
对其上具有所述金属晶种层和所述阻挡层的所述衬底结构实施原位表面处理,在所述金属晶种层上形成钝化层。
2.如权利要求1所述的方法,其中原位表面处理在气体环境中实施,所述气体环境选自由惰性气体、氢气、含氟气体、合成气、氧气和氮气组成的组。
3.如权利要求1所述的方法,其中原位表面处理使用液体实施,所述液体选自由酸、碱、溶剂和去离子水组成的组。
4.如权利要求2所述的方法,其中在氧气环境中实施原位表面处理,在所述金属晶种层上形成金属氧化物层。
5.如权利要求1所述的方法,其中所述金属晶种层选自由铜、铜合金、镍、银、金和钴组成的组。
6.如权利要求1所述的方法,其中所述阻挡层选自由钽、氮化钽、钛、氮化钛、氮化钨、钨-钽和氮化钽硅组成的组。
7.如权利要求1所述的方法,其中第一工具是金属-阻挡晶种沉积工具。
8.如权利要求1所述的方法,其中实施原位表面处理包括:
第一特定时间段,向所述第一工具的室内填充气体,和
第二特定时间段,在特定温度下,在所述室内,冷却其上具有所述金属晶种层和所述阻挡层的所述衬底结构,在所述金属晶种层上形成钝化层。
9.如权利要求8所述的方法,其中所述第一特定时间段在约15-25秒的范围内。
10.如权利要求8所述的方法,其中所述第二特定时间段在约5-15秒的范围内。
11.如权利要求8所述的方法,其中所述特定温度是约15-20℃。
12.如权利要求8所述的方法,其中所述气体包括压力直到2托的氧气。
13.如权利要求1所述的方法,还包括将具有所述阻挡层、所述金属晶种层和所述钝化层的所述衬底结构提供至电镀工具的杂质移除室内。
14.如权利要求13所述的方法,还包括在合成气中退火所述衬底,以减少所述钝化层。
15.如权利要求14所述的方法,其中退火包括第三特定时间段,在约250℃的晶种退火温度下,合成气流进所述退火室。
16.如权利要求15所述的方法,其中退火还包括第四特定时间段,在约15-20℃的晶种退火冷却温度下,在合成气中冷却所述已退火的衬底。
17.如权利要求15所述的方法,其中所述第三特定时间段为约30秒。
18.如权利要求16所述的方法,其中所述第四特定时间段为约25秒。
19.如权利要求14所述的方法,其中所述合成气包括约95%氮气和5%氢气。
20.如权利要求14所述的方法,还包括使用选自电解电镀和无电电镀的组的镀法,至少在所述衬底上图案化的沟槽和通道内沉积导电材料。
21.如权利要求20所述的方法,其中所述导电材料选自由铜、银和金组成的组。
22.一种方法,包括:
向电镀工具内提供衬底,所述衬底上具有图案化的至少一个沟槽和至少一个通道、在所述沟槽和所述通道内形成的阻挡层、在所述阻挡层上形成的金属晶种层和在所述金属晶种层上形成的钝化层;
在合成气中退火所述衬底,以减少所述钝化层;和
使用选自由电解电镀和无电电镀组成的组的镀法,至少在所述衬底上的所述沟槽和所述通道内部沉积导电材料。
23.如权利要求22所述的方法,其中在所述电镀工具内,在真空条件下,按顺序为一批衬底的每一个衬底实施退火和沉积。
24.如权利要求22所述的方法,其中退火包括第三特定时间段,在约250℃的晶种退火温度下,合成气流进所述电镀工具的杂质移除室内。
25.如权利要求22所述的方法,其中退火还包括第四特定时间段,在约15-20℃的温度下,在合成气中冷却所述已退火的衬底。
26.如权利要求24所述的方法,其中所述第三特定时间段约30秒。
27.如权利要求25所述的方法,其中所述第四特定时间段约25秒。
28.一个系统,包括:
至少一个杂质移除室,用于对衬底实施晶种退火,所述衬底上具有图案化的至少一个沟槽和至少一个通道、在所述沟槽和所述通道内形成的阻挡层、在所述阻挡层上形成的金属晶种层和在所述金属晶种层上形成的晶种钝化层;
耦合至至少一个杂质移除室的气体传输系统,用于将合成气引入所述杂质移除室,以减少所述晶种钝化层;和
耦合至所述的至少一个杂质移除室和所述气体传输系统的至少一个电镀室,所述的至少一个电镀室用于使用选自由电解电镀和无电电镀组成的组的镀法,至少在所述衬底上的所述沟槽和所述通道内部沉积导电材料。
29.如权利要求28所述的系统,其中在所述电镀工具内,在真空条件下,按顺序为一批衬底的每一个衬底实施晶种退火和沉积导电材料。
30.如权利要求28所述的系统,其中所述气体传输系统将在约250℃的第三温度下的热合成气引入所述杂质移除室约30秒,然后将在约20℃的第四温度下的冷合成气引入所述杂质移除室约25秒。
CNB028118081A 2001-08-14 2002-07-12 一种集成电路衬底表面处理装置和方法 Expired - Fee Related CN1319145C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/929,213 2001-08-14
US09/929,213 US7070687B2 (en) 2001-08-14 2001-08-14 Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing

Publications (2)

Publication Number Publication Date
CN1524292A true CN1524292A (zh) 2004-08-25
CN1319145C CN1319145C (zh) 2007-05-30

Family

ID=25457490

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028118081A Expired - Fee Related CN1319145C (zh) 2001-08-14 2002-07-12 一种集成电路衬底表面处理装置和方法

Country Status (5)

Country Link
US (1) US7070687B2 (zh)
EP (1) EP1417706A2 (zh)
CN (1) CN1319145C (zh)
TW (1) TW559901B (zh)
WO (1) WO2003023848A2 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100576530C (zh) * 2005-10-07 2009-12-30 国际商业机器公司 包含氧/氮过渡区的电镀种子层和互连结构及其形成方法
CN101563758B (zh) * 2006-12-18 2011-06-01 朗姆研究公司 用于阻障层表面钝化的方法和系统
CN104099653A (zh) * 2013-11-12 2014-10-15 南茂科技股份有限公司 半导体结构及其制造方法
CN111630654A (zh) * 2018-02-01 2020-09-04 东京毅力科创株式会社 多层配线的形成方法和存储介质

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6764940B1 (en) 2001-03-13 2004-07-20 Novellus Systems, Inc. Method for depositing a diffusion barrier for copper interconnect applications
US8298933B2 (en) 2003-04-11 2012-10-30 Novellus Systems, Inc. Conformal films on semiconductor substrates
US7842605B1 (en) 2003-04-11 2010-11-30 Novellus Systems, Inc. Atomic layer profiling of diffusion barrier and metal seed layers
US6860944B2 (en) * 2003-06-16 2005-03-01 Blue29 Llc Microelectronic fabrication system components and method for processing a wafer using such components
US7883739B2 (en) 2003-06-16 2011-02-08 Lam Research Corporation Method for strengthening adhesion between dielectric layers formed adjacent to metal layers
US6881437B2 (en) * 2003-06-16 2005-04-19 Blue29 Llc Methods and system for processing a microelectronic topography
WO2004114386A2 (en) * 2003-06-16 2004-12-29 Blue29 Corporation Methods and system for processing a microelectronic topography
US20040256240A1 (en) * 2003-06-20 2004-12-23 Nelsen David C. System and process to control electroplating a metal onto a substrate
CN1308495C (zh) * 2003-08-29 2007-04-04 中芯国际集成电路制造(上海)有限公司 铜电镀薄膜方法
US20050147746A1 (en) * 2003-12-30 2005-07-07 Dubin Valery M. Nanotube growth and device formation
AU2004312893B2 (en) 2003-12-31 2010-06-17 President And Fellows Of Harvard College Assay device and method
US7112540B2 (en) * 2004-01-28 2006-09-26 Texas Instruments Incorporated Pretreatment for an electroplating process and an electroplating process in including the pretreatment
US7235487B2 (en) * 2004-05-13 2007-06-26 International Business Machines Corporation Metal seed layer deposition
US7166543B2 (en) * 2004-08-30 2007-01-23 Micron Technology, Inc. Methods for forming an enriched metal oxide surface for use in a semiconductor device
US7098128B2 (en) * 2004-09-01 2006-08-29 Micron Technology, Inc. Method for filling electrically different features
KR100618343B1 (ko) * 2004-10-28 2006-08-31 삼성전자주식회사 패키징 기판의 제조방법 및 이를 이용한 패키징 방법.
US7129177B2 (en) * 2004-10-29 2006-10-31 Hitachi Global Storage Technologies Netherlands B.V. Write head fabrication by inverting order of process steps
KR100652317B1 (ko) * 2005-08-11 2006-11-29 동부일렉트로닉스 주식회사 반도체 소자의 금속 패드 제조 방법
US20070037389A1 (en) * 2005-08-11 2007-02-15 Shu-Jen Chen Method for electroless plating metal cap barrier on copper
JP2007150176A (ja) * 2005-11-30 2007-06-14 Sharp Corp 半導体装置及びその製造方法
JP4746443B2 (ja) * 2006-02-27 2011-08-10 株式会社東芝 電子部品の製造方法
JP2007305640A (ja) * 2006-05-09 2007-11-22 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US7645696B1 (en) * 2006-06-22 2010-01-12 Novellus Systems, Inc. Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer
US7510634B1 (en) * 2006-11-10 2009-03-31 Novellus Systems, Inc. Apparatus and methods for deposition and/or etch selectivity
KR100835839B1 (ko) * 2006-11-27 2008-06-05 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
US20080264774A1 (en) * 2007-04-25 2008-10-30 Semitool, Inc. Method for electrochemically depositing metal onto a microelectronic workpiece
WO2009045316A1 (en) * 2007-10-03 2009-04-09 Sifco Selective Plating Method of plating metal onto titanium
DE102009015718B4 (de) * 2009-03-31 2012-03-29 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Testsystem und Verfahren zum Verringern der Schäden in Saatschichten in Metallisierungssystemen von Halbleiterbauelementen
US8835308B2 (en) * 2010-12-21 2014-09-16 Applied Materials, Inc. Methods for depositing materials in high aspect ratio features
US9865501B2 (en) * 2013-03-06 2018-01-09 Lam Research Corporation Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer
WO2015035066A1 (en) 2013-09-04 2015-03-12 President And Fellows Of Harvard College Growing films via sequential liquid/vapor phases
US20160276156A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing process thereof
WO2017081797A1 (ja) 2015-11-12 2017-05-18 三菱電機株式会社 Cuめっきの形成方法、Cuめっき付き基板の製造方法、および、Cuめっき付き基板
JP6594768B2 (ja) 2015-12-25 2019-10-23 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置、プログラムおよび記録媒体
JP6561001B2 (ja) * 2016-03-09 2019-08-14 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置、ガス供給系およびプログラム
US10443146B2 (en) 2017-03-30 2019-10-15 Lam Research Corporation Monitoring surface oxide on seed layers during electroplating
WO2019066900A1 (en) * 2017-09-29 2019-04-04 Intel Corporation APPARATUS WITH SUBSTRATE FORMED BY AUTOCATALYTIC METAL DEPOSITION USING POLYELECTROLYTES FOR ADSORING METALLIC IONS IN THE SUBSTRATE
US11430692B2 (en) * 2020-07-29 2022-08-30 Taiwan Semiconductor Manufacturing Company Limited Thermally stable copper-alloy adhesion layer for metal interconnect structures and methods for forming the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5891513A (en) * 1996-01-16 1999-04-06 Cornell Research Foundation Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications
US5918150A (en) * 1996-10-11 1999-06-29 Sharp Microelectronics Technology, Inc. Method for a chemical vapor deposition of copper on an ion prepared conductive surface
CA2572499A1 (en) * 1997-04-04 1998-10-15 University Of Southern California Method for electrochemical fabrication including use of multiple structural and/or sacrificial materials
US6565729B2 (en) * 1998-03-20 2003-05-20 Semitool, Inc. Method for electrochemically depositing metal on a semiconductor workpiece
US6048445A (en) * 1998-03-24 2000-04-11 Intel Corporation Method of forming a metal line utilizing electroplating
US6319728B1 (en) 1998-06-05 2001-11-20 Applied Materials, Inc. Method for treating a deposited film for resistivity reduction
US6461675B2 (en) * 1998-07-10 2002-10-08 Cvc Products, Inc. Method for forming a copper film on a substrate
US6169024B1 (en) * 1998-09-30 2001-01-02 Intel Corporation Process to manufacture continuous metal interconnects
US6242349B1 (en) * 1998-12-09 2001-06-05 Advanced Micro Devices, Inc. Method of forming copper/copper alloy interconnection with reduced electromigration
US6221763B1 (en) * 1999-04-05 2001-04-24 Micron Technology, Inc. Method of forming a metal seed layer for subsequent plating
US6103624A (en) * 1999-04-15 2000-08-15 Advanced Micro Devices, Inc. Method of improving Cu damascene interconnect reliability by laser anneal before barrier polish
US6037258A (en) * 1999-05-07 2000-03-14 Taiwan Semiconductor Manufacturing Company Method of forming a smooth copper seed layer for a copper damascene structure
US6147404A (en) * 1999-05-24 2000-11-14 Advanced Micro Devices, Inc. Dual barrier and conductor deposition in a dual damascene process for semiconductors
US6159857A (en) * 1999-07-08 2000-12-12 Taiwan Semiconductor Manufacturing Company Robust post Cu-CMP IMD process
US6355153B1 (en) * 1999-09-17 2002-03-12 Nutool, Inc. Chip interconnect and packaging deposition methods and structures
US6423200B1 (en) * 1999-09-30 2002-07-23 Lam Research Corporation Copper interconnect seed layer treatment methods and apparatuses for treating the same
US6395642B1 (en) * 1999-12-28 2002-05-28 Taiwan Semiconductor Manufacturing Company Method to improve copper process integration
US7253124B2 (en) * 2000-10-20 2007-08-07 Texas Instruments Incorporated Process for defect reduction in electrochemical plating
US6498397B1 (en) * 2000-11-06 2002-12-24 Advanced Micro Devices, Inc. Seed layer with annealed region for integrated circuit interconnects
US6554914B1 (en) * 2001-02-02 2003-04-29 Novellus Systems, Inc. Passivation of copper in dual damascene metalization

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100576530C (zh) * 2005-10-07 2009-12-30 国际商业机器公司 包含氧/氮过渡区的电镀种子层和互连结构及其形成方法
CN101563758B (zh) * 2006-12-18 2011-06-01 朗姆研究公司 用于阻障层表面钝化的方法和系统
CN102061470B (zh) * 2006-12-18 2013-06-19 朗姆研究公司 用于阻障层表面钝化的方法和系统
CN102061469B (zh) * 2006-12-18 2015-08-19 朗姆研究公司 用于阻障层表面钝化的方法和系统
CN104099653A (zh) * 2013-11-12 2014-10-15 南茂科技股份有限公司 半导体结构及其制造方法
CN104099653B (zh) * 2013-11-12 2015-10-28 南茂科技股份有限公司 半导体结构及其制造方法
CN111630654A (zh) * 2018-02-01 2020-09-04 东京毅力科创株式会社 多层配线的形成方法和存储介质

Also Published As

Publication number Publication date
TW559901B (en) 2003-11-01
EP1417706A2 (en) 2004-05-12
US7070687B2 (en) 2006-07-04
WO2003023848A2 (en) 2003-03-20
US20030034251A1 (en) 2003-02-20
WO2003023848A3 (en) 2003-06-19
CN1319145C (zh) 2007-05-30

Similar Documents

Publication Publication Date Title
CN1524292A (zh) 集成电路制造中用于电解电镀和无电电镀金属的表面处理装置和方法
KR100711526B1 (ko) 구리 연결선을 갖는 반도체 장치의 제조방법
CN100378954C (zh) 半导体元件及制造铜导线的方法
US6181013B1 (en) Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby
KR910009316B1 (ko) 실리콘 함유 금속층을 선택적으로 형성하는 방법
US7087516B2 (en) Electromigration-reliability improvement of dual damascene interconnects
US7405157B1 (en) Methods for the electrochemical deposition of copper onto a barrier layer of a work piece
US20060216930A1 (en) Post ECP multi-step anneal/H2 treatment to reduce film impurity
EP1778896A1 (en) Method of barrier layer surface treatment to enable direct copper plating on barrier metal
US6495453B1 (en) Method for improving the quality of a metal layer deposited from a plating bath
EP1069213A2 (en) Optimal anneal technology for micro-voiding control and self-annealing management of electroplated copper
US7442267B1 (en) Anneal of ruthenium seed layer to improve copper plating
US20060091551A1 (en) Differentially metal doped copper damascenes
US6998337B1 (en) Thermal annealing for Cu seed layer enhancement
US6624074B1 (en) Method of fabricating a semiconductor device by calcium doping a copper surface using a chemical solution
KR20040033260A (ko) 반도체 장치의 제조 방법
KR100488223B1 (ko) 무전해 도금 방법, 매입형 배선, 및 매입형 배선 형성 방법
CN1965110A (zh) 能够在阻挡金属上直接镀铜的阻挡层表面处理的方法
EP1063696B1 (en) A method for improving the quality of a metal-containing layer deposited from a plating bath
US6621165B1 (en) Semiconductor device fabricated by reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface
KR100456259B1 (ko) 반도체 소자의 구리 배선 형성방법
KR100451767B1 (ko) 반도체 소자의 금속 배선 형성방법
KR100451766B1 (ko) 반도체 소자의 금속 배선 형성방법
KR100298648B1 (ko) 반도체 소자용 배선박막 형성방법
KR20050121576A (ko) 반도체 소자의 금속배선 형성방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070530

Termination date: 20100712