CN104099653B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
CN104099653B
CN104099653B CN201310680470.2A CN201310680470A CN104099653B CN 104099653 B CN104099653 B CN 104099653B CN 201310680470 A CN201310680470 A CN 201310680470A CN 104099653 B CN104099653 B CN 104099653B
Authority
CN
China
Prior art keywords
plating bath
prussiate
silver alloys
projection
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310680470.2A
Other languages
English (en)
Other versions
CN104099653A (zh
Inventor
郑世杰
卢东宝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipmos Technologies Inc
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Publication of CN104099653A publication Critical patent/CN104099653A/zh
Application granted granted Critical
Publication of CN104099653B publication Critical patent/CN104099653B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05576—Plural external layers being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11906—Multiple masking steps with modification of the same mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13564—Only on the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499—Material of the matrix
    • H01L2224/8159—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/8169—Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81699—Coating material
    • H01L2224/817—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81738—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81744—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/81862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

本发明提供一种用于制造一半导体结构的方法。该方法包括：在一半导体晶粒上形成一导电衬垫；在该导电衬垫上方形成一晶种层；在该晶种层上方界定一第一遮罩层；及在该第一遮罩层中形成一银合金凸块本体。该在该第一遮罩层中形成一银合金凸块本体包括以下操作：制备一第一基于氰化物的电镀浴；将该第一基于氰化物的电镀浴的一pH值控制在6至8的一范围内；将该半导体晶粒浸没至该第一基于氰化物的电镀浴中；及将0.1ASD至0.5ASD的一电镀电流密度施加至该半导体晶粒。

Description

半导体结构及其制造方法
技术领域
本发明为关于一种半导体结构及其制造方法。
背景技术
随着电子工业的近期进展，正开发具有高效能的电子组件，且因此存在对于小型化及高密度封装的需求。因此，必须更密集地封装用于将IC连接至主机板的内插物(interposer)。封装的高紧密化可归因于IC的I/O的数目的增大，且亦已使得用于与内插物进行连接的方法更为有效。
愈发普及的内插物技术中的一者为倒装芯片(Flip chip)结合。硅集成电路(IC)装置的制造处理流程中的倒装芯片装配由若干事实驱动。第一，当与习知线结合互连技术相关的寄生电感减小时，半导体装置的电效能可得以改良。第二，较之于线结合，倒装芯片装配在晶片与封装之间提供较高互连密度。第三，较之于线结合，倒装芯片装配消耗较少硅“占据面积”，且因此有助于节省硅区域且降低装置成本。及第四，当使用并行群式结合技术而非连续个别结合步骤时，可降低制造成本。
为了减小内插物的大小及其间距，已努力用金属凸块替换先前在倒装芯片结合中的基于焊料的互连球，尤其是努力藉由经修改的线球技术来产生金属凸块。通常，在半导体晶片的接触衬垫的铝层上产生金属凸块。随后，使用焊料将晶片附接至基板。该等金属凸块用于针对LCD、记忆体、微处理器及微波RFIC的应用的倒装晶片封装。
发明内容
本发明的一些实施例提供一种用于制造半导体结构的方法，该方法包括以下操作：在半导体晶粒上形成导电衬垫；在该导电衬垫上方形成晶种层；在该晶种层上方界定第一遮罩层；及在该第一遮罩层中形成银合金凸块本体。在该第一遮罩层中形成银合金凸块本体的操作包括：制备第一基于氰化物的电镀浴；将该第一基于氰化物的电镀浴的pH值控制在自6至8的范围内；将该半导体晶粒浸没至该第一基于氰化物的电镀浴中；及将自0.1ASD至0.5ASD的电镀电流密度施加至该半导体晶粒。
在本发明的一些实施例中，一种用于制造半导体结构的方法进一步包括：在于第一遮罩层中形成银合金凸块本体之后移除该遮罩层；及移除晶种层的不由该银合金凸块本体覆盖的部分。
在本发明的一些实施例中，在用于制造半导体结构的方法中制备第一基于氰化物的电镀浴包括以2ml/L至5ml/L的浓度将草酸盐及其盐引入至第一基于氰化物的电镀浴中。
在本发明的一些实施例中，在用于制造半导体结构的方法中制备第一基于氰化物的电镀浴包括将KAg(CN)2引入至第一基于氰化物的电镀浴中。
在本发明的一些实施例中，在用于制造半导体结构的方法中制备第一基于氰化物的电镀浴包括将KAu(CN)2引入至第一基于氰化物的电镀浴中。
在本发明的一些实施例中，在用于制造半导体结构的方法中将KAu(CN)2引入至第一基于氰化物的电镀浴中包括将KAu(CN)2的浓度控制在10wt％至60wt％的范围内。
在本发明的一些实施例中，制备第一基于氰化物的电镀浴进一步包括将K2Pd(CN)4及其盐引入至第一基于氰化物的电镀浴中。
在本发明的一些实施例中，将K2Pd(CN)4及其盐引入至第一基于氰化物的电镀浴中包括将K2Pd(CN)4的浓度控制在10wt％至30wt％的范围内。
在本发明的一些实施例中，用于制造半导体结构的方法进一步包括在摄氏200度至摄氏300度的温度下对银合金凸块本体进行退火。
在本发明的一些实施例中，用于制造半导体结构的方法进一步包括对银合金凸块本体进行退火历时30分钟至60分钟的持续时间。
在本发明的一些实施例中，用于制造半导体结构的方法进一步包括藉由电镀操作在银合金凸块本体的顶表面上方形成金属层。
在本发明的一些实施例中，用于藉由电镀操作制造在银合金凸块本体的顶表面上方具有金属层的半导体结构的方法包括将半导体晶粒浸没至包含KAu(CN)2的第二基于氰化物的电镀浴中。
在本发明的一些实施例中，用于制造半导体结构的方法进一步包括藉由电镀操作或无电极电镀操作形成覆盖银合金凸块本体的顶表面及侧壁的金属层。
在本发明的一些实施例中，在用于制造半导体结构的方法中形成覆盖银合金凸块本体的顶表面及侧壁的金属层包括：在晶种层上方形成经修整第一遮罩层；及在该经修整第一遮罩层中形成该金属层。
在本发明的一些实施例中，藉由无电极电镀操作形成覆盖银合金凸块本体的顶表面及侧壁的金属层包括将半导体晶粒浸没至包含KAu(CN)2的无电极电镀浴中。
在本发明的一些实施例中，用于制造半导体结构的方法进一步包括将第一基于氰化物的电镀浴的温度控制在摄氏40度至摄氏50度的范围内。
本发明的一些实施例提供一种用于制造膜上晶片(COF)半导体结构的方法。该方法包括：在一半导体晶粒上形成导电衬垫；在该导电衬垫上方形成晶种层；在该晶种层上方形成银合金凸块本体；将自0.1ASD至0.5ASD的电镀电流密度施加至该半导体晶粒；及将该银合金凸块本体结合至可挠性膜。在该晶种层上方形成银合金凸块本体的操作进一步包括：在自摄氏40度至摄氏50度的溶液温度下制备基于氰化物的电镀浴，其包含KAu(CN)2、KAg(CN)2及K2Pd(CN)4中的至少一者；将该基于氰化物的电镀浴的pH值控制在自6至8的范围内；及将该半导体晶粒浸没至该基于氰化物的电镀浴中。
在本发明的一些实施例中，在用于制造COF半导体结构的方法中将银合金凸块本体结合至可挠性膜包括将银合金凸块本体与可挠性膜上的焊料层之间的接面控制为处于或高于Sn-Ag共晶温度。
在本发明的一些实施例中，用于制造COF半导体结构的方法进一步包括在摄氏200度至摄氏300度的温度下对银合金凸块本体进行退火。
在本发明的一些实施例中，用于制造COF半导体结构的方法进一步包括对银合金凸块本体进行退火历时30分钟至60分钟的持续时间。
在本发明的一些实施例中，在用于制造COF半导体结构的方法中将银合金凸块本体结合至可挠性膜包括在银合金凸块本体与可挠性膜之间施加各向异性导电膜(ACF)。
在本发明的一些实施例中，用于制造COF半导体结构的方法进一步包括藉由电镀操作或无电极电镀操作在银合金凸块本体上方形成金属层。
本发明的一些实施例提供一种用于制造玻璃上晶片(COG)半导体结构的方法。该方法包括：在半导体晶粒上形成导电衬垫；在该导电衬垫上方形成晶种层；在该晶种层上方形成银合金凸块本体；将自0.1ASD至0.5ASD的电镀电流密度施加至该半导体晶粒；及将该银合金凸块本体结合至玻璃基板。在该晶种层上方形成银合金凸块本体进一步包括：制备基于氰化物的电镀浴，其包含KAu(CN)2、KAg(CN)2及K2Pd(CN)4中的至少一者；将该基于氰化物的电镀浴的pH值控制在自6至8的范围内；及将该半导体晶粒浸没至该基于氰化物的电镀浴中。
在本发明的一些实施例中，用于制造COG半导体结构的方法包括将KAu(CN)2在基于氰化物的电镀浴中的浓度控制在10wt％至60wt％的范围内。
在本发明的一些实施例中，用于制造COG半导体结构的方法包括将K2Pd(CN)4的浓度控制在10wt％至30wt％的范围内。
在本发明的一些实施例中，在用于制造COG半导体结构的方法中将银合金凸块本体结合至玻璃基板包括在银合金凸块本体与玻璃基板之间施加各向异性导电膜(ACF)。
在本发明的一些实施例中，用于制造COG半导体结构的方法进一步包括藉由电镀操作或无电极电镀操作在银合金凸块本体上方形成金属层。
在本发明的一些实施例中，在用于制造COG半导体结构的方法中藉由无电极电镀操作在银合金凸块本体上方形成金属层包括制备包含KAu(CN)2的无电极电镀浴。
在本发明的一些实施例中，用于制造COG半导体结构的方法进一步包括将无电极电镀浴的温度控制在摄氏80度至摄氏90度的范围内。
附图说明
当结合附图阅读时，可自以下详细描述最佳地理解本发明的态样。应强调，根据工业中的标准实务，各种特征不按比例绘制。实际上，为了论述的清楚起见，可任意增大或减小各种特征的尺寸。
图1为根据本发明的一些实施例的银合金凸块结构的横截面图；
图2为根据本发明的一些实施例的粒径分布曲线；
图3为根据本发明的一些实施例的银合金凸块结构的横截面图；
图4为根据本发明的一些实施例的具有银合金凸块结构的膜上晶片(COF)半导体结构的横截面图；
图5为根据本发明的一些实施例的展示于图4中的接头部分的放大视图；
图6为根据本发明的一些实施例的多层凸块结构的横截面图；
图7为根据本发明的一些实施例的具有多层凸块结构的膜上晶片(COF)半导体结构的横截面图；
图8为根据本发明的一些实施例的具有多层凸块结构的膜上晶片(COF)半导体结构的横截面图；
图9为根据本发明的一些实施例的展示于图7中的接头部分的放大视图；
图10为根据本发明的一些实施例的具有银合金凸块结构的玻璃上晶片(COG)半导体结构的横截面图；
图11为根据本发明的一些实施例的具有多层凸块结构的玻璃上晶片(COG)半导体结构的横截面图；
图12为根据本发明的一些实施例的具有多层凸块结构的玻璃上晶片(COG)半导体结构的横截面图；及
图13至图26展示根据本发明的一些实施例的制造银合金凸块结构及多层凸块结构的操作。
附图标识：
10   银合金凸块结构
20   银合金凸块结构
30   膜上晶片(COF)半导体结构
40   多层凸块结构
50   膜上晶片(COF)半导体结构
60   玻璃上晶片(COG)半导体结构
70   玻璃上晶片(COG)半导体结构
80   玻璃上晶片(COG)半导体结构
100  容器
100' 容器
100A 入口
100B 出口
101  银合金凸块本体
101A 侧壁
101B 顶表面
102  导电衬垫
103  钝化层
104  凸块下金属化(UBM)层
105  晶种层
107  金属层
109  第一遮罩层
109A 开口
110  第二遮罩层
111  阳极
112  阴极
113  电镀浴
115  无电极电镀浴
200  容器
201  热板
301  可挠性膜
301A 第一表面
301B 第二表面
302  导电层
303  点框
304  底部填充材料
305  阻焊剂图案
306  焊料层
307  点框
308  焊料层
401  玻璃基板
401A 第一表面
402  导电迹线
406  各向异性导电膜(ACF)
406A 塑胶球体
具体实施方式
在以下详细描述中，列出了若干特定细节以便提供对本发明的全面了解。然而，熟习此项技术者应了解，本发明可在无该等特定细节的情况下实施。在其他情形中，未对熟知方法、程序、组件及电路进行详细描述，以免混淆本发明。应理解，以下揭示内容提供用于建构各种实施例的不同特征的许多不同实施例或实例。下文描述组件及配置的特定实例以简化本发明。当然，此等仅为实例，而并不意欲为限制性的。
下文详细论述实施例的制作及使用。然而，应了解，本发明提供可在广泛多种特定内容脉络中体现的许多适用的发明性概念。所论述的特定实施例仅为说明制作及使用本发明的特定方式，而并不限制本发明的范畴。
在半导体封装的金属凸块技术当中，金凸块由于与此项技术中的材料特性及处理技术的类似性而最为风行。然而，高材料成本、较差结合可靠性及诸如低电导率及低热导率的不令人满意的材料特性仍为待解决的问题。制造金属凸块的替代成本节省方法为藉由产生多层凸块，例如，Cu(底部层)、Ni(中间层)及Au(顶部层)凸块。此方法节省金属凸块的金材料消耗，但铜底部层易受氧化及腐蚀，且因此产生可靠性忧虑。
当藉由回焊已沉积在衬垫上的焊料而将金凸块接合至基板衬垫时，形成数个金/锡金属间物(intermetallics)。因为金在熔融焊料中的高溶解率，具有金凸块的焊料接头在一次回焊之后具有大体积分率的金属间化合物(其中AuSn4为主要相)，其使接头大大变脆。在两次或两次以上回焊(对于装配迭层封装产品通常为需要的)之后，金凸块可能完全耗尽且转化成金/锡金属间化合物。由于此等化合物及金属间物与晶片侧上的铝衬垫的直接接触的脆性，接头经常由于在凸块/晶片界面处开裂而通不过诸如机械坠落测试的可靠性测试。
银凸块的成本为金凸块的二十分之一，且银凸块在本文中论述的三种金属(Au、Cu、Ag)中具有最高电导率及最高热导率。此外，银凸块的退火温度低于金凸块的退火温度，因此大大减少钝化裂痕的风险。就将银凸块接合至基板的焊料而言，在高于共晶温度的温度下，银/锡界面表现出优于金/锡界面的结合特性的结合特性。在本发明的一些实施例中，银合金用于银凸块以避免银针、银迁移、纯银所固有的氧化及硫化问题。
用于金属涂层电镀物品的方法大体上涉及使电流穿过电解溶液中的两个电极之间，其中该等电极中的一者(通常为阴极)为待电镀的物品。典型银或银合金电解溶液包含溶解的银离子、水、视情况选用的一或多个经溶解合金金属(诸如锡或铜)、其量足以赋予该电镀浴导电性的酸电解质(诸如甲磺酸)，及用以改良电解均一性及金属沉积物的品质的专属添加剂。此些添加剂包括错合物、界面活性剂及微晶剂，以及其他添加剂。
本发明的一些实施例提供一种用于制造半导体结构的方法。该方法包括以下操作：在半导体晶粒上形成导电衬垫；在该导电衬垫上方形成晶种层；在该晶种层上方界定第一遮罩层；及在该第一遮罩层中形成银合金凸块本体。在该第一遮罩层中形成银合金凸块本体的操作包括：制备第一基于氰化物的电镀浴；将该第一基于氰化物的电镀浴的pH值控制在自6至8的范围内；将该半导体晶粒浸没至该第一基于氰化物的电镀浴中；及将自0.1ASD至0.5ASD的电镀电流密度施加至该半导体晶粒。
本发明的一些实施例提供一种用于制造膜上晶片(COF)半导体结构的方法。该方法包括：在一半导体晶粒上形成导电衬垫；在该导电衬垫上方形成晶种层；在该晶种层上方形成银合金凸块本体；将自0.1ASD至0.5ASD的电镀电流密度施加至该半导体晶粒；及将该银合金凸块本体结合至可挠性膜。在该晶种层上方形成银合金凸块本体的操作进一步包括：在自摄氏40度至摄氏50度的溶液温度下制备基于氰化物的电镀浴，其包含KAu(CN)2、KAg(CN)2及K2Pd(CN)4中的至少一者；将该基于氰化物的电镀浴的pH值控制在自6至8的范围内；及将该半导体晶粒浸没至该基于氰化物的电镀浴中。
本发明的一些实施例提供一种用于制造玻璃上晶片(COG)半导体结构的方法。该方法包括：在半导体晶粒上形成导电衬垫；在该导电衬垫上方形成晶种层；在该晶种层上方形成银合金凸块本体；将自0.1ASD至0.5ASD的电镀电流密度施加至该半导体晶粒；及将该银合金凸块本体结合至玻璃基板。在该晶种层上方形成银合金凸块本体进一步包括：制备基于氰化物的电镀浴，其包含KAu(CN)2、KAg(CN)2及K2Pd(CN)4中的至少一者；将该基于氰化物的电镀浴的pH值控制在自6至8的范围内；及将该半导体晶粒浸没至该基于氰化物的电镀浴中。
定义
在描述及主张本发明时，将根据下文所阐述的定义使用以下术语。
如本文所使用，以下缩写将具有以下含义，除非上下文另有明确指示：ASD：A/dm2＝每平方分米安培数；℃：摄氏度；g：公克；mg：毫克；L：公升；A：埃；μm：微米；mm：毫米；min：分钟；Dl：去离子化(De-ionized)；及mL：毫升。所有含量为重量百分比(“重量％”)，且所有比率为摩尔(mol)比率，除非另有说明。所有数值范围为包括性的且可以任何次序组合，惟以下情况除外：显而易见，这些数值范围限定为合计达100％。
如本文所使用，“平均粒径”为藉由诸如X射线绕射(XRD)、电子束散射型式(EBSP)、穿透电子显微术(TEM)或扫描电子显微术(SEM)的任何习知粒径量测技术而量测。样本的经预处理横截面平面经制备用于本发明中所论述的粒径量测。图1展示银合金凸块结构10的横截面，其中银合金凸块本体101连接至导电衬垫102，且银合金凸块本体101及导电衬垫102两者皆定位在装置100上。银合金凸块结构10的纵向方向平行于Y方向。换言之，纵向方向为指垂直于容纳银合金凸块本体101及导电衬垫102的表面的方向。经受本文中所论述的量测中的任一者的横截面平面为穿经银合金凸块本体101、具有垂直于该纵向方向的平面法线的任何平面。
如本文所使用，用于平均粒径量测的“电子束散射型式(EBSP)”由电脑分析程式(例如，TSL OIM分析)加以辅助。电脑分析程式的设定包括但不限于15度的晶界错向、等于或大于0.1的CI值，及至少为5测试点的极小粒径。在一些实施例中，EBSP量测的平均粒径为藉由对至少在横截面平面的三个不同测试位置上的粒径求平均而获得。在每一测试位置量测一预定区域。预定区域根据不同实施例的特征而变化。每一测试位置距邻近测试位置至少1mm远。在一些实施例中，一个测试位置中的每一量测点间之间的间隔为至少5μm。在一些实施例中，在20kV的加速电压及100倍至500倍的放大率下观测经受EBSP量测的所制备样本。在一些实施例中，所制备样本定位在70度的倾斜角处。
如本文所使用，用于平均粒径量测的“穿透电子显微术(TEM)或扫描电子显微术(SEM)”为由影像分析程式(例如，CLEMEX VisionPE)加以辅助。在一些实施例中，TEM或SEM量测的平均粒径为藉由对横截面平面的至少三个不同测试位置上的粒径求平均而获得。在每一测试位置中量测一预定区域。该预定区域根据不同实施例的特征而变化。每一测试位置距邻近测试位置至少1mm远。在一些实施例中，一个测试位置中的每一量测点间之间的间隔为至少5μm。在一些实施例中，在5kV至20kV的加速电压及100倍至500倍的放大率下观测经受TEM或SEM量测的所制备样本。
如本文所使用，银合金凸块的“粒径分布的标准差”为指使用本文中所论述的影像分析程式获得的统计结果。在获得粒径分布的分布曲线之后，一个标准差被定义为自均值粒径(期望值)偏离的粒径，其中粒径在所偏离粒径与均值粒径间之间的晶粒的数目占到晶粒的总数目的34％。
图1为银合金凸块结构10的横截面，其中银合金凸块本体101连接至导电衬垫102。银合金凸块本体101及导电衬垫102定位在装置100上。在一些实施例中，装置100包括但不限于诸如记忆体、电晶体、二极管(PN或PIN接面)、集成电路或可变电抗器的主动装置。在其他实施例中，装置100包括诸如电阻器、电容器或电感器的被动装置。如图1中所示，仅展示银合金凸块本体101的微观结构。银合金凸块本体101的横截面为藉由沿纵向方向(Y方向)切割银合金凸块结构10而制备，且获得XY表面。使用电子显微镜，在横截面平面上识别银合金凸块本体101的晶粒结构，且在本文中所论述的影像分析软件的帮助下，可获得粒径分布的统计资讯。
参看图1，晶粒101A的一区域用直线划出阴影。银合金凸块本体101中所示的SEM图像为取自本文中所描述的银合金凸块本体101的真实横截面平面。在一些实施例中，因为银合金凸块本体101为藉由电镀操作而形成，因此粒径分布相当均一，且未观测到如焊接凸块(未图示)中的受热影响区(HAZ)的受热影响区。HAZ由于以下事实而产生粒径的突变：晶粒生长程序经受局部高温。通常，粒径在HAZ中明显地增大。在本发明的一些实施例中，可在银合金凸块本体101的晶粒中识别出子晶粒结构。举例而言，在晶粒101A中，可以如下方式看到子晶粒域：可识别出藉由域边界分离的晶粒101A内的若干区。
在一些实施例中，银合金凸块本体101包括Ag1-xYx合金。Ag1-xYx合金中的物质Y包括可以任意百分比与银形成完成固溶体的金属。在一些实施例中，可藉由观察二元相图而识别物质Y。二元相图中形成透镜形状的液相线及固相线指示在两种金属组分的任何组成下的固溶体的完全混合。举例而言，在本发明的一些实施例中，物质Y为金、钯，或其组合。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子比之间。
如图1中所示，银合金凸块本体101的粒径形成图2中的分布曲线。在一些实施例中，图2中的分布曲线为经由诸如但不限于CLEMEXVision PE的影像分析软件程式而获得。在图2中，该分布曲线的X轴指示粒径，而该分布曲线的Y轴展示经正规化晶粒数目。本发明中的粒径计算为藉由电脑分析程式(例如，TSL OIM分析)加以辅助。在一些实施例中，电脑分析程式将晶粒的面积转换为具有相同面积的假设圆，且此假设圆的直径被界定为按一长度单位(通常为微米)的粒径。然而，粒径计算不限于上述操作。在其他实施例中，平均粒径为藉由在本文中所描述的银合金凸块结构的横截面平面的TEM图像或SEM图像上绘制对角线，并将该对角线的长度除以该对角线所遇到的晶粒的数目而获得。任何粒径量测操作为适当的，只要其藉由电脑软件加以辅助或其为以一致且系统化的方式进行即可。
在绘出如图2中所示的分布曲线之后，可将标准差量测为银合金凸块本体101的微观结构的形态特征。在一些实施例中，该分布曲线为非对称，其最大值较接近于该分布曲线的右端。在一些实施例中，粒径的均值或期望值由分布曲线的最大值表示。如图2中所示，均值M对应于粒径A，其在一些实施例中在0.7μm至0.8μm的范围内。离开均值M至正方向一个标准差(+1σ)对应于粒径C，其在一些实施例中在l.0μm至1.1μm的范围内。离开平均值M至负方向一个标准差(-1σ)对应于粒径B，其在一些实施例中在0.4μm至0.5μm的范围内。在一些实施例中，一个标准差被定义为自均值M偏离的粒径，且其中粒径在所偏离粒径B或C与均值M之间的晶粒的数目占到晶粒的总数目的34％。注意，获自实际粒径量测的分布曲线并不必须关于均值M对称，且因此，在一些实施例中，离开均值M至粒径C处的正方向一个标准差(+1σ)与均值M之间的差异未必与在粒径B处在负方向上离开均值M一个标准差(-1σ)与均值M之间的差异相同。
在本发明的一些实施例中，粒径C与粒径A之间的差异自0.2μm至0.4μm。在其他实施例中，粒径B与粒径A之间的差异自0.2μm至0.4μm。藉由利用本发明中所论述的电镀操作，银合金凸块本体101的粒径表现出均一分布，且离开均值M(至正或负方向)一个标准差之间的差异可量化为在0.2μm至0.4μm的范围内。
参看图3，展示银合金凸块结构20的横截面。与图1中的银合金凸块结构10相比，银合金凸块结构20进一步包括凸块下金属化(UBM)层104及晶种层105。在一些实施例中，晶种层105含有银或银合金，且为藉由化学气相沉积(CVD)、溅镀及电镀操作中的一者而制备。在一些实施例中，UBM层104具有单层结构或包括由不同材料形成的若干子层的复合结构，且包括选自以下各者的一(或多)层：镍层、钛层、钛钨层、钯层、金层、银层，及其组合。
如图3中所示，银合金凸块本体101的高度H1为自银合金凸块本体的顶表面至装置102的顶表面而量测。在一些实施例中，银合金凸块本体101或Ag1-xYx合金的高度H1在9μm至15μm的范围内。与银合金凸块本体101的高度H1成比例，UBM层104的厚度T2与晶种层105的厚度T1相当。在一些实施例中，UBM层104的厚度T2在至的范围内，且晶种层105的厚度T1在至的范围内。
参看图4，展示膜上晶片(COF)半导体结构30的横截面。在一些实施例中，半导体结构30为半导体结构。COF半导体结构30包括可挠性膜301，该可挠性膜301具有第一表面301A及第二表面301B。可挠性膜301包括但不限于可挠性印刷电路板(FPCB)或聚酰亚胺(PI)。诸如导电铜迹线的导电层302经图案化于可挠性膜301的第一表面301A上。在图4中，具有与图1及图3中所示的数字标记相同的数字标记的元件为指相同元件或其等效物，且为简单起见而不在此处加以重复。在图4中，两个银合金凸块本体101将装置100电耦接至可挠性膜301的导电层302。在一些实施例中，例如无溶剂环氧树脂的具有适当粘度的底部填充材料304注入至可挠性膜301与装置100之间的空间中。
图4中所示的银合金凸块本体101包括Ag1-xYx合金，其中物质Y为金、钯，或其组合。举例而言，Ag1-xYx合金可为诸如Ag1-xAux或Ag1-xPdx的二元金属合金，此外，Ag1-xYx合金可为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子比之间。在一些实施例中，Ag1-xYx合金中的物质Y包括以任何权重百分比与银形成完全固溶体的金属。如图4中所示，银合金凸块本体101的高度H1在9μm至15μm的范围内，且邻近的银合金凸块本体101间之间的间距P低于10μm。在一些实施例中，导电衬垫102的宽度W在20μm至30μm的范围内。
在图4中，阻焊剂图案305定位在导电层302上。焊料层306施加至银合金凸块本体101与导电层302的接头。在本发明的一些实施例中，焊料层306可为习知SnPb或无铅焊料。由点框303包围的接头部分经放大且于图5中展示。参看图5，焊料层306不仅包括焊料材料自身，且亦包括Ag1-aSna合金。在一些实施例中，Ag1-aSna合金至少包括Ag0.5Sn0.5合金。在某些实施例中，当用于COF的在银合金凸块侧设定的内部引线结合(ILB)温度为摄氏400度时，AgSn合金系统的液相实质上大于AuSn合金系统的液相(给定在合金凸块的自由端设定的相同结合温度)。AgSn合金的过量液相促进银合金凸块本体101与导电层302之间的粘附，且因此藉由使用基于Ag的合金凸块在AgSn合金系统中获得较好接面可靠性。另一方面，用于COF的较低ILB温度可用于AgSn合金系统中。例如低于摄氏400度的较低ILB温度可防止可挠性膜301变形或收缩。在其他实施例中，各向异性导电膜(ACF)可用以连接银合金凸块本体101与导电层302。
参看图5，仅展示银合金凸块本体101的微观结构。银合金凸块本体101的平均粒径在0.5μm至1.5μm的范围内。因为银的熔化温度为摄氏962度，因此施加至银合金凸块本体101的退火温度可低于摄氏250度以避免图1、图3及图4中所示的钝化层103的开裂。与金的较高熔化温度(摄氏1064度)相比，较低熔化温度导致较低退火温度，且因此诸如钝化层的先前生长的结构经受较低热压力。在一些实施例中，在于低于摄氏250度的温度下对银合金凸块本体101进行退火之后，藉由本文中所描述的方法量测的Ag1-xYx合金的平均粒径为1μm。
参看图6，展示多层凸块结构40的横截面。与图3中的银合金凸块结构20相比，多层凸块结构40进一步包括在银合金凸块本体101的顶表面上的金属层107。在一些实施例中，多层凸块结构40包括如图1、图3及图4中所示的银合金凸块结构的银合金凸块结构，其中银合金凸块本体101的底表面连接至导电衬垫102，且其顶表面连接至金属层107。在一些实施例中，金属层107不仅位于银合金凸块本体101的顶表面上，且位于其侧壁处(请参看如图6中所示的金属层107的虚线部分)。在一些实施例中，金属层107为不同于银的金属材料。在其他实施例中，多层凸块结构40的金属层107包括金、金合金、铜，或铜合金。在其他实施例中，多层凸块结构40的金属层107包括铜及其合金。金属层107的厚度H2应足够厚以在银合金凸块本体101与外部装置或基板之间形成接头界面，例如，可挠性膜的导电迹线(此处未图示)。
在一些实施例中，金属层107的厚度H2自1μm至3μm，且金属层107为藉由电镀操作而形成。在图6中，多层凸块结构40包括凸块下金属化(UBM)层104及晶种层105。在一些实施例中，晶种层105含有银或银合金，且为藉由化学气相沉积(CVD)、溅镀及电镀操作中的一者而制备。在一些实施例中，UBM层104具有单层结构或包括由不同材料形成的若干子层的复合结构，且包括选自以下各者的一(或多)层：镍层、钛层、钛钨层、钯层、金层、银层，及其组合。
图6中所示的银合金凸块本体101包括Ag1-xYx合金，其中物质Y为金、钯，或其组合。举例而言，Ag1-xYx合金可为诸如Ag1-xAux或Ag1-xPdx的二元金属合金，此外，Ag1-xYx合金可为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYX合金中的含量介于0.005至0.25原子比之间。在一些实施例中，Ag1-xYx合金中的物质Y包括以任何权重百分比与银形成完全固溶体的金属。如图6中所示，银合金凸块本体101的高度H1在9μm至15μm的范围内。
参看图7，展示膜上晶片(COF)半导体结构50的横截面。在一些实施例中，半导体结构50为半导体结构。COF 50包括具有第一表面301A及第二表面301B的可挠性膜301。可挠性膜301包括但不限于可挠性印刷电路板(FPCB)或聚酰亚胺(PI)。诸如导电铜迹线的导电层302经图案化于可挠性膜301的第一表面301A上，且阻焊剂图案305定位在导电层302上。在图7中，与图1及图3中所示的数字标记具有相同数字标记的元件为指相同元件或其等效物，且为简单起见不在此处加以重复。在图7中，包括银合金凸块本体101及金属层107的两个多层凸块结构(101，107)将装置100电耦接至可挠性膜301的导电层302。在一些实施例中，例如无溶剂环氧树脂的具有适当粘度的底部填充材料304注入至可挠性膜301与装置100之间的空间中。在金属层107为由经电镀金膜制成的情况下，后续结合操作可利用此项技术中对于金凸块所习知的结合操作。
图7中所示的银合金凸块本体101包括Ag1-xYx合金，其中物质Y为金、钯，或其组合。举例而言，Ag1-xYx合金可为诸如Ag1-xAux或-xPdx的二元金属合金，此外，Ag1-xYx合金可为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在-xYX合金中的含量介于0.005至0.25原子比之间。在一些实施例中，Ag1-xYx合金中的物质Y包括以任何权重百分比与银形成完全固溶体的金属。图7中所示的金属层107包括不同于银的金属材料，例如金或铜。如图7中所示，银合金凸块本体101的高度H1在9μm至15μm的范围内，且邻近的银合金凸块本体101之间的间距P低于10μm。金属层107的高度H2在1μm至3μm的范围内。在一些实施例中，导电衬垫102的宽度W在20μm至30μm的范围内。
在图7中，阻焊剂图案305定位在导电层302上。焊料层308施加至多层凸块结构(101，107)与导电层302的接头。在本发明的一些实施例中，焊料层306可为习知SnPb或无铅焊料。由点框307包围的接头部分经放大且展示于图9中。
图8中所示的膜上晶片(COF)半导体结构60的横截面类似于图7中所示的COF半导体结构50的横截面，惟图8中的金属层107覆盖银合金凸块本体101的顶表面及侧壁除外。换言之，多层凸块结构(101，107)可具有至少两个不同构造。在图7中，金属层107为藉由电镀操作或无电极电镀操作而形成于银合金凸块本体101的顶表面上方，而在图8中，金属层107为藉由电镀操作或无电极电镀操作而形成于银合金凸块本体101的顶表面上方及侧壁处。图8中的与图7中所示的元件具有相同数字标记的元件指代相同元件或其等效物，且此处为简单起见而不再重复。
在本发明的一些实施例中，除藉由焊接点将银合金凸块本体101或多层凸块结构(101，107)结合至可挠性膜301以外，亦可采用各向异性导电膜(ACF)来形成如图4、图7及图8中所示的COF半导体结构30、50及60中的连接。
参看图9，焊料层308不仅包括焊料材料自身，且亦包括Au1-aSna合金(若金属层107为由Au或其合金制成)。在一些实施例中，Au1-aSna合金至少包括Au0.5Sn0.5合金。在其他实施例中，各向异性导电膜ACF)可用以连接多层凸块结构(101，107)与导电层302。
在本发明的一些实施例中，如图10中所示，本文中论述的银合金凸块本体101亦可用于玻璃上晶片(COG)半导体结构70中。透明基板的第一表面401A上的导电迹线402与待封装的装置100的银合金凸块本体101之间的电连接可为各向异性导电膜(ACF)406。举例而言，透明基板为玻璃基板401。ACF包括涂有Au的塑胶球体406A，其直径自3μm至5μm，分散在热固性环氧树脂基质中。在一些实施例中，用于在COG半导体结构60中使用ACF的结合温度为摄氏200度。
在本发明的一些实施例中，如图11中所示，本文中论述的多层凸块结构(101，107)亦可用于玻璃上晶片(COG)半导体结构80中。玻璃基板401的第一表面401A上的导电迹线402与待封装的装置100的多层凸块结构(101，107)之间的电连接可为各向异性导电薄(ACF)406。在一些实施例中，玻璃基板401的第一表面401A上的导电迹线402为由诸如氧化铟锡(ITO)的透明且导电材料制成。举例而言，ACF包括涂有Au的塑胶球体406A，其直径自3μm至5μm，分散在热固性环氧树脂基质中。在一些实施例中，用于在COG半导体结构70中使用ACF的结合温度为摄氏200度。在一些实施例中，多层凸块结构(101，107)的金属层107为经电镀金膜，其厚度自lμm至3μm。在此情况下，对于金凸块技术习知的结合操作可用于连接多层凸块结构(101，107)与诸如玻璃基板的外部装置。
在本发明的一些实施例中，如图12中所示，本文中论述的多层凸块结构(101，107)亦可用于玻璃上晶片(COG)半导体结构90中。玻璃基板401的第一表面401A上的导电迹线402与待封装的装置100的多层凸块结构(101，107)之间的电连接可为各向异性导电膜(ACF)406。举例而言，ACF包括涂有Au的塑胶球体406A，其直径自3μm至5μm，分散在热固性环氧树脂基质中。在一些实施例中，用于在COG半导体结构70中使用ACF的结合温度为摄氏200度。在一些实施例中，多层凸块结构(101，107)的金属层107为经电镀金膜，其厚度自1μm至3μm，覆盖银合金凸块本体101的顶表面101B及侧壁101A。在此情况下，对于金凸块技术习知的结合操作可用于连接多层凸块结构(101，107)与诸如玻璃基板的外部装置。在一些实施例中，顶表面101B上的金属层107的厚度不同于覆盖银合金凸块本体101的侧壁101A的金属层107的厚度。
可易于藉由选择适当电镀电镀浴来调整本文中论述的银合金凸块的硬度。举例而言，可将用于COG应用的银合金凸块的硬度调整至100HV。对于另一实例，可将用于COF应用的银合金凸块的硬度调整至55HV。因为纯银的硬度(85HV)介于55HV与100HV之间，因此可藉由使用不同电镀电镀浴来电镀银合金凸块而定制具有所要硬度的银合金。在一些实施例中，COG应用需要银合金凸块具有较大硬度以促进ACF结合操作。在其他实施例中，COF应用需要银合金凸块具有较低硬度以防止损伤可挠性膜上的导电迹线。
图13至图26展示本发明中描述的银合金凸块的制造操作。在图13中，在钝化层103及导电衬垫102的一部分上形成UBM层104。在一些实施例中，UBM层104为藉由对材料进行CVD、溅镀、电镀或无电极电镀而形成，该等材料为选自镍、钛、钛钨、钯、金、银，及其组合。在一些实施例中，将UBM层104的厚度T2控制在自至的范围内。在图14中，将晶种层105沉积在UBM层104上。在一些实施例中，晶种层105为藉由对含有银的材料进行CVD、溅镀、电镀或无电极电镀而形成。在一些实施例中，将晶种层105的厚度T1控制为与UBM层104的厚度T2相当。举例而言，在自至的范围内。
参看图15，在晶种层105上方形成可为硬式遮罩或光阻剂的第一遮罩层109。在导电衬垫102上方形成第一遮罩层109的开口109A用于接收导电凸块材料。在一些实施例中，第一遮罩层109为由厚度T3大于待电镀的导电凸块的厚度的正光阻剂制成。在其他实施例中，第一遮罩层109为由负光阻剂制成。
图16及图17展示电镀操作及其后的结果。图16展示一电镀系统，其包括容纳电镀浴113、阳极111及阴极112的容器100。在一些实施例中，阳极111不可溶且可由涂有铂的钛制成，沉积有恰当晶种层的晶圆衬垫定位在阴极112处，且电镀浴113含有基于氰化物的电镀溶液，包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4及其盐。在一些实施例中，将电镀浴113的pH值控制在中性，例如自6至8。将电镀浴113的温度控制在摄氏40度至摄氏50度。在一些实施例中，可藉由定位在容器100下的热板(未图示)来维持电镀浴113的温度。在其他实施例中，可藉由一电镀溶液循环系统来维持电镀浴113的温度，在该电镀溶液循环系统中，出口100B排放电镀溶液，且入口100A吸入温度受控的电镀溶液。可将浓度自2ml/L至5ml/L的包括草酸盐的适当整平剂添加至电镀浴113。在一些实施例中，经施加以用于银合金导电凸块电镀的直流电(DC)在0.1ASD至0.5ASD的范围内。
参看图16，阴极112包括沉积有含有银或银合金的晶种层105的晶圆衬垫，且在阴极处发生的反应可为以下反应中的一者：
KAg(CN)2→K++Ag++2CN-
KAu(CN)2→K++Au++2CN-
K2Pd(CN)4→2K++Pd2++4CN-
图15中所示的阳极111包括铂电极，且其上发生的反应可为：
2H2O→4H++O2(g)+4e-
外部DC电流的正端连接至阳极，且外部DC电流的负端连接至阴极。如图15中可见，经还原的银离子及经还原的金离子沉积至晶圆衬垫的晶种层105上，填充由第一遮罩层109界定的开口109A且形成AgAu二元合金。在一些实施例中，若电镀浴包括银离子源(例如，KAg(CN)2)及钯离子源(例如，K2Pd(CN)4)，则经由上文描述的相同电镀操作设定，经还原的银离子及经还原的金离子沉积至晶圆衬垫的晶种层105上，填充由第一遮罩层109界定的开口109且形成AgPd二元合金。在一些实施例中，若电镀浴包括银离子源(例如，KAg(CN)2)、金离子源(例如，(CN)2及其盐)及钯离子源(例如，K2Pd(CN)4及其盐)，则经由上文描述的相同电镀操作设定，经还原的银离子、经还原的金离子及经还原的钯离子沉积至晶圆衬垫的晶种层105上，填充由第一遮罩层109界定的开口109A，且形成AgAuPd三元合金。
在电镀如图6中所示的多层凸块结构40的一些实施例中，在将AgAu、AgPd或AgAuPd合金沉积至图15中的晶圆衬垫的晶种层上之后，接着自包括若干金属离子源的电镀浴移除晶圆衬垫，且将其置放至含有用于沉积如图6中所示的非银金属层107的金属离子源的一种物质的另一电镀浴。
图16展示在完成图15中所示的电镀操作之后的晶圆衬垫。在图17中，银合金凸块本体101形成于导电衬垫102上方。在图18中，若使用光阻剂，则剥除第一遮罩层109。藉由蚀刻操作移除不由银合金凸块本体101覆盖的UBM层104及晶种层105以隔离两个银合金导电凸块。
[实施例1]
实施例1提供一种用于制造图3中所示的结构20的方法，该半导体结构20具有Ag1-xAux合金凸块本体101，其中X在0.01至0.1的范围内。在制造该半导体结构20中采用的操作可参考如前文在本发明中论述的图13、图14、图15、图16、图17及图18。在图13中，在装置100上形成导电衬垫102。在实施例1中，该装置100包括半导体晶粒。在图14中，在导电衬垫102及钝化层103上方形成UBM层104及晶种层105。在图15中，在晶种层105上方图案化第一遮罩层109，且在第一遮罩层109中界定若干开口109A。在实施例1中，开口109A定位在导电衬垫102上方。图16说明藉由电镀操作在第一遮罩层109中形成银合金凸块本体101。
在图16中所示的容器100'中，包括半导体晶粒的晶圆衬垫浸没至第一基于氰化物的电镀浴中作为阴极，而涂布有Pt的Ti经定位而在电镀操作中作为阳极。在实施例1中，该第一基于氰化物的电镀浴包括5至15g/L的KAg(CN)2，以及5至15g/L的KAu(CN)2。在实施例1中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至60wt％为KAu(CN)2，其余为KAg(CN)2盐。
在实施例1中，可将整平剂(诸如2至5ml/L的含有草酸盐的溶液)添加至第一基于氰化物的电镀浴以电镀反应。该第一基于氰化物的电镀浴的pH值经控制在自6.5至7的范围内，且施加自0.15至0.5ASD的电镀电流密度。在实施例1中，第一基于氰化物的电镀浴的温度维持在摄氏40度至摄氏50度。如图18中所示，在于第一基于氰化物的电镀浴中形成银合金凸块本体101之后，移除第一遮罩层109及晶种层105的不由银合金凸块本体101覆盖的部分。接着在自摄氏200度至摄氏300度的温度下对银合金凸块本体101进行退火历时30分钟至60分钟的持续时间。
在形成实施例1中的银合金凸块本体101之后，可进一步藉由结合操作将银合金凸块本体101附接至可挠性膜301以形成如图4中所示的膜上晶片(COF)半导体结构。适当热源将施加在装置100端处，其允许银合金凸块本体101与焊料层306之间的接面处于或高于Sn-Ag共晶温度(220℃)。因为Ag的熔点低于Au的熔点，因此用于COF结构中的银合金凸块本体101的退火温度可控制在仅摄氏200度至摄氏300度历时30分钟至60分钟的持续时间。此外，可使用各向异性导电膜(ACF)来结合银合金凸块本体101与可挠性膜301，而非使用焊接点操作。
在形成实施例1中的银合金凸块本体101之后，可进一步藉由结合操作将银合金凸块本体101附接至玻璃基板401以形成如图10中所示的玻璃上晶片(COG)半导体结构。可使用各向异性导电膜(ACF)来结合银合金凸块本体101与玻璃基板401。
[实施例2]
实施例2提供一种用于制造图3中所示的半导体结构20的方法，该半导体结构20具有Ag1-xPdx合金凸块本体101，其中X在0.01至0.1的范围内。在制造该半导体结构20中采用的操作可参考如前文在本发明中论述的图13、图14、图15、图16、图17及图18。除了第一基于氰化物的电镀浴的含量外，实施例2中的其他制造操作可参考实施例1中所描述的操作。
在图16中所示的容器100'中，包括半导体晶粒的晶圆衬垫浸没至第一基于氰化物的电镀浴中作为阴极，而涂布有Pt的Ti经定位而在电镀操作中作为阳极。在实施例2中，该第一基于氰化物的电镀浴包括5至15g/L的KAg(CN)2，以及5至15g/L的K2Pd(CN)4及其盐。在实施例2中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至30wt％为K2Pd(CN)4，其余为KAg(CN)2盐。
[实施例3]
实施例3提供一种用于制造图3中所示的半导体结构20的方法，该半导体结构20具有Ag1-x(AuPd)x合金凸块本体101，其中X在0.01至0.1的范围内。在制造该半导体结构20中采用的操作可参考如前文在本发明中论述的图13、图14、图15、图16、图17及图18。除了第一基于氰化物的电镀浴的含量外，实施例3中的其他制造操作可参考实施例1及实施例2中所描述的操作。
在图16中所示的容器100'中，包括半导体晶粒的晶圆衬垫浸没至第一基于氰化物的电镀浴中作为阴极，而涂布有Pt的T i经定位而在电镀操作中作为阳极。在实施例3中，该第一基于氰化物的电镀浴包括5至15g/L的KAg(CN)2、5至15g/L的K2Pd(CN)4，以及5至15g/L的KAu(CN)2。在实施例3中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至30wt％为K2Pd(CN)4，且10wt％至60wt％为KAu(CN)2，其余为KAg(CN)2盐。
图17、图19及图20提及多层凸块结构的制造步骤。在一些实施例中，在自图15中所示的电镀浴移除之后且在剥除光阻剂的前，接着将晶圆衬垫浸没至含有KAu(CN)2的另一电镀浴中。如图19中所示，金属层107形成于银合金凸块本体101的顶表面101B上。在图20中，若使用光阻剂，则剥除第一遮罩层109。藉由蚀刻操作移除不由银合金凸块本体101覆盖的UBM层104及晶种层105以隔离两个多层合金凸块。
[实施例4]
实施例4提供一种用于制造图6中所示的多层凸块结构40的电镀方法，该多层凸块结构40具有Ag1-xAux、Ag1-xPdx或Ag1-x(AuPd)x合金凸块本体101，其中X在0.01至0.1的范围内，且金属层107仅在银合金凸块本体101的顶表面上。在制造半导体结构40中采用的操作可参考如前文在本发明中论述的图13、图14、图15、图16、图17、图19及图20。在图13中，在装置100上形成导电衬垫102。在实施例4中，该装置100包括半导体晶粒。在图14中，在导电衬垫102及钝化层103上方形成UBM层104及晶种层105。在图15中，在晶种层105上方图案化第一遮罩层109，且在第一遮罩层109中界定若干开口109A。在实施例4中，开口109A定位在导电衬垫102上方。图16说明藉由电镀操作在第一遮罩层109中形成银合金凸块本体101。
在图16中所示的容器100'中，包括半导体晶粒的晶圆衬垫浸没至第一基于氰化物的电镀浴中作为阴极，而涂布有Pt的Ti经定位而在电镀操作中作为阳极。在实施例4中，该第一基于氰化物的电镀浴可包括5至15g/L的KAg(CN)2以及5至15g/L的KAu(CN)2。在实施例4中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至60wt％为KAu(CN)2，其余为KAg(CN)2盐。类似地，在实施例4中，该第一基于氰化物的电镀浴可包括5至15g/l的KAg(CN)2，以及5至15g/L K2Pd(CN)4及其盐。在实施例4中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至30wt％为K2Pd(CN)4，其余为KAg(CN)2盐。类似地，在实施例4中，该第一基于氰化物的电镀浴可包括5至15g/L的KAg(CN)2、5至15g/L的K2Pd(CN)4以及5至15g/L的KAu(CN)2。在实施例4中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至30wt％为K2Pd(CN)4，且10wt％至60wt％为KAu(CN)2，其余为KAg(CN)2盐。
在实施例4中，可将整平剂(诸如2至5ml/L的含有草酸盐的溶液)添加至第一基于氰化物的电镀浴以促进电镀反应。该第一基于氰化物的电镀浴的pH值经控制在6.5至7的范围内，且施加自0.15至0.5ASD的电镀电流密度。在实施例4中，第一基于氰化物的电镀浴的温度维持在摄氏40度至摄氏50度。
在实施例4中，在形成银合金凸块本体101之后，接着将晶圆衬垫浸没至包括5至15g/L的KAu(CN)2的第二基于氰化物的电镀浴中。可将整平剂(诸如2至5ml/L的含有草酸盐的溶液)添加至第二基于氰化物的电镀浴以促进电镀反应。该第二基于氰化物的电镀浴的pH值经控制在6.5至7的范围内，且施加自0.15至0.5ASD的电镀电流密度。在实施例4中，该第二基于氰化物的电镀浴的温度维持在摄氏40度至摄氏45度的范围内。
如图19及图20中所示，在于该第二基于氰化物的电镀浴中形成多层凸块结构(101，107)之后，移除第一遮罩层109及晶种层105的不由多层凸块结构(101，107)覆盖的部分。接着在自摄氏200度至摄氏300度的温度下对多层凸块结构(101，107)进行退火历时30分钟至60分钟的持续时间。
在形成实施例4中的银合金凸块本体101之后，可进一步藉由结合操作将银合金凸块本体101附接至可挠性膜301以形成如图7中所示的膜上晶片(COF)半导体结构。适当热源将施加在装置100端处，其允许银合金凸块本体101的顶表面上的金属层107与焊料层306之间的接面处于或高于Sn-Au共晶温度(215℃)。此外，可使用各向异性导电膜(ACF)来结合银合金凸块本体101与可挠性膜301，而非使用焊接点操作。
在形成实施例1中的银合金凸块本体101之后，可进一步藉由结合操作将银合金凸块本体101附接至玻璃基板401以形成如图11中所示的玻璃上晶片(COG)半导体结构。可使用各向异性导电膜(ACF)406来结合银合金凸块本体101与玻璃基板401。
图17、图21至图24及图26提及多层凸块结构的制造步骤。在一些实施例中，电镀操作用以形成多层凸块结构。在自图16中所示的电镀电镀浴移除之后且在剥除光阻剂的前，在第一遮罩层109上形成第二遮罩层110以减小第一遮罩层109的第一宽度W1。在一些实施例中，第一遮罩层109的第一宽度Wl足够宽以形成至经电镀银合金凸块本体101的侧壁101A的实体接触。在图21及图22中，第一遮罩层109经由部分剥除操作而变换成第二宽度W2。在一些实施例中，在剥除操作中移除不由第二硬式遮罩层110覆盖的部分，且获得其减小的第二宽度W2。在一些实施例中，第二遮罩层110的第二宽度W2足够窄以在其自身与经电镀银合金凸块本体101的侧壁101A之间形成一间隙。
图23展示一电镀系统，其包括容纳电镀电镀浴113、阳极111及阴极112的容器100。在一些实施例中，阳极111不可溶且可由涂有铂的钛制成，沉积有恰当晶种层的晶圆衬垫定位在阴极112处，且电镀电镀浴113含有基于氰化物的电镀溶液，包括KAu(CN)2。在一些实施例中，将电镀电镀浴113的pH值控制为中性，例如自6至8。将电镀电镀浴113的温度控制为摄氏40度至摄氏50度。在一些实施例中，可藉由定位在容器100下的热板(未图示)来维持电镀电镀浴113的温度。在其他实施例中，可藉由一电镀溶液循环系统来维持电镀电镀浴113的温度，在该电镀溶液循环系统中，出口100B排放电镀溶液，且入口100A吸入温度受控的电镀溶液。可将浓度自2ml/L至5ml/L的包括草酸盐的适当整平剂添加至电镀电镀浴113。在一些实施例中，经施加用于银合金导电凸块电镀的直流电(DC)在0.1ASD至0.5ASD的范围内。
图24展示在图23中的电镀操作之后自电镀浴113取出的晶圆衬垫。金离子与银合金凸块本体101在其表面(包括银合金凸块本体101的顶表面101B及侧壁101A)处反应，且形成覆盖银合金凸块本体101的顶表面101B及侧壁101A两者的金属层107。然而，在一些实施例中，金属层107在顶表面101A处的厚度不同于金属层107在银合金凸块本体101的侧壁101B处的厚度。在其他实施例中，金属层107在顶表面101A处的厚度大于金属层107在银合金凸块本体101的侧壁101B处的厚度。
在图26中，藉由剥除及蚀刻操作移除第一遮罩层109以及不由银合金凸块本体101覆盖的UBM层104及晶种层105以隔离两个多层合金凸块。
[实施例5]
实施例5提供一种用于制造图6中所示的多层凸块结构40的电镀方法，该多层凸块结构40具有Ag1-xAux、Ag1-xPdx或Ag1-x(AuPd)x合金凸块本体101，其中X在0.01至0.1的范围内，且金属层107不仅在银合金凸块本体101的顶表面上，而且在其侧壁处。在制造半导体结构40中采用的操作可参考如前文在本发明中论述的图13、图14、图15、图16、图17、图21、图22、图23、图24及图26。在图13中，在装置100上形成导电衬垫102。在实施例5中，该装置100包括半导体晶粒。在图14中，在导电衬垫102及钝化层103上方形成UBM层104及晶种层105。在图15中，在晶种层105上方图案化第一遮罩层109，且在第一遮罩层109中界定若干开口109A。在实施例5中，开口109A定位在导电衬垫102上方。图16说明藉由电镀操作在第一遮罩层109中形成银合金凸块本体101。
在图16中所示的容器100'中，包括半导体晶粒的晶圆衬垫浸没至第一基于氰化物的电镀浴中作为阴极，而涂布有Pt的Ti经定位而在电镀操作中作为阳极。在实施例5中，该第一基于氰化物的电镀浴可包括5至15g/L的KAg(CN)2以及5至15g/L的KAu(CN)2。在实施例5中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至60wt％为KAu(CN)2，其余为KAg(CN)2盐。类似地，在实施例5中，该第一基于氰化物的电镀浴可包括5至15g/l的KAg(CN)2，以及5至15g/L K2Pd(CN)4及其盐。在实施例5中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至30wt％为K2Pd(CN)4，其余为KAg(CN)2盐。类似地，在实施例5中，该第一基于氰化物的电镀浴可包括5至15g/L的KAg(CN)2、5至15g/L的K2Pd(CN)4以及5至15g/L的KAu(CN)2。在实施例5中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至30wt％为K2Pd(CN)4，且10wt％至60wt％为KAu(CN)2，其余为KAg(CN)2盐。
在实施例5中，可将整平剂(诸如2至5ml/L的含有草酸盐的溶液)添加至第一基于氰化物的电镀浴以促进电镀反应。该第一基于氰化物的电镀浴的pH值经控制在6.5至7的范围内，且施加自0.15至0.5ASD的电镀电流密度。在实施例5中，第一基于氰化物的电镀浴的温度维持在摄氏40度至摄氏50度。
在实施例5中，具有宽度W2的经修整第一遮罩层109形成于晶种层105上方，从而在经修整第一遮罩层109与银合金凸块本体101之间形成一间隙。因为经修整第一遮罩层109的宽度W2短于第一遮罩层109的宽度W1，因此可经由如图21及图22中所示的微影操作进行经修整第一遮罩层109的形成。图21中所示的第二遮罩层110用以界定经修整第一遮罩层109的修整程度(亦即，W1与W2之间的差异)。
在实施例5中，在形成银合金凸块本体101及经修整第一遮罩层109之后，接着将晶圆衬垫浸没至包括5至15g/L的KAu(CN)2的第二基于氰化物的电镀浴中。可将整平剂(诸如2至5ml/L的含有草酸盐的溶液)添加至该第二基于氰化物的电镀浴以促进电镀反应。该第二基于氰化物的电镀浴的pH值经控制在6.5至7的范围内，且施加自0.15至0.5ASD的电镀电流密度。在实施例5中，该第二基于氰化物的电镀浴的温度维持在摄氏40度至摄氏45度的范围内。
如图24及图26中所示，在于该第二基于氰化物的电镀浴中形成多层凸块结构(101，107)之后，移除经修整第一遮罩层109及晶种层105的不由多层凸块结构(101，107)覆盖的部分。接着在自摄氏200度至摄氏300度的温度下对多层凸块结构(101，107)进行退火历时30分钟至60分钟的持续时间。
在形成实施例5中的银合金凸块本体101之后，可进一步藉由结合操作将银合金凸块本体101附接至可挠性膜301以形成如图8中所示的膜上晶片(COF)半导体结构60。适当热源将施加在装置100端处，其允许银合金凸块本体101的顶表面上的金属层107与焊料层306之间的接面处于或高于Sn-Au共晶温度(215℃)。此外，可使用各向异性导电膜(ACF)来结合银合金凸块本体101与可挠性膜301，而非使用焊接点操作。
在形成实施例5中的银合金凸块本体101之后，可进一步藉由结合操作将银合金凸块本体101附接至玻璃基板401以形成如图12中所示的玻璃上晶片(COG)半导体结构90。可使用各向异性导电膜(ACF)406来结合银合金凸块本体101与玻璃基板401。
图17、图25及图26提及多层凸块结构的制造步骤。在一些实施例中，无电极电镀操作用以形成多层凸块结构。在移除第一遮罩层109之后，最初由第一遮罩层109覆盖的UBM层104及晶种层105接着被暴露。图25展示容纳无电极电镀浴115的容器200。将剥除第一遮罩层109之后的晶圆衬垫浸没至含有基于氰化物(诸如KAu(CN)2)的无电极电镀浴115中。在一些实施例中，将无电极电镀浴115的pH值控制为中性，例如自6至8。将无电极电镀浴115的温度控制为摄氏40度至摄氏50度。在一些实施例中，可藉由定位在容器200下的热板201维持无电极电镀浴115的温度。在其他实施例中，可藉由一无电极电镀溶液循环系统(未图示)来维持无电极电镀浴115的温度，在该无电极电镀溶液循环系统中，出口排放无电极电镀溶液，且入口进入控制温度的无电极电镀溶液。可将浓度自2ml/L至5ml/L的包括草酸盐及其盐的适当整平剂添加至无电极电镀浴115。如图25及图26中所示，金离子与银合金凸块本体101在其表面(包括银合金凸块本体101的顶表面101B及侧壁101A)处反应，且形成覆盖银合金凸块本体101的顶表面101B及侧壁101A两者的金属层107。然而，在一些实施例中，金属层107在顶表面101A处的厚度可与金属层107在银合金凸块本体101的侧壁101B处的厚度相当。在其他实施例中，藉由无电极电镀操作制备的金属层107的厚度均一性比藉由电镀操作制备的金属层107的厚度均一性更佳。
图26展示在图25中但在移除不由银合金凸块本体101覆盖的UBM层104及晶种层105之后的晶圆衬垫。
[实施例6]
实施例6提供一种用于制造图6中所示的多层凸块结构40中的金属层107的无电极电镀方法，该多层凸块结构40具有Ag1-xAux、Ag1-xPdx或Ag1-x(AuPd)x合金凸块本体101，其中X在0.01至0.1的范围内，且金属层107不仅在银合金凸块本体101的顶表面上，而且在其侧壁处。在制造半导体结构40中采用的操作可参考如前文在本发明中论述的图13、图14、图15、图16、图17、图25及图26。在图13中，在装置100上形成导电衬垫102。在实施例4中，该装置100包括半导体晶粒。在图14中，在导电衬垫102及钝化层103上方形成UBM层104及晶种层105。在图15中，在晶种层105上方图案化第一遮罩层109，且在第一遮罩层109中界定若干开口109A。在实施例6中，开口109A定位在导电衬垫102上方。图16说明藉由电镀操作在第一遮罩层109中形成银合金凸块本体101。
在图16中所示的容器100'中，包括半导体晶粒的晶圆衬垫浸没至第一基于氰化物的电镀浴中作为阴极，而涂布有Pt的Ti经定位而在电镀操作中作为阳极。在实施例6中，该第一基于氰化物的电镀浴可包括5至15g/L的KAg(CN)2以及5至15g/L的KAu(CN)2。在实施例6中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至60wt％为KAu(CN)2，其余为KAg(CN)2盐。类似地，在实施例6中，该第一基于氰化物的电镀浴可包括5至15g/l的KAg(CN)2，以及5至15g/L K2Pd(CN)4及其盐。在实施例6中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至30wt％为K2Pd(CN)4，其余为KAg(CN)2盐。类似地，在实施例6中，该第一基于氰化物的电镀浴可包括5至15g/L的KAg(CN)2、5至15g/L的K2Pd(CN)4以及5至15g/L的KAu(CN)2。在实施例6中，在该第一基于氰化物的电镀浴中，其中添加的全部盐中10wt％至30wt％为K2Pd(CN)4，且10wt％至60wt％为KAu(CN)2，其余为KAg(CN)2盐。
在实施例6中，可将整平剂(诸如2至5ml/L的含有草酸盐的溶液)添加至第一基于氰化物的电镀浴以促进电镀反应。该第一基于氰化物的电镀浴的pH值经控制在6.5至7的范围内，且施加自0.15至0.5ASD的电镀电流密度。在实施例6中，第一基于氰化物的电镀浴的温度维持在摄氏40度至摄氏50度。
如图17及图25中所示，在形成银合金凸块本体101之后，移除第一遮罩层109，且接着将晶圆衬垫浸没至包括10至20g/L的KAu(CN)2的无电极电镀浴115中。无电极电镀浴115的pH值经控制在4.5至6.5的范围内。在实施例6中，无电极电镀浴115的温度维持在摄氏80度至摄氏90度的范围内。
如图25及图26中所示，在于无电极电镀浴115中形成多层凸块结构(101，107)之后，移除晶种层105的不由多层凸块结构(101，107)覆盖的部分。接着在自摄氏200度至摄氏300度的温度下对多层凸块结构(101，107)进行退火历时30分钟至60分钟的持续时间。
在形成实施例6中的银合金凸块本体101之后，可进一步藉由结合操作将银合金凸块本体101附接至可挠性膜301以形成如图8中所示的膜上晶片(COF)半导体结构60。适当热源将施加在装置100端处，其允许银合金凸块本体101的顶表面上的金属层107与焊料层306之间的接面处于或高于Sn-Au共晶温度(215℃)。此外，可使用各向异性导电膜(ACF)来结合银合金凸块本体101与可挠性膜301，而非使用焊接点操作。
在形成实施例6中的银合金凸块本体101之后，可进一步藉由结合操作将银合金凸块本体101附接至玻璃基板401以形成如图12中所示的玻璃上晶片(COG)半导体结构90。可使用各向异性导电膜(ACF)406来结合银合金凸块本体101与玻璃基板401。
此外，本申请案的范畴不意欲限于说明书中描述的制程、机器、制造，及物质组成、构件、方法及步骤的特定实施例。如熟习此项技术者将易于自本发明的揭示内容而了解，可根据本发明利用执行与本文中所描述的对应实施例执行实质上相同的功能或达成与该等对应实施例实质上相同的结果的当前现有或稍后待开发的程序、机器、制造、物质组成、构件、方法或步骤。
因此，所附申请专利范围意欲在其范畴中包括此等程序、机器、制造，及物质组成、构件、方法或步骤。此外，每一权利要求构成一单独实施例，且各种权利要求及实施例的组合在本发明的范畴内。

Claims (6)

1.一种用于制造一半导体结构的方法，其包含：
在一半导体晶粒上形成一导电衬垫；
在所述导电衬垫上方形成一晶种层；
在所述晶种层上方界定一第一遮罩层；及
在所述第一遮罩层中形成一银合金凸块本体，其包含：
制备一第一基于氰化物的电镀浴；
将所述第一基于氰化物的电镀浴的一pH值控制在6至8的范围内；
将所述半导体晶粒浸没至所述第一基于氰化物的电镀浴中；及
将自0.1ASD至0.5ASD的一电镀电流密度施加至所述半导体晶粒,
其中所述制备所述第一基于氰化物的电镀浴包含将KAg(CN)2引入至所述第一基于氰化物的电镀浴中。
2.如权利要求1所述的用于制造一半导体结构的方法，其特征在于，其中所述制备所述第一基于氰化物的电镀浴进一步包含将KAu(CN)2引入至所述第一基于氰化物的电镀浴中。
3.如权利要求2所述的用于制造一半导体结构的方法，其特征在于，其中所述将KAu(CN)2引入至所述第一基于氰化物的电镀浴中包含将KAu(CN)2的一浓度控制在10wt％至60wt％的一范围内。
4.一种用于制造一半导体结构的方法，包括：
在一半导体晶粒上形成一导电衬垫；
在所述导电衬垫上方形成一晶种层；
在所述晶种层上方界定一第一遮罩层；
在所述第一遮罩层中形成一银合金凸块本体，其包含：
制备一第一基于氰化物的电镀浴；
将所述第一基于氰化物的电镀浴的一pH值控制在6至8的范围内；
将所述半导体晶粒浸没至所述第一基于氰化物的电镀浴中；及
将自0.1ASD至0.5ASD的一电镀电流密度施加至所述半导体晶粒；及
藉由一电镀操作形成所述银合金凸块本体的一顶表面上方的一金属层，
其中将所述半导体晶粒浸没至包含KAu(CN)2的一第二基于氰化物的电镀浴中。
5.一种用于制造一半导体结构的方法，包括：
在一半导体晶粒上形成一导电衬垫；
在所述导电衬垫上方形成一晶种层；
在所述晶种层上方界定一第一遮罩层；
在所述第一遮罩层中形成一银合金凸块本体，其包含：
制备一第一基于氰化物的电镀浴；
将所述第一基于氰化物的电镀浴的一pH值控制在6至8的范围内；
将所述半导体晶粒浸没至所述第一基于氰化物的电镀浴中；及
将自0.1ASD至0.5ASD的一电镀电流密度施加至所述半导体晶粒；及
藉由一电镀操作或一无电极电镀操作形成覆盖所述银合金凸块本体的一顶表面及一侧壁的一金属层，
其中所述形成覆盖所述银合金凸块本体的所述顶表面及所述侧壁的所述金属层包含：
在所述晶种层上方形成一经修整第一遮罩层；及
在所述经修整第一遮罩层中形成所述金属层。
6.一种用于制造一半导体结构的方法，包括：
在一半导体晶粒上形成一导电衬垫；
在所述导电衬垫上方形成一晶种层；
在所述晶种层上方界定一第一遮罩层；
在所述第一遮罩层中形成一银合金凸块本体，其包含：
制备一第一基于氰化物的电镀浴；
将所述第一基于氰化物的电镀浴的一pH值控制在6至8的范围内；
将所述半导体晶粒浸没至所述第一基于氰化物的电镀浴中；及
将自0.1ASD至0.5ASD的一电镀电流密度施加至所述半导体晶粒；及
藉由一电镀操作或一无电极电镀操作形成覆盖所述银合金凸块本体的一顶表面及一侧壁的一金属层，
其中所述藉由一无电极电镀操作形成覆盖所述银合金凸块本体的一顶表面及一侧壁的一金属层包含将所述半导体晶粒浸没至包含KAu(CN)2的一无电极电镀浴中。
CN201310680470.2A 2013-11-12 2013-12-11 半导体结构及其制造方法 Active CN104099653B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/078,240 US8877630B1 (en) 2013-11-12 2013-11-12 Semiconductor structure having a silver alloy bump body and manufacturing method thereof
US14/078,240 2013-11-12

Publications (2)

Publication Number Publication Date
CN104099653A CN104099653A (zh) 2014-10-15
CN104099653B true CN104099653B (zh) 2015-10-28

Family

ID=49639774

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310680470.2A Active CN104099653B (zh) 2013-11-12 2013-12-11 半导体结构及其制造方法

Country Status (6)

Country Link
US (1) US8877630B1 (zh)
EP (1) EP2879169B1 (zh)
JP (2) JP2022008700A (zh)
KR (1) KR101545402B1 (zh)
CN (1) CN104099653B (zh)
TW (1) TWI462204B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150171039A1 (en) * 2013-12-13 2015-06-18 Chipmos Technologies Inc. Redistribution layer alloy structure and manufacturing method thereof
JP7391692B2 (ja) 2020-02-05 2023-12-05 新光電気工業株式会社 配線基板及び配線基板の製造方法
CN112981482B (zh) * 2021-02-02 2022-05-13 无锡华友微电子有限公司 一种在半导体晶圆上电镀导电材质的方法
CN113337860B (zh) * 2021-08-02 2021-11-09 华芯半导体研究院(北京)有限公司 在芯片晶圆表面进行电镀的方法及其应用
CN117238781B (zh) * 2023-11-16 2024-02-23 江苏芯德半导体科技有限公司 一种晶圆级超薄四边无引脚芯片封装方法及芯片封装结构
CN117542818B (zh) * 2024-01-10 2024-04-05 深圳市联合蓝海应用材料科技股份有限公司 一种金银合金凸块及其制备方法和应用

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516412A (en) * 1995-05-16 1996-05-14 International Business Machines Corporation Vertical paddle plating cell
CN1524292A (zh) * 2001-08-14 2004-08-25 英特尔公司 集成电路制造中用于电解电镀和无电电镀金属的表面处理装置和方法
CN101235524A (zh) * 2006-11-07 2008-08-06 恩伊凯慕凯特股份有限公司 金凹凸或者金布线形成用的非氰系电解金电镀浴液
US20110031113A1 (en) * 2006-12-01 2011-02-10 Sergey Lopatin Electroplating apparatus
CN102376863A (zh) * 2010-08-06 2012-03-14 晶元光电股份有限公司 发光元件的制造方法
CN103361683A (zh) * 2012-03-30 2013-10-23 罗门哈斯电子材料有限公司 镀液和电镀方法

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3466233A (en) * 1967-05-23 1969-09-09 Engelhard Ind Inc Gold plating
DE2121150C3 (de) * 1971-04-24 1980-08-21 Schering Ag, 1000 Berlin Und 4619 Bergkamen Verfahren zur galvanischen Abscheidung von Goldlegierungen
US4121982A (en) * 1978-02-03 1978-10-24 American Chemical & Refining Company Incorporated Gold alloy plating bath and method
JPS5824509B2 (ja) * 1980-05-08 1983-05-21 日本鉱業株式会社 銀パラジウム合金メツキ液及び銀パラジウム合金メツキ方法
JPS58176969A (ja) * 1982-04-09 1983-10-17 Toshiba Corp 半導体装置
JPH06184789A (ja) * 1992-12-22 1994-07-05 Asahi Glass Co Ltd 耐酸化性金属部材、メッキ液、及び回路装置
DE4406419C1 (de) * 1994-02-28 1995-04-13 Heraeus Gmbh W C Bad zum galvanischen Abscheiden von Silber-Gold-Legierungen
JP3285294B2 (ja) 1995-08-08 2002-05-27 太陽誘電株式会社 回路モジュールの製造方法
US6040702A (en) * 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
US5973405A (en) * 1997-07-22 1999-10-26 Dytak Corporation Composite electrical contact structure and method for manufacturing the same
US5965945A (en) * 1998-11-12 1999-10-12 Advanced Micro Devices, Inc. Graded PB for C4 pump technology
US6926796B1 (en) * 1999-01-29 2005-08-09 Matsushita Electric Industrial Co., Ltd. Electronic parts mounting method and device therefor
JP3703455B2 (ja) * 2002-12-13 2005-10-05 Ｎｅｃエレクトロニクス株式会社 二層バンプの形成方法
US7012333B2 (en) * 2002-12-26 2006-03-14 Ebara Corporation Lead free bump and method of forming the same
JP3943515B2 (ja) * 2003-03-20 2007-07-11 ローム株式会社 半導体装置の製造方法
JP4758614B2 (ja) * 2003-04-07 2011-08-31 ローム・アンド・ハース・エレクトロニック・マテリアルズ，エル．エル．シー． 電気めっき組成物および方法
JP2005123247A (ja) * 2003-10-14 2005-05-12 Seiko Epson Corp 半導体装置及びその製造方法
US20050092611A1 (en) * 2003-11-03 2005-05-05 Semitool, Inc. Bath and method for high rate copper deposition
US7713859B2 (en) * 2005-08-15 2010-05-11 Enthone Inc. Tin-silver solder bumping in electronics manufacture
US7397121B2 (en) * 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
EP1783548B1 (en) * 2005-11-08 2017-03-08 Rohm and Haas Electronic Materials LLC Method of forming a patterned layer on a substrate
JP2007142271A (ja) * 2005-11-21 2007-06-07 Tanaka Electronics Ind Co Ltd バンプ材料および接合構造
US20070114663A1 (en) * 2005-11-23 2007-05-24 Brown Derrick L Alloys for flip chip interconnects and bumps
TWI287846B (en) 2006-03-17 2007-10-01 Advanced Semiconductor Eng Method for forming metal bumps
KR100744149B1 (ko) * 2006-08-30 2007-08-01 삼성전자주식회사 은 범프를 이용한 반도체 패키지 구조 및 형성 방법
US8193636B2 (en) * 2007-03-13 2012-06-05 Megica Corporation Chip assembly with interconnection by metal bump
US7919859B2 (en) * 2007-03-23 2011-04-05 Intel Corporation Copper die bumps with electromigration cap and plated solder
SG148056A1 (en) * 2007-05-17 2008-12-31 Micron Technology Inc Integrated circuit packages, methods of forming integrated circuit packages, and methods of assembling intgrated circuit packages
JP2009071093A (ja) * 2007-09-14 2009-04-02 Ne Chemcat Corp バンプ及びバンプ形成方法
EP2221396A1 (en) * 2008-12-31 2010-08-25 Rohm and Haas Electronic Materials LLC Lead-Free Tin Alloy Electroplating Compositions and Methods
US8193555B2 (en) * 2009-02-11 2012-06-05 Megica Corporation Image and light sensor chip packages
US8153905B2 (en) * 2009-02-27 2012-04-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board and printed wiring board
US8318596B2 (en) * 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
JP2012038965A (ja) * 2010-08-09 2012-02-23 Lapis Semiconductor Co Ltd 半導体装置及びその製造方法
US9404194B2 (en) * 2010-12-01 2016-08-02 Novellus Systems, Inc. Electroplating apparatus and process for wafer level packaging
US20120325671A2 (en) * 2010-12-17 2012-12-27 Tel Nexx, Inc. Electroplated lead-free bump deposition
CN102851719B (zh) * 2011-06-29 2016-01-27 比亚迪股份有限公司 一种锆基非晶合金复合材料及其制备方法
JP5749113B2 (ja) * 2011-08-05 2015-07-15 古河電気工業株式会社 可動接点部品用被覆複合材および可動接点部品、スイッチならびにその製造方法
US8888984B2 (en) * 2012-02-09 2014-11-18 Rohm And Haas Electronic Materials Llc Plating bath and method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516412A (en) * 1995-05-16 1996-05-14 International Business Machines Corporation Vertical paddle plating cell
CN1524292A (zh) * 2001-08-14 2004-08-25 英特尔公司 集成电路制造中用于电解电镀和无电电镀金属的表面处理装置和方法
CN101235524A (zh) * 2006-11-07 2008-08-06 恩伊凯慕凯特股份有限公司 金凹凸或者金布线形成用的非氰系电解金电镀浴液
US20110031113A1 (en) * 2006-12-01 2011-02-10 Sergey Lopatin Electroplating apparatus
CN102376863A (zh) * 2010-08-06 2012-03-14 晶元光电股份有限公司 发光元件的制造方法
CN103361683A (zh) * 2012-03-30 2013-10-23 罗门哈斯电子材料有限公司 镀液和电镀方法

Also Published As

Publication number Publication date
JP6149306B2 (ja) 2017-06-21
EP2879169B1 (en) 2019-10-23
EP2879169A3 (en) 2015-08-26
EP2879169A2 (en) 2015-06-03
TW201444004A (zh) 2014-11-16
JP2015195382A (ja) 2015-11-05
KR101545402B1 (ko) 2015-08-18
US8877630B1 (en) 2014-11-04
CN104099653A (zh) 2014-10-15
JP2022008700A (ja) 2022-01-14
KR20150054607A (ko) 2015-05-20
TWI462204B (zh) 2014-11-21

Similar Documents

Publication Publication Date Title
CN104099653B (zh) 半导体结构及其制造方法
CN104051406B (zh) 半导体结构及其制造方法
CN104716120A (zh) 半导体结构及其制造方法
US8497200B2 (en) Method to form solder alloy deposits on substrates
CN103390565B (zh) 包括在优选方向生长的Cu6Sn5晶粒的电性连接结构及其制备方法
US8957323B2 (en) Electrical connecting element having nano-twinned copper, method of fabricating the same, and electrical connecting structure comprising the same
TW200536031A (en) Fretting and whisker resistant coating system and method
US9721913B2 (en) Semiconductor package and method of manufacturing thereof
TWI482231B (zh) 具有奈米雙晶銅之電性連接體、其製備方法、以及包含其之電性連接結構
US8822326B2 (en) Method for manufacturing Sn alloy bump
KR20160003078A (ko) 무연 솔더 접속을 위한 리드 프레임 구조체
Tomita et al. Cu bump interconnections in 20 μm-pitch at low temperature utilizing electroless tin-plating on 3D stacked LSI
CN112670238A (zh) 在电气部件与电子部件之间形成互连的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant