JP4746443B2 - 電子部品の製造方法 - Google Patents
電子部品の製造方法 Download PDFInfo
- Publication number
- JP4746443B2 JP4746443B2 JP2006049523A JP2006049523A JP4746443B2 JP 4746443 B2 JP4746443 B2 JP 4746443B2 JP 2006049523 A JP2006049523 A JP 2006049523A JP 2006049523 A JP2006049523 A JP 2006049523A JP 4746443 B2 JP4746443 B2 JP 4746443B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- plating
- plating solution
- seed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000007747 plating Methods 0.000 claims description 98
- 239000000758 substrate Substances 0.000 claims description 91
- 238000000034 method Methods 0.000 claims description 53
- 238000001816 cooling Methods 0.000 claims description 26
- 238000009713 electroplating Methods 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 2
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- 239000010408 film Substances 0.000 description 134
- 239000000243 solution Substances 0.000 description 45
- 239000010949 copper Substances 0.000 description 42
- 238000004090 dissolution Methods 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 11
- 239000010410 layer Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- POFFJVRXOKDESI-UHFFFAOYSA-N 1,3,5,7-tetraoxa-4-silaspiro[3.3]heptane-2,6-dione Chemical compound O1C(=O)O[Si]21OC(=O)O2 POFFJVRXOKDESI-UHFFFAOYSA-N 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 239000011800 void material Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000007788 liquid Substances 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 238000011049 filling Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000003287 bathing Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- -1 polymethylsiloxane Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 229920000412 polyarylene Polymers 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011077 uniformity evaluation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Electroplating Methods And Accessories (AREA)
Description
基体上にシード膜を形成するシード膜形成工程と、
基体温度がめっき液の温度よりも10℃以上低くなるように前記シード膜を冷却する冷却工程と、
冷却された前記シード膜をめっき液に浸漬させ、前記シード膜をカソードとして電解めっきを行なうめっき工程と、
を備え、
前記電解めっきを行なうに際し、前記めっき液に浸漬後に電解めっきを開始する開始時の電圧よりも低い電圧を前記シード膜に印加した状態で前記シード膜を前記めっき液に浸漬させることを特徴とする。
実施の形態1では、low−k膜の絶縁層にCuダマシン配線を形成する場合について、以下、図面を用いて説明する。
図1において、本実施の形態では、低誘電率の絶縁性材料からなるlow−k膜の薄膜を形成するlow−k膜形成工程(S102)、キャップ膜を形成するキャップ膜形成工程(S104)、開口部を形成する開口部形成工程(S106)、導電性材料を用いた導電性材料膜を形成する導電性材料膜形成工程として、バリアメタル膜形成工程(S108)、シード膜形成工程(S110)、冷却工程(S112)、めっき工程(S114)と、研磨工程(S116)という一連の工程を実施する。
図2では、図1のlow−k膜形成工程(S102)から開口部形成工程(S106)までを示している。それ以降の工程は後述する。
図3では、図1のバリアメタル膜形成工程(S108)からめっき工程(S114)までを示している。それ以降の工程は後述する。
めっき装置は、略円筒状で内部にめっき液670が入っためっき槽650と、めっき槽650の上方に配置され、めっき面を下に向けた基板200を着脱自在に保持するホルダ652とを備えている。めっき液670は、硫酸銅を主成分として、添加剤を加えた液を用いるとよい。めっき槽650のめっき液670底部には、上面をめっき液670に晒したアノード電極654が配置されている。アノード電極654として、例えば、含リン銅等の溶解性アノードを用いるとよい。めっき液670は、めっき槽650内へ接続された図示していない液噴射ノズルから供給される。また、めっき槽650内からオーバーフローして溢れ出ためっき液670は、図示していない排出口から排出される。排出口と液噴射ノズルは、図示していないめっき液管理装置に接続され、排出されためっき液670は、めっき液管理装置で再度、成分調整後、めっき槽650内へと戻され、循環する。また、めっき液670は、循環した状態でめっき液管理装置により例えば25℃に温度管理されている。
ここで、基板温度は、めっき液670の温度よりも10℃以上冷却することが望ましい。例えば、めっき液670の温度が25℃である場合に、基板温度を基板200が結露しない温度(例えば5℃)から15℃の範囲に制御するとよい。25℃でのめっき液670中のシード膜250の溶解速度を100%とした場合に、基板温度を15℃にすることで、めっき液670中のシード膜250の溶解速度を56%程度にまで抑えることができる。また、基板温度を5℃にすれば、めっき液670中のシード膜250の溶解速度を30%程度にまで抑えることができる。すなわち、基板温度を15℃以下にすることで、溶解速度を半分近くまで遅くすることができる。また、冷却位置は、できるだけめっき液670に近い位置が望ましい。できるだけめっき液670に近い位置にすることにより冷却後に基板200がめっき液670に接液するまでの時間を短くすることができ、冷却効果を維持することができる。
本実施の形態1では、めっき液670が入っためっき槽650に基板200表面を入槽させる際に、上述した冷却工程でシード膜250が冷やされた基板200を回転させながら入槽させる。そして、回転させたまま基板200表面をめっき液670に浸し、アノード電極654を陽極(アノード)、めっき面となる基板200のシード膜250を陰極(カソード)として所定の電流密度の電流を流し、電解めっきを行なう。また、入槽させる際に、基板200とめっき液670との間に空気が残らないように基板を所定の角度だけ傾けた状態で入槽させるとなおよい。また、後述するように、シード膜250の膜厚条件によってはカソードとなる基板200側に電圧を印加させた状態で入槽させるとよい。
図6は、図1のフローチャートに対応して実施される工程を表す工程断面図である。
図6では、図1の研磨工程(S116)を示している。
スパッタ等によりシード膜250が成膜された場合、図7に示すように、開口部150の側壁で膜厚が最小となってしまう。ここで、発明者らの実験によって、かかる最小膜厚の厚さによって、基板200を入槽させる際の最適な入槽条件が異なることを見出した。
図8(a)に示すように、基板冷却をしない場合には、開口部側壁で顕著に生じるシードCu層消失によるボイドが生じてしまう。そして、これに対処するために電圧を基板200に印加しながら入槽すると埋め込み均一性を劣化させてしまう。これに対し、上述したように、Cuめっきを施す基板200の温度を低温に制御してめっき液670中へ入槽することにより、図8(b)に示すように、めっき前のシードCu層の溶解を抑制して特に開口部側壁で顕著に生じるシードCu層消失によるめっき未析を防ぐことが可能となる。これにより、従来、電圧を印加しながら入槽する方法において問題となっていた基板端部と中心部のめっき速度の違いを、印加電圧を低減することにより軽減することができる。
実施の形態1では、基板200をめっき槽650に入槽する前に、例えば、図4に示した待機位置で冷却し、入槽時には冷却を止めていたが、これに限るものではない。
図9は、実施の形態2における基板の入槽手法の一例を示す概念図である。
図9(a)に示すように、基板200をめっき槽650に入槽する前に気体を基板200の裏面に当てながら流すことは、実施の形態1と同様である。実施の形態2では、図9(b)に示すように、基板200を冷却しながらめっき槽650に入槽させる。このように構成することにより、より冷却効果を維持することができる。また、実際のめっき中も引き続いて基板200を冷却し続けても構わない。
200 基板
250 シード膜
260 Cu膜
601 流路
670 めっき液
Claims (3)
- 基体上にシード膜を形成するシード膜形成工程と、
基体温度がめっき液の温度よりも10℃以上低くなるように前記シード膜を冷却する冷却工程と、
冷却された前記シード膜をめっき液に浸漬させ、前記シード膜をカソードとして電解めっきを行なうめっき工程と、
を備え、
前記電解めっきを行なうに際し、前記めっき液に浸漬後に電解めっきを開始する開始時の電圧よりも低い電圧を前記シード膜に印加した状態で前記シード膜を前記めっき液に浸漬させることを特徴とする電子部品の製造方法。 - 気体を用いて前記基体裏面を冷却することで前記シード膜を冷却することを特徴とする請求項1記載の電子部品の製造方法。
- 前記気体として、窒素ガスと空気のいずれかを用いることを特徴とする請求項2記載の電子部品の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006049523A JP4746443B2 (ja) | 2006-02-27 | 2006-02-27 | 電子部品の製造方法 |
US11/710,477 US20070202699A1 (en) | 2006-02-27 | 2007-02-26 | Electronic component fabrication method |
CN200710092331.2A CN101074485B (zh) | 2006-02-27 | 2007-02-27 | 电子部件制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006049523A JP4746443B2 (ja) | 2006-02-27 | 2006-02-27 | 電子部品の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007227819A JP2007227819A (ja) | 2007-09-06 |
JP4746443B2 true JP4746443B2 (ja) | 2011-08-10 |
Family
ID=38444562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006049523A Expired - Fee Related JP4746443B2 (ja) | 2006-02-27 | 2006-02-27 | 電子部品の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20070202699A1 (ja) |
JP (1) | JP4746443B2 (ja) |
CN (1) | CN101074485B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007234719A (ja) * | 2006-02-28 | 2007-09-13 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
CN104988545A (zh) * | 2015-06-30 | 2015-10-21 | 苏州华日金菱机械有限公司 | 一种电镀铜的工艺 |
US9881972B2 (en) * | 2016-05-20 | 2018-01-30 | Micron Technology, Inc. | Array of memory cells and methods of forming an array of memory cells |
US10461128B2 (en) | 2017-04-26 | 2019-10-29 | Micron Technology, Inc. | Arrays of memory cells and methods of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6042712A (en) * | 1995-05-26 | 2000-03-28 | Formfactor, Inc. | Apparatus for controlling plating over a face of a substrate |
KR20010015609A (ko) * | 1997-09-23 | 2001-02-26 | 메탈 테크놀로지, 인코포레이티드 | 전기 도금 공정 |
US6261433B1 (en) * | 1998-04-21 | 2001-07-17 | Applied Materials, Inc. | Electro-chemical deposition system and method of electroplating on substrates |
JP3631392B2 (ja) * | 1998-11-02 | 2005-03-23 | 株式会社神戸製鋼所 | 配線膜の形成方法 |
US6607640B2 (en) * | 2000-03-29 | 2003-08-19 | Applied Materials, Inc. | Temperature control of a substrate |
US7070687B2 (en) * | 2001-08-14 | 2006-07-04 | Intel Corporation | Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing |
US6846519B2 (en) * | 2002-08-08 | 2005-01-25 | Blue29, Llc | Method and apparatus for electroless deposition with temperature-controlled chuck |
US20040149584A1 (en) * | 2002-12-27 | 2004-08-05 | Mizuki Nagai | Plating method |
JP2004218080A (ja) * | 2002-12-27 | 2004-08-05 | Ebara Corp | めっき方法 |
JP2007119793A (ja) * | 2005-10-24 | 2007-05-17 | Ebara Corp | 電解めっき方法及び電解めっき装置 |
-
2006
- 2006-02-27 JP JP2006049523A patent/JP4746443B2/ja not_active Expired - Fee Related
-
2007
- 2007-02-26 US US11/710,477 patent/US20070202699A1/en not_active Abandoned
- 2007-02-27 CN CN200710092331.2A patent/CN101074485B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US20070202699A1 (en) | 2007-08-30 |
JP2007227819A (ja) | 2007-09-06 |
CN101074485A (zh) | 2007-11-21 |
CN101074485B (zh) | 2010-12-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7259091B2 (en) | Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer | |
US20060163746A1 (en) | Barrier structure for semiconductor devices | |
US7795142B2 (en) | Method for fabricating a semiconductor device | |
US7374584B2 (en) | Interconnects forming method and interconnects forming apparatus | |
JP4921945B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
US20050272258A1 (en) | Method of manufacturing a semiconductor device and semiconductor device | |
US20090020883A1 (en) | Semiconductor device and method for fabricating semiconductor device | |
JP2008300652A (ja) | 半導体装置の製造方法 | |
US7601638B2 (en) | Interconnect metallization method having thermally treated copper plate film with reduced micro-voids | |
JP2005056945A (ja) | 半導体装置の製造方法 | |
US20070173056A1 (en) | Semiconductor device fabrication method and polishing apparatus | |
JP4746443B2 (ja) | 電子部品の製造方法 | |
JP2007180496A (ja) | 金属シード層の製造方法 | |
US8878364B2 (en) | Method for fabricating semiconductor device and semiconductor device | |
US7955971B2 (en) | Hybrid metallic wire and methods of fabricating same | |
US20090191706A1 (en) | Method for fabricating a semiconductor device | |
JP2011252218A (ja) | 電子部品の製造方法及び電解めっき装置 | |
US20080020683A1 (en) | Polishing method and polishing pad | |
JP2005340460A (ja) | 半導体装置の形成方法 | |
JP2010165760A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2005340601A (ja) | 半導体装置の製造方法及び半導体装置 | |
JP2006120664A (ja) | 半導体装置の製造方法 | |
JP2006060011A (ja) | 半導体装置の製造方法 | |
JP2011124472A (ja) | 半導体装置の製造方法 | |
JP2009246228A (ja) | 研磨方法及び半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080806 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101008 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101019 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101126 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110419 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110513 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140520 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140520 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |