CN111615747B - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN111615747B CN111615747B CN201780097906.1A CN201780097906A CN111615747B CN 111615747 B CN111615747 B CN 111615747B CN 201780097906 A CN201780097906 A CN 201780097906A CN 111615747 B CN111615747 B CN 111615747B
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- heat sink
- semiconductor device
- lead frame
- semiconductor chip
- heat
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Abstract
一种半导体装置(100),其特征在于,具有:散热器(3),其具有搭载面(3b)、散热面(3a)、侧面(3c)及卡合部(3d、3e、3f、3g);半导体芯片(4),其搭载于所述散热器的搭载面;引线框(9),其与所述散热器的卡合部卡合;以及模塑树脂(7),其将所述散热器、所述半导体芯片及所述引线框封装,所述散热器的卡合部配置于所述散热器的避开搭载面的位置。所述散热器的卡合部由在所述散热器的散热面形成的销钉(3g)形成。另外,所述散热器的卡合部由在散热器的侧面形成的销钉(3f)构成。
Description
技术领域
本申请涉及半导体装置,特别地,涉及具有引线框和散热器的半导体装置的构造。
背景技术
移动电话用基站代表无线通信的器件市场。在该无线通信的器件市场中,目前,Si器件、GaAs器件是主流。在指向高功率化的领域中,对于半导体器件,由于通信容量的增大而要求宽频带化、小型化(例如,参照专利文献1)。因此,在指向高功率化的领域中,GaN器件逐渐成为主流,另一方面,对半导体器件的低成本化的要求严格。
就GaN器件而言,也正在推进通过模塑树脂将引线框封装后的低成本的模塑封装件构造的研究。在模塑封装件构造中,为了确保半导体芯片的散热性,使用具有铜或铜合金类的散热器的引线框。例如,正在开发将在散热器的上表面设置的销钉与引线框通过铆接进行固定的半导体装置。就该半导体装置而言,由于在散热器的上表面存在无法进行部件安装的区域,因此阻碍封装件的小型化。
已知在散热基板(散热器)的两端具有上边长、下边短的梯形凸部的构造(例如,参照专利文献2)。在引线的保持体的下部设置有与上述梯形凸部一致的槽形凹部。凸部和凹部嵌合。在本构造中,由于在散热器的两端存在用于嵌合的区域,因此在散热器的上表面产生无法进行部件安装的区域。这种构造的半导体装置不适用于实现封装件的小型化。
另外,已知将引线从上方插入到以从搭载部件的下表面穿透至上表面的方式设置的安装用孔中的构造(例如,参照专利文献3)。本构造在搭载部件设置有安装用孔。由于将引线插入至该孔,因此在搭载部件的上表面产生无法进行部件安装的区域。因此,该半导体装置也不适用于实现封装件的小型化。
专利文献1:日本特开昭52-150970号公报
专利文献2:日本特开昭48-066776号公报
专利文献3:日本特开2004-103790号公报
发明内容
如上说明所示,就通过铆接而将在散热器的上表面设置的销钉与引线框固定的半导体装置而言,在散热器的上表面产生无法进行部件安装的区域,因而阻碍了封装件的小型化。本申请的目的在于提供能够在散热器的上表面全部区域进行部件安装的引线框构造及半导体装置。
本申请的说明书所公开的半导体装置的特征在于,具有:散热器,其具有搭载面、散热面、侧面以及卡合部;半导体芯片,其搭载于所述散热器的搭载面;引线框,其与所述散热器的卡合部卡合;以及模塑树脂,其将所述散热器、所述半导体芯片及所述引线框封装,所述散热器的卡合部配置于所述散热器的避开搭载面的位置。
发明的效果
本申请的说明书所公开的半导体装置的特征在于,具有:散热器,其具有搭载面、散热面、侧面以及卡合部;半导体芯片,其搭载于所述散热器的搭载面;引线框,其与所述散热器的卡合部卡合;以及模塑树脂,其将所述散热器、所述半导体芯片及所述引线框封装,所述散热器的卡合部配置于所述散热器的避开搭载面的位置,由此,能够提供可在散热器的上表面全部区域进行部件安装的引线框构造及半导体装置。
附图说明
图1是对本发明的实施方式涉及的半导体装置的外观构造进行说明的图。
图2是对本发明的实施方式涉及的半导体装置的电极端子的构造进行说明的图。
图3是对实施方式1涉及的半导体装置的引线框的构造进行说明的图。
图4是对实施方式1涉及的半导体装置的散热器的构造进行说明的图。
图5是对实施方式1涉及的半导体装置的引线框的构造进行说明的图。
图6是对实施方式2涉及的半导体装置的引线框的构造进行说明的图。
图7是对实施方式3涉及的半导体装置的引线框的构造进行说明的图。
图8是对实施方式4涉及的半导体装置的引线框的构造进行说明的图。
具体实施方式
以下,一边参照附图一边对本发明的实施方式涉及的半导体装置进行说明。此外,在各图中,对相同或同样的结构部分标注相同标号,相应的各结构部的尺寸、比例尺各自独立。例如,在对结构的一部分进行了变更的剖面图之间,在对未变更的相同结构部分进行图示时,有时相同结构部分的尺寸、比例尺不同。另外,半导体装置实际上还具有多个部件,但为使说明简单,仅记载说明所需要的部分,省略其它部分。
实施方式1.
一边参照附图一边对本发明的实施方式涉及的半导体装置的构造进行说明。图1是表示实施方式涉及的半导体装置的外观的示意图。本发明的实施方式涉及的半导体装置100由漏极电极端子1、栅极电极端子2、散热器3、模塑树脂7、引线框9等构成。在散热器3搭载有半导体芯片和电路基板。半导体芯片具有漏极电极、栅极电极、源极电极。半导体芯片、电路基板、引线框9以及散热器3被模塑树脂7封装。
散热器3具有散热面(背面)、搭载面(上表面)和侧面。半导体芯片和电路基板搭载于散热器3的搭载面。从半导体芯片和电路基板散出的热经由散热器3的散热面散发至外部。就本发明的实施方式涉及的半导体装置100而言,散热器3兼作源极电极端子。本发明的实施方式涉及的半导体装置100适用于输出频率大于或等于1GHz、大于或等于1W的电力。散热器3具有大于或等于200mW/K的导热率。
在散热器3的背面(散热面)固定有被进行了引线切割的引线框9a、9b。半导体装置(封装件)通过对引线框9a、9b进行引线切割而被分离为单片。在该图中,将从漏极电极端子1朝向栅极电极端子2的方向称为X方向。另外,将从散热器3的散热面(背面或底面)朝向散热器3的搭载面(上表面)的方向称为Z方向。另外,将从引线框9a朝向引线框9b的方向称为Y方向。
图2是表示本实施方式涉及的半导体装置100的构造的剖面图。散热器3具有散热面3a、搭载面3b和侧面3c。在散热器3通过Ag膏树脂、焊料、烧结Ag等芯片键合材料8而安装有半导体芯片4和电路基板5。Si器件、GaAs器件、GaN器件等半导体芯片4配置于散热器3的上表面(搭载面)。漏极电极端子1与半导体芯片4的漏极电极通过键合导线6而连接。
栅极电极端子2与半导体芯片4的栅极电极通过键合导线6而连接。散热器3与半导体芯片4的源极电极连接。半导体芯片4与电路基板5在通过Au、Ag、Al等键合导线6而结线之后,通过模塑树脂7进行封装。散热器3的背面(散热面)开放,从模塑树脂露出。
图3是表示本实施方式涉及的散热器3的构造的斜视图。在散热器3的上表面(搭载面)通过Ag膏树脂、焊料、烧结Ag等芯片键合材料8而固定有半导体芯片4和电路基板5。引线框9具有端子大于或等于2个的引线。在散热器3的背面(散热面)固定有引线框9a、9b。半导体芯片4和电路基板5通过键合导线6而配线至漏极电极端子1和栅极电极端子2。
为了保护半导体装置100不受异物、外力等损害,半导体芯片4和电路基板5通过模塑树脂7进行封装。在该图中,引线框9a、9b被进行了引线切割。通过对引线框9实施引线切割,从而将半导体装置(封装件)分离为单片。连接漏极电极端子1和栅极电极端子2的方向(X方向)与连接引线框9a和引线框9b的方向(Y方向)正交。
图4是表示本实施方式的半导体装置100的构造的剖面示意图。在散热器3的上表面(搭载面)通过Ag膏树脂、焊料、烧结Ag等芯片键合材料8而固定有半导体芯片4和电路基板5。引线框9具有端子大于或等于2个的引线。散热器3在背面(散热面)侧具有销钉3g。通过将在散热器3的散热面形成的销钉3g与引线框9a、9b进行铆接,从而将引线框9与散热器3固定。模塑树脂7为了保护半导体装置100不受异物、外力等损害,而将半导体芯片4、电路基板5封装。通过对引线框9a、9b进行引线切割,从而将半导体装置(封装件)分离为单片。
图5是表示本实施方式的散热器3的构造的示意图。该图示出散热器3的背侧的形状。散热器3在其背面(散热面)形成有成为卡合部的销钉3g1和销钉3g2。在引线框9a及引线框9b开设有与销钉3g卡合的卡合孔9x。引线框9a的卡合孔9x嵌合至销钉3g1而卡合。引线框9b的卡合孔9x嵌合至销钉3g2而卡合。通过将散热器3的销钉3g与引线框9铆接而将引线框9与散热器3固定。在散热器3的表面(搭载面)安装有半导体芯片4和电路基板5。
就为了将散热器3与引线框9固定而在散热器3的上表面(搭载面)存在销钉和铆接部的构造而言,产生无法用于部件安装的区域。就本实施方式涉及的半导体装置而言,在散热器的上表面(搭载面)不存在销钉、铆接部。由于能够将散热器的上表面全部用于部件安装,所以能够实现封装件(半导体装置)的小型化。即,本实施方式涉及的半导体装置由于能够将散热器的上表面(搭载面)全部用于部件安装,因此与以往相比,能够实现封装件(半导体装置)的小型化。
本实施方式涉及的半导体装置是输出频率大于或等于1GHz、大于或等于1W的电力的半导体装置,其特征在于,具有导热率大于或等于200mW/K的散热器,利用具有端子大于或等于2个的引线的引线框,通过将引线框插入至在散热器的侧面设置的槽而将引线框与散热器固定,将Si器件、GaAs器件、GaN器件通过Ag膏树脂、焊料、烧结Ag等芯片键合材料而安装于散热器的上表面,通过Au、Ag、Al等键合导线而结线之后,通过模塑树脂进行封装。
即,本发明的实施方式涉及的半导体装置100的特征在于,具有:散热器,其具有搭载面、散热面、侧面及卡合部;半导体芯片,其搭载于所述散热器的搭载面;引线框,其与所述散热器的卡合部卡合;以及模塑树脂,其将所述散热器、所述半导体芯片及所述引线框封装,所述散热器的卡合部配置于所述散热器的避开搭载面的位置。
实施方式2.
本发明的实施方式涉及的半导体装置100由漏极电极端子1、栅极电极端子2、散热器3、模塑树脂7、引线框9等构成。在散热器3搭载有半导体芯片和电路基板。半导体芯片具有漏极电极、栅极电极、源极电极。半导体芯片、电路基板、引线框9以及散热器3通过模塑树脂7进行封装。散热器3兼作源极电极端子。
本发明的实施方式涉及的半导体装置100适用于输出频率大于或等于1GHz、大于或等于1W的电力。散热器3具有大于或等于200mW/K的导热率。散热器3具有散热面(背面)、搭载面(上表面)和侧面。在散热器3的背面固定有引线框9。半导体芯片和电路基板搭载于散热器3的搭载面。从半导体芯片和电路基板散出的热经由散热器3的散热面散发至外部。
图6是表示本发明的实施方式涉及的半导体装置100的构造的剖面示意图。在散热器3的上表面(搭载面)通过Ag膏树脂、焊料、烧结Ag等芯片键合材料8而固定有半导体芯片4和电路基板5。引线框9具有端子大于或等于2个的引线。散热器3在侧面具有成为卡合部的销钉3f。在引线框9a及引线框9b开设有与销钉3f卡合的卡合孔9x。引线框9a的卡合孔9x嵌合至左侧的销钉3f而卡合。引线框9b的卡合孔9x嵌合至右侧的销钉3f而卡合。
通过将散热器3的销钉3f与引线框9a、9b铆接,从而将引线框9与散热器3固定。本发明的实施方式涉及的模塑树脂7为了保护半导体装置100不受异物、外力等损害,而将半导体芯片4和电路基板5封装。本实施方式的半导体装置100的特征在于,通过将引线框铆接至在散热器的侧面设置的销钉而将引线框与散热器固定。
就为了将散热器3与引线框9固定而在散热器3的上表面(搭载面)存在销钉和铆接部的构造而言,产生无法用于部件安装的区域。就本实施方式涉及的半导体装置而言,在散热器的上表面(搭载面)不存在销钉、铆接部。由于能够将散热器的上表面(搭载面)全部用于部件安装,所以能够实现封装件(半导体装置)的小型化。即,本实施方式涉及的半导体装置能够将散热器的上表面全部用于部件安装,因此与以往相比,能够实现封装件(半导体装置)的小型化。
实施方式3.
本发明的实施方式涉及的半导体装置100由漏极电极端子1、栅极电极端子2、散热器3、模塑树脂7、引线框9等构成。在散热器3搭载有半导体芯片和电路基板。半导体芯片具有漏极电极、栅极电极、源极电极。将半导体芯片、电路基板、引线框9以及散热器3通过模塑树脂7进行封装。散热器3兼作源极电极端子。
本发明的实施方式涉及的半导体装置100适用于输出频率大于或等于1GHz、大于或等于1W的电力。散热器3具有大于或等于200mW/K的导热率。散热器3具有散热面(背面)、搭载面(上表面)和侧面。在散热器3的背面固定有引线框9。半导体芯片和电路基板搭载于散热器3的搭载面。从半导体芯片和电路基板散出的热经由散热器3的散热面散发至外部。
图7是表示本发明的实施方式涉及的半导体装置100的构造的剖面示意图。在散热器3的上表面(搭载面)通过Ag膏树脂、焊料、烧结Ag等芯片键合材料8而固定有半导体芯片4和电路基板5。引线框9具有端子大于或等于2个的引线。散热器3在背面具有成为卡合部的槽3e。槽3e从散热器3的背面朝向上表面而沿纵向形成,不穿透散热器的上表面。
引线框9a嵌合至散热器3的左侧的槽3e而卡合。引线框9b嵌合至散热器3的右侧的槽3e而卡合。通过将引线框9a及引线框9b插入至散热器3的槽3e而将引线框9与散热器3固定。
本发明的实施方式涉及的模塑树脂7为了保护半导体装置100不受异物、外力等损害,而将半导体芯片4和电路基板5封装。因此,本发明的实施方式涉及的半导体装置100的特征在于,通过将引线框插入至在散热器的背面设置的槽而将引线框与散热器固定。此外,本发明的实施方式涉及的槽可以是V字形也可以是U字形。
就为了将散热器3与引线框9固定而在散热器3的上表面(搭载面)存在销钉和铆接部的构造而言,产生无法用于部件安装的区域。就本实施方式涉及的半导体装置而言,在散热器的上表面(搭载面)不存在销钉、铆接部。由于能够将散热器的上表面全部用于部件安装,所以能够实现封装件(半导体装置)的小型化。即,本实施方式涉及的半导体装置能够将散热器的上表面全部用于部件安装,因此与以往相比,能够实现封装件(半导体装置)的小型化。
实施方式4.
本发明的实施方式涉及的半导体装置100由漏极电极端子1、栅极电极端子2、散热器3、模塑树脂7、引线框9等构成。在散热器3搭载有半导体芯片和电路基板。半导体芯片具有漏极电极、栅极电极、源极电极。将半导体芯片、电路基板、引线框9以及散热器3通过模塑树脂7进行封装。散热器3兼作源极电极端子。
本发明的实施方式涉及的半导体装置100适用于输出频率大于或等于1GHz、大于或等于1W的电力。散热器3具有大于或等于200mW/K的导热率。散热器3具有散热面(背面)、搭载面(上表面)和侧面。在散热器3的背面固定有引线框9。半导体芯片和电路基板搭载于散热器3的搭载面。从半导体芯片和电路基板散出的热经由散热器3的散热面散发至外部。
图8是表示本发明的实施方式涉及的半导体装置100的构造的剖面示意图。在散热器3的上表面(搭载面)通过Ag膏树脂、焊料、烧结Ag等芯片键合材料8而固定有半导体芯片4和电路基板5。引线框9具有端子大于或等于2个的引线。散热器3在侧面具有成为卡合部的槽3d。槽3d在散热器3的侧面遍及侧面的全长而形成。
引线框9a嵌合至散热器3的左侧的槽3d而卡合。引线框9b嵌合至散热器3的右侧的槽3d而卡合。通过将引线框9a和引线框9b插入至散热器3的槽3d而将引线框9与散热器3固定。
本发明的实施方式涉及的模塑树脂7为了保护半导体装置100不受异物、外力等损害,而将半导体芯片4和电路基板5封装。因此,本发明的实施方式涉及的半导体装置的特征在于,通过将引线框插入至在散热器的侧面设置的槽而将引线框与散热器固定。此外,本发明的实施方式涉及的槽可以是V字形也可以是U字形。
就为了将散热器3与引线框9固定而在散热器3的上表面(搭载面)存在销钉和铆接部的构造而言,产生无法用于部件安装的区域。就本发明的实施方式涉及的半导体装置而言,在散热器的上表面(搭载面)不存在销钉、铆接部。由于能够将散热器的上表面(搭载面)全部用于部件安装,所以能够实现封装件(半导体装置)的小型化。即,本发明的实施方式涉及的半导体装置由于能够将散热器的上表面全部用于部件安装,因此与以往相比,能够实现封装件(半导体装置)的小型化。
此外,本申请说明书所公开的技术能够在所公开的技术构思的范围内,对各实施方式自由地进行组合,或者对各实施方式适当地进行变形、省略。
标号的说明
1漏极电极端子,2栅极电极端子,3散热器,3d槽,3e槽,3f销钉,3g销钉,4半导体芯片,5电路基板,6键合导线,7模塑树脂,8芯片键合材料,9引线框,9a引线框,9b引线框,100半导体装置
Claims (6)
1.一种半导体装置,其特征在于,具有:
散热器,其具有搭载面、散热面、侧面、第1卡合部以及第2卡合部;
半导体芯片,其搭载于所述散热器的搭载面;
第1引线框,其与所述散热器的第1卡合部卡合;
第2引线框,其与所述散热器的第2卡合部卡合;以及
模塑树脂,其将所述散热器、所述半导体芯片、所述第1引线框及所述第2引线框封装,
所述散热器具有的第1卡合部及第2卡合部配置于所述散热器的避开搭载面的位置,
所述散热器具有的第1卡合部及第2卡合部由在所述散热器具有的侧面形成的销钉或槽构成。
2.根据权利要求1所述的半导体装置,其特征在于,
所述散热器具有的散热面从所述模塑树脂露出。
3.根据权利要求1所述的半导体装置,其特征在于,
所述半导体芯片具有漏极电极、栅极电极、源极电极,
所述散热器与所述半导体芯片具有的源极电极连接。
4.根据权利要求3所述的半导体装置,其特征在于,还具有:
漏极电极端子,其与所述半导体芯片的漏极电极通过键合导线而连接;以及
栅极电极端子,其与所述半导体芯片的栅极电极通过键合导线而连接。
5.根据权利要求4所述的半导体装置,其特征在于,
连接所述第1引线框和所述第2引线框的方向与连接所述漏极电极端子和所述栅极电极端子的方向正交。
6.根据权利要求1所述的半导体装置,其特征在于,
还具有搭载于所述散热器的搭载面的电路基板,
所述电路基板被所述模塑树脂封装。
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Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58223353A (ja) * | 1982-06-21 | 1983-12-24 | Toshiba Corp | 半導体装置 |
JPH0645348U (ja) * | 1992-11-24 | 1994-06-14 | 富士通テン株式会社 | ハイブリッドic用リード端子 |
US5328870A (en) * | 1992-01-17 | 1994-07-12 | Amkor Electronics, Inc. | Method for forming plastic molded package with heat sink for integrated circuit devices |
WO1996027903A1 (en) * | 1995-03-06 | 1996-09-12 | National Semiconductor Corporation | Heat sink for integrated circuit packages |
JPH08255853A (ja) * | 1995-03-16 | 1996-10-01 | Ibiden Co Ltd | 電子部品搭載装置 |
KR0137066B1 (ko) * | 1994-09-07 | 1998-04-24 | 황인길 | 히트싱크 내장형 반도체패키지 및 그 제조방법 |
JPH11150216A (ja) * | 1997-11-19 | 1999-06-02 | Denso Corp | 樹脂封止型半導体部品及びその製造方法 |
US6117709A (en) * | 1997-11-12 | 2000-09-12 | Denso Corporation | Resin sealing type semiconductor device and method of manufacturing the same |
US6239487B1 (en) * | 1998-02-11 | 2001-05-29 | Hyundai Electronics Industries Co., Ltd. | Lead frame with heat spreader and semiconductor package therewith |
JP2004228447A (ja) * | 2003-01-24 | 2004-08-12 | Nec Semiconductors Kyushu Ltd | 半導体装置及びその製造方法 |
JP2006073670A (ja) * | 2004-08-31 | 2006-03-16 | Denso Corp | 集積回路装置 |
JP2006093470A (ja) * | 2004-09-24 | 2006-04-06 | Toshiba Corp | リードフレーム、発光装置、発光装置の製造方法 |
WO2006065007A1 (en) * | 2004-12-16 | 2006-06-22 | Seoul Semiconductor Co., Ltd. | Leadframe having a heat sink supporting ring, fabricating method of a light emitting diodepackage using the same and light emitting diodepackage fabbricated by the method |
JP2008028311A (ja) * | 2006-07-25 | 2008-02-07 | Mitsubishi Electric Corp | 半導体装置 |
CN102693953A (zh) * | 2011-03-22 | 2012-09-26 | 株式会社东芝 | 半导体装置及其制造方法 |
JP2012222159A (ja) * | 2011-04-08 | 2012-11-12 | Denso Corp | 半導体装置及び半導体装置の製造方法 |
JP2012248774A (ja) * | 2011-05-31 | 2012-12-13 | Denso Corp | 半導体装置およびその製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS514906B2 (zh) | 1971-12-15 | 1976-02-16 | ||
JPS52105970A (en) | 1976-03-04 | 1977-09-06 | Tdk Electronics Co Ltd | Method of producing magnetic tape storage case |
JPS52150970A (en) | 1976-06-11 | 1977-12-15 | Hitachi Ltd | Resin molded type semiconductor device |
JPS60103651A (ja) * | 1983-11-11 | 1985-06-07 | Hitachi Ltd | 半導体装置 |
JPH10284658A (ja) * | 1997-04-04 | 1998-10-23 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP3854208B2 (ja) | 2002-09-09 | 2006-12-06 | 株式会社三井ハイテック | リードフレームおよびリードフレームの製造方法 |
JP2005011899A (ja) * | 2003-06-17 | 2005-01-13 | Himeji Toshiba Ep Corp | リードフレーム及びそれを用いた電子部品 |
JP4100332B2 (ja) * | 2003-11-12 | 2008-06-11 | 株式会社デンソー | 電子装置およびその製造方法 |
WO2006059828A1 (en) | 2004-09-10 | 2006-06-08 | Seoul Semiconductor Co., Ltd. | Light emitting diode package having multiple molding resins |
TWI405349B (zh) | 2004-10-07 | 2013-08-11 | Seoul Semiconductor Co Ltd | 側照明透鏡以及使用此透鏡的發光元件 |
KR100579397B1 (ko) * | 2004-12-16 | 2006-05-12 | 서울반도체 주식회사 | 리드프레임과 직접 연결된 히트싱크를 채택하는 발광다이오드 패키지 |
JP2012033665A (ja) * | 2010-07-30 | 2012-02-16 | On Semiconductor Trading Ltd | 半導体装置及びその製造方法 |
JP2015035554A (ja) * | 2013-08-09 | 2015-02-19 | 住友電工デバイス・イノベーション株式会社 | 半導体装置 |
US10199303B1 (en) * | 2017-08-07 | 2019-02-05 | Nxp Usa, Inc. | Molded air cavity packages and methods for the production thereof |
-
2017
- 2017-12-27 DE DE112017008323.0T patent/DE112017008323T5/de not_active Withdrawn
- 2017-12-27 JP JP2018527244A patent/JP6373545B1/ja active Active
- 2017-12-27 CN CN201780097906.1A patent/CN111615747B/zh active Active
- 2017-12-27 WO PCT/JP2017/046929 patent/WO2019130474A1/ja active Application Filing
- 2017-12-27 KR KR1020207016680A patent/KR102351764B1/ko active IP Right Grant
- 2017-12-27 US US16/756,450 patent/US11335619B2/en active Active
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58223353A (ja) * | 1982-06-21 | 1983-12-24 | Toshiba Corp | 半導体装置 |
US5328870A (en) * | 1992-01-17 | 1994-07-12 | Amkor Electronics, Inc. | Method for forming plastic molded package with heat sink for integrated circuit devices |
JPH0645348U (ja) * | 1992-11-24 | 1994-06-14 | 富士通テン株式会社 | ハイブリッドic用リード端子 |
KR0137066B1 (ko) * | 1994-09-07 | 1998-04-24 | 황인길 | 히트싱크 내장형 반도체패키지 및 그 제조방법 |
WO1996027903A1 (en) * | 1995-03-06 | 1996-09-12 | National Semiconductor Corporation | Heat sink for integrated circuit packages |
JPH08255853A (ja) * | 1995-03-16 | 1996-10-01 | Ibiden Co Ltd | 電子部品搭載装置 |
US6117709A (en) * | 1997-11-12 | 2000-09-12 | Denso Corporation | Resin sealing type semiconductor device and method of manufacturing the same |
JPH11150216A (ja) * | 1997-11-19 | 1999-06-02 | Denso Corp | 樹脂封止型半導体部品及びその製造方法 |
US6239487B1 (en) * | 1998-02-11 | 2001-05-29 | Hyundai Electronics Industries Co., Ltd. | Lead frame with heat spreader and semiconductor package therewith |
JP2004228447A (ja) * | 2003-01-24 | 2004-08-12 | Nec Semiconductors Kyushu Ltd | 半導体装置及びその製造方法 |
JP2006073670A (ja) * | 2004-08-31 | 2006-03-16 | Denso Corp | 集積回路装置 |
JP2006093470A (ja) * | 2004-09-24 | 2006-04-06 | Toshiba Corp | リードフレーム、発光装置、発光装置の製造方法 |
WO2006065007A1 (en) * | 2004-12-16 | 2006-06-22 | Seoul Semiconductor Co., Ltd. | Leadframe having a heat sink supporting ring, fabricating method of a light emitting diodepackage using the same and light emitting diodepackage fabbricated by the method |
JP2008028311A (ja) * | 2006-07-25 | 2008-02-07 | Mitsubishi Electric Corp | 半導体装置 |
CN102693953A (zh) * | 2011-03-22 | 2012-09-26 | 株式会社东芝 | 半导体装置及其制造方法 |
JP2012222159A (ja) * | 2011-04-08 | 2012-11-12 | Denso Corp | 半導体装置及び半導体装置の製造方法 |
JP2012248774A (ja) * | 2011-05-31 | 2012-12-13 | Denso Corp | 半導体装置およびその製造方法 |
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JP6373545B1 (ja) | 2018-08-15 |
CN111615747A (zh) | 2020-09-01 |
WO2019130474A1 (ja) | 2019-07-04 |
KR102351764B1 (ko) | 2022-01-14 |
JPWO2019130474A1 (ja) | 2019-12-26 |
US20200258806A1 (en) | 2020-08-13 |
KR20200087200A (ko) | 2020-07-20 |
US11335619B2 (en) | 2022-05-17 |
DE112017008323T5 (de) | 2020-09-10 |
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