CN110391142A - 形成半导体器件的方法 - Google Patents

形成半导体器件的方法 Download PDF

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Publication number
CN110391142A
CN110391142A CN201810970797.6A CN201810970797A CN110391142A CN 110391142 A CN110391142 A CN 110391142A CN 201810970797 A CN201810970797 A CN 201810970797A CN 110391142 A CN110391142 A CN 110391142A
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China
Prior art keywords
dielectric layer
layer
corona treatment
metal
seed layer
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CN201810970797.6A
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CN110391142B (zh
Inventor
谢昀蓁
蔡惠榕
郭宏瑞
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例提供一种形成半导体器件的方法，其包括在介电层上形成金属晶种层，以及在金属晶种层上方形成图案化掩模。图案化掩模中的开口位于介电层的第一部分上方，且图案化掩模与介电层的第二部分重叠。该方法进一步包括在开口中镀金属区域，去除图案化掩模以暴露金属晶种层的一些部分，蚀刻金属晶种层的暴露部分，对介电层的第二部分的表面实施等离子体处理，以及对介电层的第二部分的表面实施蚀刻处理。

Description

形成半导体器件的方法
技术领域
本发明涉及半导体领域，并且更具体地，涉及形成半导体器件的方法。
背景技术
随着半导体技术的演化，半导体芯片/管芯变得越来越小。与此同时，更多的功能需要集成到半导体管芯中。相应地，半导体管芯需要具有封装到更小区域中的越来越多数量的I/O焊盘，且I/O焊盘的密度随时间快速升高。因此，半导体管芯的封装变得更加困难，这不利地影响封装领域。
常规的封装技术可分为两类。在第一类中，晶元上的管芯在被切割之前封装。这种封装技术具有一些有利特征，诸如更大的生产量和更低的成本。此外，需要更少的底部填充或模制化合物。然而，这种封装技术还遭受弊端。由于管芯的尺寸变得越来越小，且相应的封装件仅可为扇入型封装件，其中每个管芯的I/O焊盘受限于相应管芯的表面正上方的区域。由于管芯的有限面积，I/O焊盘的数量由于I/O焊盘的间距的限制而受到限制。如果要减小焊盘的间距，可能出现锡短路。此外，在固定球尺寸要求下，焊料球必须具有特定尺寸，这又会限制能够封装在管芯的表面上的焊料球的数量。
在另一类封装中，管芯在其封装之前从晶元切割。这种封装技术的有利特征是可能形成扇出封装件，这意味着管芯上的I/O焊盘可分配到比管芯更大的面积，并且因此封装在管芯的表面上的I/O焊盘的数量可增加。这种封装技术的另一有利特征在于“已知合格之晶片”被封装，有缺陷的管芯被丢弃，因此不会在有缺陷的管芯上浪费成本和努力。
在扇出封装件中，器件管芯封装在模制化合物中，然后对模制化合物平坦化以暴露器件管芯。介电层形成在器件管芯上方。再分布线形成在介电层中以连接至器件管芯。扇出封装件还可包括穿透模制化合物的通孔。
发明内容
根据本发明的一个方面，提供一种形成半导体器件的方法，包括：在第一介电层上形成金属晶种层；在金属晶种层上方形成图案化掩模，其中图案化掩模中的开口位于第一介电层的第一部分上方，且图案化掩模与第一介电层的第二部分重叠；在开口中镀金属区域；去除图案化掩模以暴露金属晶种层的一些部分；蚀刻金属晶种层的暴露部分；对第一介电层的第二部分的表面实施第一等离子体处理；以及对第一介电层的第二部分的表面实施蚀刻工艺。
根据本发明的另一方面，提供一种形成半导体器件的方法，包括：在介电层上方形成金属区域；实施第一等离子体处理以轰击介电层，其中在第一等离子体处理期间施加偏置电压；实施湿蚀刻，其中介电层的表面暴露至用于湿蚀刻的化学制品；以及将金属区域封装在封装材料中，其中，介电层的表面与封装材料接触。
根据本发明的另一方面，提供一种形成半导体器件的方法，包括：形成高于介电层突出的金属柱；轰击介电层的表面层；实施蚀刻工艺以去除介电层的表面层上的金属颗粒；以及对金属柱实施等离子体处理。
附图说明
当阅读附图时从以下详细描述将更好地理解本公开的一些方面。应当注意，根据本工业中的标准实践，各个附图未按照比例绘制。事实上，各个附图的尺寸可随意增大或减小以便于讨论。
图1至图16例示了根据一些实施例的形成封装件的中间阶段的截面图。
图17至图21例示了根据一些实施例的形成包括背面再分布线的封装件的中间阶段的截面图。
图22至图24例示了根据一些实施例的形成无通孔的封装件的中间阶段的截面图。
图25例示了根据一些实施例的形成封装件的流程图。
具体实施方式
以下公开提供了许多不同的实施例，或者例如，用于实施本发明的不同特征。以下描述了部件和装置的具体示例以简化本公开。当然，这些仅仅是示例而不意在限制。例如，如下描述中在第二部件上方或上形成第一部件可包括第一部件和第二部件直接接触形成的实施例，也可包括附加部件可形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。此外，本公开在各个示例中可重复参考标号和/或字母。这种重复是出于简洁明了的目的且本身并不指示所讨论的各个实施例和/或配置之间的关系。
此外，空间相对术语，诸如“下面”、“下方”、“下”、“上面”、“上”等，在本文中可用于易于描述，以描述如附图所示的一个元件或部件相对于另一元件(或另一元件)或部件(或多个部件)的关系。该空间相对术语意在涵盖除了附图中描绘的定向之外在使用或操作中的器件的不同定向。装置还可以其他方式定向(旋转90度或以其他方向)且本文中使用的空间相对描述可同样相应地解释。
根据各个示例性实施例提供集成扇出(InFO)封装件及其形成方法。根据一些实施例例示了形成InFO封装件的中间阶段。讨论了一些实施例的各种变体。遍及各个附图和示例性实施例，相同的参考标号用于表示相同的元件。
图1至图16例示了根据一些实施例的形成封装件的中间阶段的截面图。在图1至图16中示出的步骤还在图25所示的流程图200中示意性示出。
参考图1，提供载体20，且离型膜22涂覆在载体20上。相应的工艺如在图25中示出的流程图中的工艺202所示。载体20由透明材料形成，并且可为玻璃载体、陶瓷载体、有机载体等。载体20可具有圆形俯视形状。离型膜22可与载体20的顶部表面物理接触。离型膜22可由光热转换(LTHC)图涂层料形成，并且可通过涂覆施加到载体20上。根据本公开的一些实施例，LTHC涂层材料能够在光/辐射(诸如激光)的热量下分解，因此可将载体20从形成在其上的结构释放。
根据本公开的一些实施例，如图1所示，介电缓冲层24形成在LTHC涂层材料22上。相应的工艺还如在图25中示出的流程图中的工艺202所示。根据本公开的一些方面，介电缓冲层24由有机材料形成，其可为聚合物，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。
图2至图5例示了金属柱32的形成。参考图2，金属晶种层26例如通过物理汽相沉积(PVD)形成。相应的工艺如在图25中示出的流程图中的工艺204所示。金属晶种层26形成为掩盖层(blanket layer)，其可包括粘合层26A和位于粘合层26A上方的含铜层26B。粘合层26A包括不同于铜的金属，且可包括钛、钽、氮化钛、氮化钽等。含铜层26B可由纯铜或大致纯铜(例如，铜百分比大于95％)或铜合金形成。图案化的光刻胶28形成在金属晶种层26上方，且例如通过曝光和显影形成开口30。相应的工艺还如在图25中示出的流程图中的工艺204所示。
接下来，如图3所示，金属柱32’例如通过镀，可为电化学镀(ECP)或化学镀形成在开口30中。相应的工艺如在图25中示出的流程图中的工艺206所示。金属柱32’可由铜或铜合金形成。镀金属材料可为铜或铜合金。金属柱32’的顶部表面低于光刻胶28的顶部表面，使得金属柱32’的形状由开口30限制。金属柱32’可具有大致竖直和直立的边缘。在用于形成金属柱32’的镀之后，去除光刻胶28。
接下来，去除含铜层26B的直接位于去除的光刻胶28下面的部分。相应的工艺如在图25中示出的流程图中的工艺208所示。所得结构在图4中示出。含铜层26B的剩余部分称作26B’。蚀刻可为湿蚀刻或干蚀刻，并且可包括各向同性蚀刻工艺。蚀刻剂可包括H3PO4/H2O2/H2O的混合物、H2SO4/H2O2/H2O的混合物、(NH4)2S2O8/H2O的混合物或选自HCl(H2O中)的化学制品、HCL/CuCl2的混合物、FeCl3或以上的组合。
在蚀刻含铜层26B之后，暴露粘合层26A。然后实施第二蚀刻工艺，所得结构在图5中示出。可通过湿蚀刻来蚀刻粘合层26A。选择蚀刻化学制品/溶液来腐蚀粘合层26A，且不腐蚀含铜晶种层26B和金属柱32’。蚀刻化学制品/溶液可包括HF、HF/H2O2的混合物、H2O2(具有一些其他添加剂)、NaHCO3、NaOH、NaHCO3/H2O2的混合物、NaHCO3/NaOH/H2O2的混合物的溶液或碱金属氢氧化物溶液。碱金属氢氧化物溶液可为NaOH、KOH等的溶液。在整个描述中，铜晶种层26的剩余部分26A’和26B’以及上面的金属柱32’组合称为金属柱32。
在蚀刻粘合层26A之后，可能剩下含金属颗粒，其为剩余在介电缓冲层24上的粘合层26A的残渣。含金属颗粒在图5中表示为29。含金属颗粒29可包括钛、钽、氮化钛、氮化钽等，这取决于粘合层26A的组分。含金属颗粒29是导电的，因此不利地增大了所得封装件中的泄露电流。含金属颗粒29相对疏松，还可能导致介电缓冲层24与随后分配的封装材料48(图9)之间的分层。特别地，由于封装材料48和介电缓冲层24是不同类型的材料，且不同类型材料之间的粘合性通常不如由相同类型材料形成的两个层之间的粘合性好，因此无论含金属颗粒29是否存在，封装材料48和介电缓冲层24之间的粘合性都可能不太好。含金属颗粒29的产生进一步恶化了粘合性。通过去除含金属颗粒29，根据本公开的一些实施例因此避免降低的粘合性。
参考图5，实施由箭头31表示的(第一等离子体)处理。相应的工艺如在图25中示出的流程图中的工艺210中所示。根据本公开的一些实施例，该处理为干式工艺，其通过等离子体处理实现，其中轰击介电缓冲层24。用于产生等离子体的工艺气体可包括氮气(N2)、氩气(Ar)或二者组合等。除了上述工艺气体，还可添加氧气(O2)。轰击具有疏松含金属颗粒29且增大介电缓冲层24的表面粗糙度的功能。氧气具有进一步增大介电缓冲层24的粗糙度的功能。增大介电缓冲层24的表面粗糙度导致介电缓冲层24和随后分配的封装材料之间的粘合性提高。应当领会，由于轰击效果，一些含金属颗粒29可被喷溅以附接到金属柱32的侧壁。
根据本公开的一些实施例，通过施加具有在约1KHz到约103MHz之间的范围内的频率的射频(RF)功率以便产生等离子体来实施等离子体处理。此外，施加DC偏置功率(和电压)以使等离子体中的离子的运动为定向的，以便轰击介电缓冲层24。DC偏置功率和电压选定为足够高以疏松含金属颗粒29并且使介电缓冲层24的表面足够粗糙，但是不会高到导致通过该处理产生变成污染物而恶化表面粘合性的副产物。例如，DC偏置功率可在约100瓦特到约1000瓦特之间的范围内。等离子体处理可持续在约30秒到约3分钟的范围内的时间段。工艺气体的流速可在约100sccm到约1000sccm之间的范围内。
在该处理之后，如图6所示，可实施蚀刻工艺(由箭头33表示)。相应的工艺如在图25中示出的流程图中的工艺212所示。蚀刻工艺可为湿蚀刻工艺或干蚀刻工艺。化学制品可选自用于蚀刻粘合层26A的候选化学制品的相同组。根据本公开的一些实施例，通过湿蚀刻工艺实施蚀刻，且可包括HF、HF/H2O2的混合物、H2O2(具有一些其他添加剂)、NaHCO3、NaOH、NaHCO3/H2O2的混合物、NaHCO3/NaOH/H2O2的混合物的溶液或碱金属氢氧化物溶液。该蚀刻可使用与用于蚀刻粘合层26A相同或不同的化学制品。蚀刻时间取决于含金属颗粒29的类型和用于湿蚀刻的化学制品的类型。例如，当使用HF来湿蚀刻时，蚀刻可持续在约10秒到约3分钟的范围内的时间段。
在蚀刻工艺中，蚀刻疏松化的含金属颗粒29，使得在介电缓冲层24上/中的含金属颗粒29的量减小。此外，如果含金属颗粒29喷溅到金属柱32的侧壁(在图5中示出的步骤期间)，则喷射的含金属颗粒29也被蚀刻。
图7例示了在蚀刻之后实施的第二处理(由箭头35表示)。相应的工艺如在图25中示出的流程图中的工艺214所示。第二处理具有氧化金属柱32的表面层以在金属柱32的表面上形成薄氧化物层以使金属柱32与随后分配的封装材料48(图9)之间的粘合性提高的功能。根据本公开的一些实施例，第二处理包括等离子体处理，其中工艺气体包括氧气(O2)和附加气体，诸如N2、Ar等。可使用与第一处理相同的工艺气体实施第二处理，或使用不同于第一处理中所用的工艺气体实施第二处理。第二处理不用于轰击介电缓冲层24。相应地，第二处理中的偏置功率(或电压)低于在第一处理中使用的偏置功率(或电压)。例如，第二处理中的偏置功率(或电压)低于用于第一处理的偏置功率(或电压)的50％、或低于30％。根据本公开的一些实施例，在第二处理中不施加偏置功率/电压。应当领会，尽管在添加氧气时，第一处理也具有氧化金属柱32的表面层的效果，但形成的金属氧化物在湿蚀刻工艺中被去除。因此实施第二处理以在金属柱32的表面上重新形成金属氧化物层(未示出)。
图8例示了器件36(替代地称作封装部件)的放置/附接。相应的工艺如在图25中示出的流程图中的工艺216所示。器件36可为器件管芯，因此此后称作器件管芯36，但器件36还可为封装件、管芯堆叠件等。器件管芯36通过管芯附接膜(DAF)34附接到介电缓冲层24，其中管芯附接膜34为在器件管芯36放置在介电缓冲层24上之前预附接在器件管芯36上的粘附膜。器件管芯36可包括具有与相应的下面的DAF34物理接触的背部表面(面向下的表面)的半导体衬底。器件管芯36可包括诸如有源器件的集成电路器件，其包括在半导体衬底的前部表面(面向上的表面)处的晶体管(未示出)。根据本公开的一些实施例，器件管芯36包括一个或多个逻辑管芯，其可为中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯。由于载体20是晶圆级载体，尽管示出了两个器件管芯36，但是在管芯放置步骤中，多个相同的器件管芯36组可放置在介电缓冲层24上方，且可将器件管芯组分配为包括多个行和多个列的阵列。
根据一些示例性实施例，金属柱42(诸如铜柱)预成型为器件管芯36的一部分，且金属柱42通过下面的金属焊盘40(例如，可为铝焊盘)电连接至集成电路器件，诸如器件管芯36中的晶体管(未示出)。尽管在每个器件36中示出一个金属焊盘40和一个金属柱42，但是每个器件管芯36可包括多个金属焊盘和多个上覆的金属柱42。根据本公开的一些实施例，诸如聚合物层44的介电层作为顶部介电层填充相同器件管芯中邻近的金属柱42之间的间隙。钝化层43还可形成在聚合物层44下面。顶部介电层44还可包括覆盖和保护金属柱42的一部分。根据本公开的一些实施例，聚合物层44可由PBO或聚酰亚胺形成。应当领会，由本公开的实施例预期，器件管芯36可具有包括不同的顶部介电层的不同设计。例如，实施例还可预期，可形成或省略可为由聚酰亚胺、PBO等形成的聚合物层的介电层45。
接下来，参考图9，器件管芯36和金属柱32封装在封装材料48中。相应的工艺如在图25中示出的流程图中的工艺218所示。相应地，金属柱32在后文中称作通孔。封装材料48填充邻近的通孔32之间的间隙以及通孔32与器件管芯36之间的间隙。封装材料48可为模制化合物、模制底部填料、环氧树脂和/或树脂。分配的封装材料48的顶部表面高于金属柱42和通孔32的顶端。封装材料48可包括基础材料48A和位于基础材料48A中的填料颗粒48B，其中基础材料48A可为聚合物、树脂、环氧树脂等。填料颗粒可为诸如SiO2、Al2O3、硅土等的介电材料的颗粒，且可具有球形形状。此外，如根据一些示例，球形填料颗粒48B可具有相同或不同的直径。
在随后的步骤中，如在图9中所示，实施诸如化学机械抛光(CMP)步骤或机械研磨步骤的平坦化步骤以使封装材料48和介电层44变薄，直到通孔32和金属柱42完全暴露。通孔32和金属柱42还可轻微抛光以确保通孔32和金属柱42的暴露。由于平坦化工艺，通孔32的顶端与金属柱42的顶部表面大致齐平(共面)，并且与封装材料48的顶部表面大致共面。由于平坦化工艺，模制封装材料48的顶部处的一些填料颗粒48B被部分地抛光，使填料颗粒48中的一些的顶部部分去除，并且保留底部部分，如图9所示。因此所得的部分填料颗粒48B的顶部表面将为平坦的，该平坦顶部表面与基础材料48A的顶部表面、通孔和金属柱42共面。
图10至图13例示了正面再分布结构的形成。相应的工艺如在图25中示出的流程图中的工艺220所示。图10例示了再分布线(RDL)54的第一层和相应的介电层50的形成。根据本公开的一些实施例，介电层50首先形成在图9所示的结构上。介电层50可由诸如PBO、聚酰亚胺等的聚合物形成。形成工艺包括以可流动形式涂覆介电层50，然后使介电层50固化。根据本公开的替代实施例，介电层50由诸如氮化硅、二氧化硅等的无机介电材料形成。该形成方法可包括化学汽相沉积(CVD)、原子层沉积(ALD)、等离子体增强型化学汽相沉积(PECVD)或其他适用的沉积方法。然后，例如通过光刻工艺形成开口(被RDL54的通孔部分占据)。根据一些实施例，其中介电层50由诸如PBO或聚酰亚胺的光敏材料形成，开口的形成包含使用光刻掩膜(未示出)光致曝光介电层50以及显影介电层50。通孔32和金属柱42通过开口暴露。
接下来，RDL54形成在介电层50上方。RDL54包括形成在介电层50中以连接至金属柱42和通孔32的通孔54A、以及位于介电层50上方的金属迹线(金属线)54B。根据本公开的一些实施例，RDL54(包括54A和54B)在镀工艺中形成，镀工艺包括沉积金属晶种层(未示出)、在金属晶种层上方形成并图案化光刻胶(未示出)、以及在金属晶种层上方镀诸如铜和/或铝的金属材料。金属晶种层还可包括粘合层和含铜层，其形成方法和材料类似于金属晶种层26(图2)。然后去除图案化光刻胶，然后蚀刻金属晶种层的之前被图案化的光刻胶覆盖的部分。
根据本公开的一些实施例，在蚀刻金属晶种层之后，不实施等离子体处理和湿蚀刻工艺(参考图5和图6公开)。应当领会，将形成在介电层50上方且接触介电层50的介电层可由与介电层50相同类型的材料形成，因此其粘合剂通常足够好，并且因此无需进一步通过等离子体处理提高粗糙度。根据替代实施例，实施等离子体处理和湿蚀刻工艺以进一步提高粘合性并减少泄露。
参考图11，根据本公开的一些实施例，介电层56形成在如图10所示的结构上方，然后在介电层56中形成开口(被RDL58的通孔部分占据)。因此RDL54的一些部分通过开口暴露。介电层56可使用选自用于形成介电层50的相同候选材料的材料形成，其可包括PBO、聚酰亚胺、BCB或其他有机或无机材料。然后形成RDL58。RDL58还包括延伸到介电层56中的开口中以接触RDL54的通孔部分、以及位于介电层56正上方的金属线部分。RDL58的形成可与RDL54的形成一样，可包括形成晶种层，形成图案化掩膜，镀RDL58，然后去除图案化掩膜和晶种层的不需要部分。
图12例示了介电层60和RDL62在介电层56和RDL58上方的形成。介电层60可由选自用于形成介电层50和56的候选材料的相同组的材料形成。RDL62还可由金属或金属合金(包括铝、铜、钨或其合金)形成。应当领会，尽管在所示的示例性实施例中，形成三层RDL(54、58和62)，但是封装件可具有任何数量的RDL层，诸如一层、两层或多于三层。
图13例示了介电层64的形成。介电层64可由选自用于形成介电层50、56和60的候选材料的相同组的材料形成。例如，介电层64可使用PBO、聚酰亚胺或BCB形成。开口66形成在介电层64中以显示下面的金属焊盘，在所示实施例中其为RDL62的一部分。
图14和图15A例示了根据一些示例性实施例的凸块下金属(UBM)68(图15A)、以及电连接器70的形成。相应的工艺如在图25中示出的流程图中的工艺222所示。参考图14，形成晶种层72。晶种层72可具有与晶种层26(图2)类似的结构，并且可包括粘合层和位于粘合层上方的含铜层，其由如所讨论的用于晶种层26的类似材料形成。晶种层72延伸到开口66(图13)中以连接RDL62中的金属焊盘。
图案化光刻胶74形成在晶种层72上方，其中形成开口以显示晶种层72的一些部分。接下来，在开口中通过镀形成金属柱70(替代地称为电连接器)。金属柱70可由非焊接材料(non-solder material)(诸如铜)或焊料形成。在随后的工艺中，去除光刻胶74，暴露晶种层72的下面的部分。然后实施蚀刻工艺以蚀刻晶种层72的暴露部分。晶种层72中的粘合层的剩余部分此后称作UBM68。用于蚀刻晶种层72的蚀刻工艺和相应的化学制品可参考如图4和图5所示的蚀刻晶种层26的讨论。
接下来，如图15A所示，实施处理工艺和蚀刻工艺，这些工艺由箭头76表示。相应的工艺如在图25中示出的流程图中的工艺224所示。已经参考图5和图6讨论了处理和蚀刻工艺的细节，其可分别包括干(等离子体)处理工艺和湿蚀刻工艺，因此此处不再重复。处理和蚀刻工艺具有减小由蚀刻的晶种层72(图14)，特别是晶种层72中的粘合层剩下的不需要的金属颗粒的功能。处理还具有增大介电层64的表面粗糙度的功能。根据本公开的一些实施例，其中镀金属柱70包括焊料，实施回流，并且所得焊接区域70将为圆形的，类似于图15B-2所示。
图15B-1和图15B-2例示了根据一些实施例的形成UBM68的中间阶段，其中，替代具有形成为电连接器70的金属柱，形成焊接区域以充当电连接器70。参考图15B-1，形成UBM68。形成工艺包括形成介电层64和开口66，如图13所示，形成掩盖金属层(类似于图14中所示的金属晶种层72)以延伸到开口66中，形成掩蔽层(诸如光刻胶)以覆盖金属层的一些部分，以及蚀刻晶种层的通过掩蔽层暴露的部分。掩盖金属层的剩余部分是UBM68。根据一些实施例，掩盖金属层(以及所得的UBM68)包括镍层、钛层、钯层、金层、铜层或以上的多层。
接下来，如图15B-1所示，实施处理工艺和蚀刻工艺，这些工艺由箭头76表示。处理和蚀刻工艺的细节本质上与图15A中所示的工艺76相同。处理工艺和蚀刻工艺的细节已经分别参考图5和图6讨论，因此本文不再重复。该处理和蚀刻工艺具有减小由掩盖金属层剩余的不需要的金属颗粒以及增大介电层64的表面粗糙度的特征。
参考图15B-2，在处理工艺和蚀刻工艺之后，形成焊接区域(也表示为70)。该形成可包括将焊料球放置在UBM68上，然后使焊料球回流。
包括组合的介电层24和上覆部件的结构此后称为封装件84，其可为包括等同于图15A或图15B-2中例示的多个结构的复合材料晶元。接下来，复合材料晶元84放置在带(tape)(未示出)上，使得复合材料晶元84可通过在离型膜22上投射光(诸如激光束)且光透过透明衬底20而从衬底20拆卸。离型膜22因此被拆卸，并且复合材料晶元84从载体20释放。
参考图16，开口(被焊接区域95占据)形成在介电缓冲层24中，因此暴露通孔32。根据本公开的一些实施例，开口通过激光钻孔形成。根据本公开的替代实施例，开口通过光刻工艺中的蚀刻形成。
复合材料晶元84包括多个封装件84’(参考图16)，其可彼此等同，其中每个封装件84’包括多个通孔32和一个或多个器件管芯36。图16例示了封装件86到封装件84’的结合，因此形成叠加封装件(PoP)结构/封装件100。通过焊接区域80实施结合。根据本公开的一些实施例，封装件86包括封装件衬底88和器件管芯90，其可为存储器管芯，诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等。底部填料92还设置在封装件86与下面封装件84’之间的间隙中并且固化。由于底部填料92(还可包括作为基础材料的树脂(或环氧树脂)和位于基础材料中的填料颗粒)不同于介电层64的材料，其间的粘合剂通常不够好，因此工艺76(图15A和图15B-1)可提高粘合性。
实施分离(管芯切割)工艺以将复合材料晶元84和结合到其上的封装件86分离成彼此等同的单独的封装件84’。图16还例示了分离的封装件到封装部件94通过焊接区域95的结合。根据本公开的一些实施例，封装部件94为封装件衬底，其可为无芯衬底或具有芯的衬底(诸如玻璃纤维施加芯)。根据本公开的其他实施例，封装部件94为印刷电路板或封装件。图16中的封装件此后称为封装件102。
图17至图24例示了根据本公开的一些实施例的形成封装件的中间阶段的截面图。除非有特定说明，这些实施例中的部件的材料和形成方法本质上与图1至图16中所示的实施例中的相同参考标号表示的相同部件一样。因此，关于图17至图24中所示的部件的形成工艺和材料的细节可参考图1至图16中示出的实施例的讨论。
图17至图21例示了在器件管芯的封装之前形成包括背面RDL的封装件中的中间阶段的截面图。参考图17，离型膜22涂覆在载体20上，且介电缓冲层24形成在离型膜22上方。根据本公开的一些实施例，介电层24由聚合物形成，其可为聚酰亚胺、PBO等。
接下来，背面RDL104形成在介电层24上方。RDL104的形成可包括在介电层24上方形成金属晶种层(未示出)，在晶种层上方形成诸如光刻胶的图案化掩膜(未示出)，然后在暴露的晶种层上实施金属镀。然后去除图案化掩膜和晶种层中被图案化掩膜覆盖的部分，如图17所示留下RDL104。根据本公开的一些实施例，晶种层包括钛层和位于钛层上方的铜层。可使用例如物理汽相沉积(PVD)形成晶种层。例如可使用化学镀实施镀。
接下来，在RDL104上形成介电层106。介电层106的底部表面与RDL104和介电层24的顶部表面接触。根据本公开的一些实施例，介电层106由聚合物形成，其可为聚酰亚胺、PBO等。根据本公开的替代实施例，介电层106由非聚合物(无机)材料形成，例如可为二氧化硅、氮化硅等。然后图案化介电层106以在其中形成开口108。因此，RDL104的一些部分通过介电层106中的开口108暴露。
图18例示了金属柱的形成。工艺细节和材料类似于参考图2至图5示出和讨论的内容，因此此处不再重复。所得金属柱32通过介电层106中的通孔110连接至下面的RLD104，并且与金属柱32同时形成。此外，金属晶种层26(包括粘合层26A和含铜层26B)包括金属柱32中的一些部分和通孔110中的一些其他部分。
图19例示了多个工艺，其可包括第一处理31、处理31之后的蚀刻工艺33、以及蚀刻工艺33之后的第二工艺35。第一处理、蚀刻工艺和第二处理的处理细节可分别参考图5、图6和图7所讨论，此处不再重复。相应地，可去除不利的金属颗粒，增大介电层106的表面粗糙度。
图20例示了在形成包括介电层50、56、60和64、RDL54和58、UBM68和电连接器70的上覆结构之后的结构。还可实施等离子体处理和蚀刻工艺76。等离子体处理和蚀刻工艺的细节可分别参考图5和图6的讨论。应当领会，图15B-1和图15B-2中所示的工艺也可应用。图21例示了实施以形成封装件102的随后步骤。
图22至图25例示了根据本公开的一些实施例形成封装件的中间阶段。这些实施例类似于图1至图16中示出的实施例，除了没有形成通孔。参考图22，形成DAF34，然后将器件管芯36附接至DAF34。DAF34不是每个在相应的上覆器件管芯36的下面的离散DAF，而是在整个载体20上方扩展的大型DAF。根据本公开的一些实施例，如图5至图7所示的第一处理、蚀刻和第二处理根据一些实施例未实施。
图23例示了器件管芯36的封装和上覆介电层50、56、60和64、RDL54、58和62、UBM68和电连接器70的形成。此外，可实施处理76，其包括等离子体处理和蚀刻处理。等离子体处理和蚀刻处理的细节可分别参考图5和图6的讨论。应当领会，图15B-1和图15B-2的处理也可应用。图24例示了实施以形成封装件102的随后步骤。
在以上例示的示例性实施例中，根据本公开的一些实施例讨论了一些示例性工艺和特征。也可包括其他特征和工艺。例如，可包括测试结构以协助三维(3D)封装或3DIC器件的验证测试。测试结构可包括例如形成在再分布层中或衬底上允许测试3D封装或3DIC、使用探针和/或探针板等的测试焊盘。可在中间结构以及最终结构上实施验证测试。此外，本文公开的结构和方法可与测试方法论结合使用，测试方法论包含已知良好管芯的中间验证以提高产量并降低成本。
本公开的实施例具有一些有利特征。在晶元上实施的实验指示通过等离子体处理和蚀刻工艺，由粘合层剩下的金属残渣显著减少。例如，第一样品晶元形成为具有在介电缓冲层上的金属柱，类似于图5所示结构。在等离子体处理和蚀刻工艺之前，金属颗粒(残渣)占据介电缓冲层约7.1％的表面面积。在等离子体处理和蚀刻工艺之后，金属颗粒占据介电缓冲层小于0.1％的表面面积。
第二样品晶元也形成为在介电层上形成UBM和金属柱，类似于图15A中所示的结构。在等离子体处理和蚀刻工艺之前，金属颗粒(残渣)占据介电缓冲层约11.2％的表面面积。在等离子体处理和蚀刻工艺之后，金属颗粒占据介电缓冲层约0.3％的表面面积。金属残渣的显著减少有助于减小泄露电流并提高粘合性。此外，等离子体处理导致表面介电层的表面粗糙度增大，因此提高粘合性。
根据本公开的一些实施例，一种方法包括在第一介电层上形成金属晶种层；在金属晶种层上方形成图案化掩膜，其中图案化掩膜中的开口位于第一介电层的第一部分上方，且图案化掩膜与第一介电层的第二部分重叠；镀开口中的金属区域；去除图案化掩膜以暴露金属晶种层的一些部分；蚀刻金属晶种层的暴露部分；在第一介电层的第二部分的表面上实施第一等离子体处理；以及在第一介电层的第二部分的表面上实施蚀刻工艺。在实施例中，方法进一步包括在第一介电层的第二部分上放置器件管芯；以及将金属区域和器件管芯封装在封装材料中。在实施例中，方法进一步包括：在蚀刻工艺之后，对金属区域实施第二等离子体处理。在实施例中，使用与第一等离子体处理相同的工艺气体实施第二等离子体处理。在实施例中，通过比第一等离子体处理更低的偏置电压实施第二等离子体处理。在实施例中，使用相同的湿蚀刻化学制品实施蚀刻工艺和蚀刻金属晶种层的暴露部分。在实施例中，该方法进一步包括将焊接区域与金属区域接合；以及分配底部填料以封装焊接区域。在实施例中，在接合焊接区域之后实施第一等离子体处理和蚀刻工艺。在实施例中，该方法进一步包括形成第二介电层；在第二介电层上方形成再分布线；形成第一介电层；在第一介电层中形成开口；以及在第一介电层中形成通孔，其中，通孔和金属区域同时形成。
根据本公开的一些实施例，一种方法包括在介电层上方形成金属区域；在第一等离子体处理期间施加偏置电压实施第一等离子体处理以轰击介电层；实施湿蚀刻，其中介电层的表面暴露至用于湿蚀刻的化学制品；以及将金属区域封装到封装材料中，其中，介电层的表面与封装材料接触。在实施例中，该方法进一步包括实施第二等离子体处理以氧化金属区域的表面层。在实施例中，使用包括氧气(O2)的工艺气体实施第一处理和第二等离子体处理。在实施例中，使用不包括氧气(O2)的工艺气体实施第一等离子体处理，使用包括氧气(O2)的工艺气体实施第二等离子体处理。在实施例中，形成金属区域包括：形成具有接触介电层的底部部分的金属晶种层；以及在金属晶种层上镀金属区域，其中使用配置成蚀刻金属晶种层的底部部分的化学制品实施湿蚀刻。在实施例中，金属晶种层进一步包括顶部部分，且化学制品配置成不蚀刻金属晶种层的顶部部分。
根据本公开的一些实施例，一种方法包括形成高于介电层突出的金属柱；轰击介电层的表面层；实施蚀刻工艺以去除介电层的表面层上的金属颗粒；以及对金属柱实施等离子体处理。在实施例中，方法进一步包括在介电层上沉积金属晶种层，其中金属柱形成在金属晶种层上；以及蚀刻金属晶种层，其中金属颗粒为金属晶种层的残留颗粒。在实施例中，金属晶种层包括钛，且使用配置成蚀刻钛的化学溶液实施蚀刻工艺。在实施例中，使用包括氩气或氮气的工艺气体实施轰击介电层的表面层。在实施例中，工艺气体进一步包括氧气(O2)。
根据本发明的一个方面，提供一种形成半导体器件的方法，包括：在第一介电层上形成金属晶种层；在金属晶种层上方形成图案化掩模，其中图案化掩模中的开口位于第一介电层的第一部分上方，且图案化掩模与第一介电层的第二部分重叠；在开口中镀金属区域；去除图案化掩模以暴露金属晶种层的一些部分；蚀刻金属晶种层的暴露部分；对第一介电层的第二部分的表面实施第一等离子体处理；以及对第一介电层的第二部分的表面实施蚀刻工艺。
根据本发明的一个实施例，方法进一步包括：在第一介电层的第二部分上放置器件管芯；以及将金属区域和器件管芯封装在封装材料中。
根据本发明的一个实施例，方法进一步包括：在蚀刻工艺之后，对金属区域实施第二等离子体处理。
根据本发明的一个实施例，使用与第一等离子体处理相同的工艺气体实施第二等离子体处理。
根据本发明的一个实施例，通过比第一等离子体处理更低的偏置电压实施第二等离子体处理。
根据本发明的一个实施例，使用相同的湿蚀刻化学制品实施蚀刻工艺以及蚀刻金属晶种层的暴露部分。
根据本发明的一个实施例，方法进一步包括：将焊接区域与金属区域接合；以及分配底部填料以封装焊接区域。
根据本发明的一个实施例，在接合焊接区域之后实施第一等离子体处理和蚀刻工艺。
根据本发明的一个实施例，方法进一步包括：形成第二介电层；在第二介电层上方形成再分布线；形成第一介电层；在第一介电层中形成开口；以及在第一介电层中形成通孔，其中通孔和金属区域同时形成。
根据本发明的另一方面，提供一种形成半导体器件的方法，包括：在介电层上方形成金属区域；实施第一等离子体处理以轰击介电层，其中在第一等离子体处理期间施加偏置电压；实施湿蚀刻，其中介电层的表面暴露至用于湿蚀刻的化学制品；以及将金属区域封装在封装材料中，其中，介电层的表面与封装材料接触。
根据本发明的一个实施例，方法进一步包括：实施第二等离子体处理以氧化金属区域的表面层。
根据本发明的一个实施例，使用包括氧气(O2)的工艺气体实施第一处理和第二等离子体处理。
根据本发明的一个实施例，使用不含氧气(O2)的第一工艺气体实施第一等离子体处理，使用包含氧气(O2)的工艺气体实施第二等离子体处理。
根据本发明的一个实施例，形成金属区域包括：形成具有接触介电层的底部部分的金属晶种层；以及在金属晶种层上镀金属区域，其中使用配置成蚀刻金属晶种层的底部部分的化学制品实施湿蚀刻。
根据本发明的一个实施例，金属晶种层进一步包括顶部部分，且化学制品配置成不蚀刻金属晶种层的顶部部分。
根据本发明的另一方面，提供一种形成半导体器件的方法，包括：形成高于介电层突出的金属柱；轰击介电层的表面层；实施蚀刻工艺以去除介电层的表面层上的金属颗粒；以及对金属柱实施等离子体处理。
根据本发明的一个实施例，方法进一步包括：在介电层上沉积金属晶种层，其中金属柱形成在金属晶种层上；以及蚀刻金属晶种层，其中金属颗粒为金属晶种层的残留颗粒。
根据本发明的一个实施例，金属晶种层包括钛，且使用配置成蚀刻钛的化学溶液实施蚀刻工艺。
根据本发明的一个实施例，使用包括氩气或氮气的工艺气体实施介电层的表面层的轰击。
根据本发明的一个实施例，工艺气体进一步包括氧气(O2)。
以上概括了若干实施例的特征以使本领域中的技术人员更好地理解本公开的一些方面。本领域中的技术人员应领会，其可容易地使用本公开作为设计或修改用于执行相同目的和/或实现本文介绍的实施例的相同优势的其他工艺和结构的基础。本领域中的技术人员还应意识到，这种等同构造不背离本公开的精神和范围，且它们在本文中可进行各种改变、替换和更改而不背离本公开的精神和范围。

Claims (10)

1.一种形成半导体器件的方法，包括：
在第一介电层上形成金属晶种层；
在所述金属晶种层上方形成图案化掩模，其中所述图案化掩模中的开口位于所述第一介电层的第一部分上方，且所述图案化掩模与所述第一介电层的第二部分重叠；
在所述开口中镀金属区域；
去除所述图案化掩模以暴露所述金属晶种层的一些部分；
蚀刻所述金属晶种层的所述暴露部分；
对所述第一介电层的所述第二部分的表面实施第一等离子体处理；以及
对所述第一介电层的所述第二部分的所述表面实施蚀刻工艺。
2.根据权利要求1所述的方法，进一步包括：
在所述第一介电层的所述第二部分上放置器件管芯；以及
将所述金属区域和所述器件管芯封装在封装材料中。
3.根据权利要求2所述的方法，进一步包括：
在所述蚀刻工艺之后，对所述金属区域实施第二等离子体处理。
4.根据权利要求3所述的方法，其中，使用与所述第一等离子体处理相同的工艺气体实施所述第二等离子体处理。
5.根据权利要求3所述的方法，其中，通过比所述第一等离子体处理更低的偏置电压实施所述第二等离子体处理。
6.根据权利要求1所述的方法，其中，使用相同的湿蚀刻化学制品实施所述蚀刻工艺以及蚀刻所述金属晶种层的所述暴露部分。
7.根据权利要求1所述的方法，进一步包括：
将焊接区域与所述金属区域接合；以及
分配底部填料以封装所述焊接区域。
8.根据权利要求7所述的方法，其中，在接合所述焊接区域之后实施所述第一等离子体处理和所述蚀刻工艺。
9.一种形成半导体器件的方法，包括：
在介电层上方形成金属区域；
实施第一等离子体处理以轰击所述介电层，其中在所述第一等离子体处理期间施加偏置电压；
实施湿蚀刻，其中所述介电层的表面暴露至用于所述湿蚀刻的化学制品；以及
将所述金属区域封装在封装材料中，其中，所述介电层的所述表面与所述封装材料接触。
10.一种形成半导体器件的方法，包括：
形成高于介电层突出的金属柱；
轰击所述介电层的表面层；
实施蚀刻工艺以去除所述介电层的所述表面层上的金属颗粒；以及
对所述金属柱实施等离子体处理。
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