TWI710080B - 疊層封裝結構及製造封裝體的方法 - Google Patents

疊層封裝結構及製造封裝體的方法 Download PDF

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TWI710080B
TWI710080B TW107135146A TW107135146A TWI710080B TW I710080 B TWI710080 B TW I710080B TW 107135146 A TW107135146 A TW 107135146A TW 107135146 A TW107135146 A TW 107135146A TW I710080 B TWI710080 B TW I710080B
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layer
die
package
conductive
amorphous
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TW107135146A
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TW202002204A (zh
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鄭禮輝
高金福
簡智源
盧思維
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台灣積體電路製造股份有限公司
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Abstract

一種疊層封裝(package-on-package；PoP)結構包括第 一封裝及堆疊在所述第一封裝上的第二封裝。所述第一封裝包括晶粒、多個導電結構、包封體及重佈線結構。所述晶粒具有主動表面及與所述主動表面相對的後表面。所述晶粒包括位於後表面上的非晶層。所述導電結構環繞所述晶粒。所述包封體包封所述晶粒及所述導電結構。所述重佈線結構位於所述晶粒的主動表面上且與所述導電結構及所述晶粒電性連接。

Description

疊層封裝結構及製造封裝體的方法
本發明實施例是有關於一種疊層封裝結構，且特別是有關於一種在晶粒中包括非晶層的疊層封裝結構。
由於各種電子元件(例如，電晶體、二極體、電阻器、電容器等)的積體密度的持續提高，半導體行業已經歷快速增長。在很大程度上，積體密度的此種提高來自於最小特徵大小(minimum feature size)的重複減小，此使得更多較小的元件能夠集成到給定區域中。這些較小的電子元件也需要與先前的封裝相比利用較小區域的較小的封裝。當前，積體扇出型封裝因其緊湊性而正變得日漸流行。如何確保積體扇出型封裝的可靠性已成為此領域中的挑戰。
一種疊層封裝結構包括第一封裝及堆疊在所述第一封裝上的第二封裝。所述第一封裝具有晶粒、多個導電結構、包封體 及重佈線結構。所述晶粒具有主動表面及與所述主動表面相對的後表面。所述晶粒包括位於後表面上的非晶層。所述導電結構環繞所述晶粒。所述包封體包封所述晶粒及所述導電結構。所述重佈線結構位於所述晶粒的主動表面上且與所述導電結構及所述晶粒電性連接。
10、20:封裝
10a:封裝陣列
100、100’:導電結構
110a:晶種材料層
110b:晶種層
112a、112b:第一子層
114a、114b:第二子層
120’:導電材料
120a:導電圖案
200:晶粒
100a’、200a、300a、300a’:頂表面
100b、200b、300b:後表面
200c:主動表面
202:半導體基板
204:導電接墊
206:鈍化層
208:導通孔
210、210a:保護層
212:非晶層
300:包封體
300’:包封材料
400:重佈線結構
400a:層間介電層
400b:重佈線導電圖案
500:導電端子
600:連接端子
700:底部填充膠
1000:疊層封裝結構
AD:黏合層
C:載板
IDB:剝離層
IDE:乾式蝕刻製程
M:罩幕
OP:開口
R1、R2:凹槽
T200、T212:厚度
TP:膠帶
WE:濕式蝕刻製程
圖1A到圖1R是根據本公開一些實施例的疊層封裝(package-on-package；PoP)結構的製造流程的示意性剖面圖。
圖2A是根據本公開一些替代性實施例的疊層封裝結構的製造流程的中間階段的示意性剖面圖。
圖2B是根據本公開一些替代性實施例的疊層封裝結構的製造流程的中間階段的示意性剖面圖。
圖3A到圖3D是根據本公開一些替代性實施例的疊層封裝結構的製造流程的混合蝕刻製程(hybrid etching process)的示意性剖面圖。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例而非旨在進行限制。舉例來說，在 以下說明中，在第二特徵之上或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外，本公開在各種實例中可重複使用參考編號和/或字母。此種重複使用是為了簡明及清晰起見，且自身並不表示所論述的各個實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。除附圖中所繪示的取向以外，所述空間相對性用語旨在涵蓋裝置在使用或操作中的不同取向。設備可被另外取向(旋轉90度或處於其他取向)，且本文所使用的空間相對性描述語可同樣相應地作出解釋。
本公開也可包括其他特徵及製程。舉例來說，可包括測試結構，以說明對三維(three-dimensional；3D)封裝或三維積體電路(three-dimensional integrated circuit；3DIC)裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基板上形成的測試接墊，以使得能夠對三維封裝或三維積體電路進行測試、對探針和/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包括對已知良好晶粒(known good die)進行中間驗證的測試方法 來使用，以提高良率並降低成本。
圖1A到圖1R是根據本公開一些實施例的疊層封裝(PoP)結構1000的製造流程的示意性剖面圖。參照圖1A，提供上面形成有剝離層DB的載板C。在一些實施例中，剝離層DB形成在載板C的頂表面上。載板C為例如玻璃基板。另一方面，在一些實施例中，剝離層DB可為形成在所述玻璃基板上的光熱轉換(light-to-heat conversion；LTHC)釋放層。在一些替代性實施例中，剝離層可由膠(glue)或聚合物系材料(polymer-based material)製成。然而，以上列出的載板C及剝離層DB的材料僅用於示例性說明，且本公開並非僅限於此。在一些替代性實施例中，其他材料可適合作為載板C，只要所述材料能夠在承載/支撐隨後形成的元件的同時經受隨後的製程即可。類似地，其他材料可適合作為剝離層DB，只要所述材料能夠在後續製程中執行釋放功能即可。
參照圖1B，在剝離層DB上形成晶種材料層110a。在一些實施例中，晶種材料層110a可為由不同的材料所形成的複合層。舉例來說，晶種材料層110a可包括第一子層112a及第二子層114a。在一些實施例中，第二子層114a形成在第一子層112a上。舉例來說，第一子層112a夾置在剝離層DB與第二子層114a之間。在一些實施例中，第一子層112a的材料可包括鈦、氮化鈦、鉭、氮化鉭、其他合適的材料或其組合。另一方面，第二子層114a的材料可包括例如銅、銅合金或其他合適的材料選擇。在一些實 施例中，第一子層112a及第二子層114a是通過物理氣相沉積或其他合適的方法來形成。第一子層112a可具有大約0.01μm到大約1μm的厚度。另一方面，第二子層114a的厚度也可介於約0.01μm到約1μm之間。
參照圖1C，在晶種材料層110a上形成罩幕M。對罩幕M進行圖案化以形成多個開口OP。在一些實施例中，開口OP暴露出隨後形成的導電結構100’(示於圖1F中)的預期位置。在一些實施例中，罩幕M的開口OP暴露出晶種材料層110a的一部分。舉例來說，罩幕M暴露出第二子層114a的一部分。在一些實施例中，罩幕M可由感光性材料來形成。舉例來說，罩幕M可為光阻或乾膜(dry film)。
參照圖1D，將導電材料120’填充到罩幕M的開口OP中。在一些實施例中，導電材料120’形成在晶種材料110a的第二子層114a的被罩幕M的開口OP暴露出的部分上。在一些實施例中，可通過鍍覆製程來形成導電材料120’。鍍覆製程例如為電鍍、無電鍍覆、浸鍍等。導電材料120’例如為銅、銅合金等。換句話說，晶種材料層110a的第二子層114a及導電材料120’可由同一種材料製成。然而，本公開並非僅限於此。在一些替代性實施例中，第二子層114a與導電材料120’可包含不同的材料。
參照圖1D及圖1E，隨後移除罩幕M以得到位於晶種材料層110a上的多個導電圖案120a。在一些實施例中，可通過剝除製程、蝕刻製程及/或清潔製程來移除罩幕M。由於導電圖案120a 是通過將導電材料120’填充到罩幕M的開口OP中所形成，因此導電圖案120a可具有與罩幕M的開口OP相同的輪廓。
參照圖1E及圖1F，對晶種材料層110a進行圖案化以形成晶種層110b。如圖1F所示，晶種層110b可由與導電圖案120a對應的多個晶種層圖案構成。以下將闡述晶種材料層110a的圖案化。
在一些實施例中，通過第一蝕刻製程選擇性地移除第二子層114a被導電圖案120a暴露出的部分。在一些實施例中，第一蝕刻製程可包括例如乾式蝕刻等非等向性蝕刻製程或例如濕式蝕刻等等向性蝕刻製程。在一些實施例中，氬氣(Ar)氣體、氮氣(N2)氣體、氧氣(O2)氣體、四氟甲烷(tetrafluoromethane；CF4)氣體或其組合可作為乾式蝕刻的蝕刻劑。在一些替代性實施例中，氟化氫(hydrogen fluoride；HF)溶液、磷酸(phosphoric acid；H3PO4)溶液、過氧化氫(hydrogen peroxide；H2O2)溶液、氫氧化銨(ammonium hydroxide；NH4OH)溶液或其組合可作為濕式蝕刻的蝕刻劑。第一蝕刻製程移除第二子層114a的部分以形成第二子層114b。應注意的是，以上所列出的蝕刻劑僅用於示例性說明，且其他類型的蝕刻劑也可作為對第二子層114a進行蝕刻的蝕刻劑。
在移除第二子層114a的部分之後，第一子層112a的部分會被導電圖案120a及剩餘的第二子層114b暴露出。可通過第二蝕刻製程來移除第一子層112a被暴露的部分。在一些實施例中， 可通過乾式蝕刻製程或濕式蝕刻製程對第一子層112a進行蝕刻以得到第一子層112b。用於移除第一子層112a的蝕刻劑可包括氟系氣體，例如四氟甲烷(CF4)氣體、三氟甲烷(fluoroform；CHF3)氣體、其他合適的氣體或其組合。在一些替代性實施例中，用於移除第一子層112a的蝕刻劑可包括氟化氫(HF)溶液或其他合適的蝕刻溶液。應注意的是，以上所列出的蝕刻劑僅用於示例性說明，且其他類型的蝕刻劑也可作為對第一子層112a進行蝕刻的蝕刻劑。
在一些實施例中，可將導電圖案120a及晶種層110b(包括第一子層112b及第二子層114b)統稱為導電結構100’。換句話說，如圖1F所示，導電結構100’形成在剝離層DB上。在一些實施例中，每一導電結構100’包括貼合到剝離層DB的晶種層110b。舉例來說，導電結構100’的晶種層110b直接接觸剝離層DB。
參照圖1G，將多個晶粒200放置在剝離層DB上。在一些實施例中，晶粒200位於導電結構100’之間。舉例來說，晶粒200排列成陣列且被導電結構100’環繞。在一些實施例中，每一晶粒200具有頂表面200a及與頂表面200a相對的後表面200b。如圖1G所示，晶粒200被放置成頂表面200a朝上而後表面200b面對剝離層DB。在一些實施例中，通過拾取及放置製程(pick-and-place process)將晶粒200放置在剝離層DB上。在一些實施例中，每一晶粒200可為記憶體晶粒(即，動態隨機存取記憶體(dynamic random access memory；DRAM)、靜態隨機存取 記憶體(static random access memory；SRAM)、非揮發性隨機存取記憶體(nonvolatile random access memory；NVRAM)及/或類似晶粒)、邏輯晶粒、射頻(radio frequency；RF)晶粒或處理器晶粒(即，加速處理器(accelerated processor；AP)等)。以下將闡述每一晶粒200的樣態。
在一些實施例中，每一晶粒200包括半導體基板202、多個導電接墊204、鈍化層206、多個導通孔208、保護層210及非晶層212。在一些實施例中，半導體基板202可為矽基板。在一些替代性實施例中，半導體基板202可由下列製成：合適的元素半導體，例如金剛石或鍺；合適的化合物半導體，例如砷化鎵、碳化矽、砷化銦或磷化銦；或者合適的合金半導體，例如碳化矽鍺(silicon germanium carbide)、磷化鎵砷(gallium arsenic phosphide)或磷化鎵銦(gallium indium phosphide)。在一些實施例中，半導體基板202包括形成在半導體基板202中的主動元件(例如，電晶體等)及被動元件(例如，電阻器、電容器、電感器等)。
在一些實施例中，導電接墊204分佈在半導體基板202上。導電接墊204可為鋁接墊、銅接墊或其他合適的金屬接墊。鈍化層206形成在半導體基板202上且具有局部地暴露出導電接墊204的接觸開口。鈍化層206可為氧化矽層、氮化矽層、氮氧化矽層或由其他合適的介電材料形成的介電層。在一些實施例中，可在鈍化層206上進一步形成後鈍化層(未繪示)。另外，導 通孔208形成在導電接墊204上。在一些實施例中，導通孔208被鍍覆在導電接墊204上以使得導通孔208與導電接墊204電性連接。導通孔208可為銅通孔或其他合適的金屬通孔。保護層210形成在鈍化層206上以覆蓋導通孔208。在一些實施例中，保護層210可為聚苯并噁唑(polybenzoxazole；PBO)層、聚醯亞胺(polyimide；PI)層或由其他合適的聚合物製成的層。在一些替代性實施例中，保護層210可由無機材料製成。
在一些實施例中，在將晶粒200放置在剝離層DB上之前，對每一晶粒200執行薄化製程。舉例來說，可對每一晶粒200的後表面200b執行背側研磨製程以減小晶粒200的總厚度。在薄化製程期間，部分半導體基板202會被研磨。在研磨製程期間產生的應力會破壞半導體基板202位於經研磨表面上的部分的晶格，從而在晶粒200的後表面200b上形成非晶層212。如圖1G所示，非晶層212位於半導體基板202上且與半導體接墊204相對。在一些實施例中，非晶層212直接接觸半導體基板202且覆蓋半導體基板202。在一些實施例中，當半導體基板202為矽基板時，非晶層212可為非晶矽層。另一方面，當半導體基板202包括其他類型的半導體時，非晶層212可為其他類型的非晶半導體層。在一些實施例中，非晶層212的厚度T212介於約1nm與約300nm之間。另一方面，晶粒200的厚度T200介於約40μm與約250μm之間。在一些實施例中，非晶層212的厚度T212對晶粒200的厚度T200的比率介於約1：133.3與約1：250000之間。
在一些實施例中，晶粒200通過黏合層AD黏附到剝離層DB。在一些實施例中，位於晶粒200的後表面200b上的非晶層212貼合到黏合層AD。舉例來說，非晶層212可直接接觸黏合層AD而使得黏合層AD夾置在非晶層212與剝離層DB之間。在一些實施例中，黏合層AD可包括晶粒貼合膜(die attach film；DAF)。然而，本公開並非僅限於此。在一些替代性實施例中，其他材料可作為黏合層AD，只要所述材料能夠加強晶粒20與剝離層DB之間的黏附性即可。
參照圖1H，在剝離層DB上形成包封材料300’以包封導電結構100’及晶粒200。在一些實施例中，包封材料300’是模塑化合物、模塑底部填充膠(molding underfill)、樹脂(例如環氧樹脂)等。可通過模塑製程(例如壓縮模塑製程(compression molding process))來形成包封材料300’。在一些實施例中，包封材料300’的頂表面300a’位於比晶粒200的頂表面200a及導電結構100’的頂表面100a’高的水平高度處。換句話說，導電結構100’及每一晶粒200的保護層210不會被顯露出而是被包封材料300’很好地保護住。
參照圖1H及圖1I，研磨包封材料300’及晶粒200的保護層210，直到暴露出導電結構100’的頂表面100a’以及晶粒200的導通孔208的頂表面為止。在對包封材料300’進行研磨之後，包封體300形成在剝離層DB上以包封導電結構100’及晶粒200。包封體300暴露出每一晶粒200的至少部分以及每一導電結構 100’的至少部分。在一些實施例中，通過機械研磨、化學機械拋光(chemical mechanical polishing；CMP)或其他合適的機制來研磨包封材料300’。在研磨製程期間，保護層210的部分也受到研磨以顯露出導通孔208，由此形成保護層210a。在一些實施例中，在包封材料300’及保護層210的研磨製程期間，導電結構100’的部分及/或導通孔208的部分也可受到輕微地研磨。在研磨之後，每一晶粒200具有與後表面200b相對的主動表面200c。導通孔208被暴露出的部分位於晶粒200的主動表面200c上。應注意的是，導電結構100’的頂表面100a’、包封體300的頂表面300a及晶粒200的主動表面200c實質上彼此共面。
參照圖1J，在導電結構100’、晶粒200及包封體300上形成重佈線結構400。在一些實施例中，重佈線結構400形成在導電結構100’的頂表面100a’、晶粒200的主動表面200c及包封體300的頂表面300a上，以與導電結構100’及晶粒200電性連接。如圖1J所示，重佈線結構400包括交替堆疊的多個層間介電層400a與多個重佈線導電圖案400b。重佈線導電圖案400b與嵌置在包封體300中的晶粒200的導通孔208以及導電結構100’電性連接。在一些實施例中，最底的層間介電層400a局部地覆蓋導通孔208的頂表面及導電結構100’的頂表面100a’以形成多個接觸開口。最底的重佈線導電圖案400b延伸到最底的層間介電層400的接觸開口中以物理接觸(physical contact)導通孔208的頂表面及導電結構100’的頂表面100a’。如圖1J所示，最頂的重佈線導電 圖案400b包括多個接墊。在一些實施例中，上述接墊可包括多個球下金屬(under-ball metallurgy；UBM)圖案以用於球安裝。在一些替代性實施例中，上述接墊還可包括用於安裝被動元件的多個連接墊。
在一些實施例中，重佈線導電圖案400b的材料包括鋁、鈦、銅、鎳、鎢及/或其合金。可通過例如電鍍、沉積及/或微影以及蝕刻來形成重佈線導電圖案400b。在一些實施例中，層間介電層400a的材料包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯(benzocyclobutene；BCB)、聚苯并噁唑(PBO)或其他合適的聚合物系介電材料。可通過例如旋轉塗布(spin-on coating)、化學氣相沉積(chemical vapor deposition；CVD)、電漿增強型化學氣相沉積(plasma-enhanced chemical vapor deposition；PECVD)等合適的製作技術來形成層間介電層400a。
參照圖1K，在形成重佈線結構400之後，將多個導電端子500放置在重佈線結構400的最頂的重佈線導電圖案400b(UBM圖案)上。在一些實施例中，導電端子500包括焊料球。在一些實施例中，可通過植球製程或其他合適的製程將導電端子500放置在UBM圖案上。
參照圖1K及圖1L，在重佈線結構400上形成導電端子500之後，移除載板C。在一些實施例中，可利用紫外(UV)雷射照射剝離層DB(例如，LTHC釋放層)而使得載板C可被剝落來實現載板C的移除。在剝落製程期間，剝離層DB的一部分會 黏附在載板C上且可被載板C帶走。同時，剝離層DB的另一部分留在黏合層AD、包封體300及導電結構100’上。在移除載板C之後，將此結構上下顛倒，使得晶粒200的後表面200b朝上。將經顛倒的結構放置在膠帶TP上以供進一步處理，如圖1L所示。
在一些實施例中，移除剩餘的剝離層DB而暴露出導電結構100’以用於未來的電性連接。在一些實施例中，黏合層AD具有較差的導熱性，這將會導致在晶粒200的操作期間產生的熱量積聚在隨後形成的封裝10(示於圖1R中)內，因而會損害隨後形成的封裝10的性能及壽命。因此，在一些實施例中，可移除黏合層AD以增強隨後形成的封裝10的性能及壽命。在一些實施例中，為了進一步增強導電結構100’與隨後形成的元件之間的黏附性，可移除晶種層110b的第一子層112b以暴露出第二子層114b。在一些實施例中，可通過包括多個蝕刻步驟的混合蝕刻製程(hybrid etching process)來實現剝離層DB、黏合層AD及晶種層110b的第一子層112b的移除。舉例來說，混合蝕刻製程可包括濕式蝕刻製程及在其之前執行的乾式蝕刻製程。以下將結合圖1M到圖1P來論述混合蝕刻製程。
參照圖1M及圖1N，對圖1M所示結構執行乾式蝕刻製程DE，以移除剝離層DB及黏合層AD。在一些實施例中，乾式蝕刻製程DE的蝕刻劑不含氟化合物。舉例來說，乾式蝕刻製程DE的蝕刻劑不包含四氟甲烷(CF4)氣體。另一方面，乾式蝕刻製程DE的蝕刻劑可包含氬氣(Ar)氣體、氮氣(N2)氣體及/或 氧氣(O2)氣體。應注意的是，以上所列出的蝕刻劑僅用於示例性說明，且其他氣體也可作為乾式蝕刻製程DE的蝕刻劑，只要不包含氟化合物即可。在一些實施例中，乾式蝕刻製程DE的持續時間為10秒到300秒。如圖1N所示，乾式蝕刻製程DE不會移除位於黏合層AD下的非晶層212。即，在整個乾式蝕刻製程DE中，每一晶粒200的半導體基板202被非晶層212覆蓋。因此，非晶層212可充當阻擋層(barrier layer)以防止在乾式蝕刻製程DE期間產生的雜質損壞半導體基板202或擴散到半導體基板202中，由此確保晶粒200的可靠性。
如圖1N所示，乾式蝕刻製程DE移除黏合層AD以在包封體300中形成凹槽R1。在一些實施例中，凹槽R1暴露出每一晶粒200的非晶層212。由於非晶層212位於凹槽R1中，因此非晶層212的表面(即，晶粒200的後表面200b)位於與包封體300的後表面300b不同的水平高度處。舉例來說，非晶層212的表面可位於比包封體300的後表面300b低的水平高度處。即，包封體300的厚度可大於晶粒200的厚度。
參照圖1O及圖1P，在乾式蝕刻製程DE之後，對圖1O所示結構執行濕式蝕刻製程WE以移除晶種層110b的一部分。舉例來說，可通過濕式蝕刻製程WE來移除晶種層110b的第一子層112b。在一些實施例中，濕式蝕刻製程WE的蝕刻劑包括氟化氫(HF)溶液、磷酸(H3PO4)溶液、過氧化氫(H2O2)溶液、氫氧化銨(NH4OH)溶液或其組合。應注意的是，以上所列出的蝕 刻劑僅用於示例性說明，且其他溶液也可作為濕式蝕刻製程WE的蝕刻劑。如圖1P所示，濕式蝕刻製程WE不會移除被暴露的非晶層212。即，在整個濕式蝕刻製程WE中，每一晶粒200的半導體基板202被非晶層212覆蓋。因此，非晶層212可充當阻擋層以防止在濕式蝕刻製程WE期間產生的金屬雜質(例如，晶種層110a中的銅或鈦)破壞半導體基板202或擴散到半導體基板202中。因此，可消除銅化合物擴散到半導體基板202中的鰭式銅問題(copper-in-fin issue)，且可確保晶粒200的可靠性。
如圖1P所示，在執行混合蝕刻製程之後得到封裝陣列10a。在一些實施例中，在混合蝕刻製程之後，非晶層212仍保留在每一晶粒200的後表面200b上以覆蓋半導體基板202。如圖1P所示，濕式蝕刻製程WE移除晶種層110a的第一子層112b以在包封體300中形成凹槽R2。在一些實施例中，凹槽R2暴露出晶種層110b的第二子層114b。在一些實施例中，晶種層110b的第二子層114b與導電圖案120a構成多個導電結構100。由於晶種層110b的第二子層114b位於凹槽R2中，因此導電結構100的後表面100b位於與包封體300的後表面300b不同的水平高度處。舉例而言，導電結構100的後表面100b可位於比包封體300的後表面300b低的水平高度處。應注意的是，儘管導電結構100的後表面100b、晶粒200的後表面200b及包封體300的後表面300b被繪示為位於不同的水平高度處，然而本公開並非僅限於此。在一些替代性實施例中，在混合蝕刻製程期間，可移除包封體300的 一部分從而呈現出不同的樣態。以下將結合圖2A及圖2B來論述不同的樣態。
圖2A是根據本公開一些替代性實施例的疊層封裝結構1000的製造流程的中間階段的示意性剖面圖。參照圖2A，在乾式蝕刻製程DE及/或濕式蝕刻製程WE期間，可對包封體300的一部分進行蝕刻。因此，導電結構100的後表面100b及/或晶粒200的後表面200b可與包封體300的後表面300b實質上共面。即，包封體300的厚度可實質上等於晶粒200的厚度。
圖2B是根據本公開一些替代性實施例的疊層封裝結構1000的製造流程的中間階段的示意性剖面圖。參照圖2B，在乾式蝕刻製程DE及/或濕式蝕刻製程WE期間，可對包封體300的一部分進行蝕刻。因此，包封體300的後表面300b可位於與晶粒200的後表面200b及導電結構100的後表面100b不同的水平高度處。舉例來說，包封體300的後表面300b可位於比晶粒200的後表面200b及導電結構100的後表面100b低的水平高度處。即，包封體300的厚度可小於晶粒200的厚度。
應注意的是，圖1M到圖1P所示步驟僅為混合蝕刻製程的示例性說明，且本公開並非僅限於此。在一些替代性實施例中，混合蝕刻製程可包括不同的步驟。以下將結合圖3A到圖3D來論述移除剝離層DB、黏合層AD及晶種層110b的第一子層112b的另一示例性混合蝕刻製程。
圖3A到圖3D是根據本公開一些替代性實施例的疊層封 裝結構1000的製造流程的混合蝕刻製程的示意性剖面圖。參照圖3A及圖3B，對圖3A所示結構執行乾式蝕刻製程DE，以移除剝離層DB以及晶種層110b的一部分。舉例來說，可通過乾式蝕刻製程DE來移除剝離層DB以及晶種層110b的第一子層112b。在一些實施例中，乾式蝕刻製程DE的蝕刻劑包含四氟甲烷(CF4)氣體。在一些實施例中，乾式蝕刻製程DE的蝕刻劑還可進一步包含氬氣(Af)氣體、氮氣(N2)氣體及/或氧氣(O2)氣體。應注意的是，以上所列出的蝕刻劑僅用於示例性說明，且其他氣體也可作為乾式蝕刻製程DE的蝕刻劑。在一些實施例中，乾式蝕刻製程DE的持續時間為10秒到180秒。通過將乾式蝕刻製程DE的持續時間控制在上述範圍內，可充分移除剝離層DB以及晶種層110b的第一子層112b而不會完全移除黏合層AD。換句話說，在整個乾式蝕刻製程DE中，每一晶粒200的半導體基板202以及非晶層212被黏合層AD覆蓋。因此，黏合層AD及非晶層212可充當阻擋層以防止在乾式蝕刻製程DE期間產生的金屬雜質(例如，晶種層110a中的銅或鈦)重新沉積或擴散到半導體基板202中。因此，可消除銅化合物擴散到半導體基板202中的鰭式銅問題，且可確保晶粒200的可靠性。
參照圖3C及圖3D，在乾式蝕刻製程DE之後，對圖3C所示結構執行濕式蝕刻製程WE，以移除黏合層AD。在一些實施例中，濕式蝕刻製程WE的蝕刻劑包括氟化氫(HF)溶液、磷酸(H3PO4)溶液、過氧化氫(H2O2)溶液、氫氧化銨(NH4OH)溶 液或其組合。應注意的是，以上所列出的蝕刻劑僅用於示例性說明，且其他溶液也可作為濕式蝕刻製程WE的蝕刻劑。如圖3D所示，在濕式蝕刻製程WE之後，非晶層212保留在晶粒200的後表面200b上。即，在整個濕式蝕刻製程WE中，每一晶粒200的半導體基板202被非晶層212覆蓋。因此，非晶層212可充當阻擋層以防止在濕式蝕刻製程WE期間產生的雜質損壞半導體基板202或擴散到半導體基板202中，由此確保晶粒200的可靠性。
返回參照圖1Q，在執行混合蝕刻製程之後，在封裝陣列10a上堆疊多個封裝20。在一些實施例中，封裝陣列10a具有雙側端子設計以容置封裝20。封裝20例如為積體電路(integrated circuit；IC)封裝。封裝20通過夾置在封裝20與封裝陣列10a之間的多個連接端子600與封裝陣列10a電性連接。在一些實施例中，連接端子600為通過植球製程及/或回焊製程而形成的焊料接頭(solder joint)。應注意的是，圖1Q僅充當示例性說明，且本公開並非僅限於此。在一些替代性實施例中，可在封裝陣列10a上堆疊例如積體扇出型(integrated fan-out；InFO)封裝、記憶體裝置、球柵陣列封裝(ball grid array；BGA)或晶圓(wafer)等其他電子裝置來取代封裝20。
參照圖1R，對封裝陣列10a進行切割或單體化，以形成上面堆疊有封裝20的多個封裝10。在一些實施例中，切割製程或單體化製程通常涉及利用旋轉刀片或雷射光束進行切割。換句話說，切割或單體化製程為例如雷射切割製程、機械切割製程或其 他合適的製程。在一些實施例中，可將封裝10稱為積體扇出型封裝。在一些實施例中，形成底部填充膠700以包封連接端子600。在一些實施例中，底部填充膠700的至少一部分位於封裝10與封裝20之間。舉例來說，底部填充膠700可填充封裝10與封裝20之間的間隙，使得底部填充膠700直接接觸晶粒200的非晶層212。在形成底部填充膠700之後，得到疊層封裝結構1000。
根據本公開的一些實施例，一種疊層封裝(PoP)結構包括第一封裝及堆疊在所述第一封裝上的第二封裝。所述第一封裝具有晶粒、多個導電結構、包封體及重佈線結構。所述晶粒具有主動表面及與所述主動表面相對的後表面。所述晶粒包括位於後表面上的非晶層。所述導電結構環繞所述晶粒。所述包封體包封所述晶粒及所述導電結構。所述重佈線結構位於所述晶粒的主動表面上且與所述導電結構及所述晶粒電性連接。
根據本公開的一些實施例，所述非晶層包括非晶矽層。
根據本公開的一些實施例，所述非晶層的厚度對所述晶粒的厚度的比率介於約1：133.3與約1：250000之間。
根據本公開的一些實施例，所述非晶層的厚度介於約1nm與約300nm之間。
根據本公開的一些實施例，所述非晶層的表面與所述包封體的表面實質上共面。
根據本公開的一些實施例，所述非晶層的表面位於與所述包封體的表面不同的水平高度處。
根據本公開的一些實施例，所述疊層封裝還包括位於所述重佈線結構上的多個導電端子。
根據本公開的一些實施例，所述疊層封裝還包括多個連接端子以及底部填充膠。所述多個連接端子夾置在所述第一封裝與所述第二封裝之間。所述底部填充膠包封所述多個連接端子。
根據本公開的一些實施例，所述底部填充膠直接接觸所述非晶層。
根據本公開的一些實施例，一種製造封裝體的方法包括至少以下步驟。提供載板。所述載板上形成有剝離層。在所述剝離層上形成導電結構。所述導電結構包括貼合到所述剝離層的晶種層。通過黏合層將晶粒貼合到所述剝離層上。所述晶粒包括貼合到所述黏合層的非晶層。移除載板。移除所述剝離層及所述黏合層以暴露出所述非晶層。在移除所述剝離層及所述黏合層之後，移除所述晶種層的一部分。
根據本公開的一些實施例，移除所述剝離層及所述黏合層包括執行乾式蝕刻製程。
根據本公開的一些實施例，所述乾式蝕刻製程的蝕刻劑不含CF4氣體。
根據本公開的一些實施例，所述乾式蝕刻製程的蝕刻劑包含氬氣(Ar)氣體、氮氣(N2)氣體、氧氣(O2)氣體或其組合。
根據本公開的一些實施例，所述乾式蝕刻製程的持續時 間為10秒到180秒。
根據本公開的一些實施例，所述製造封裝體的方法還包括至少以下步驟。在所述晶粒及所述導電結構上形成重佈線結構。在所述重佈線結構上形成導電端子。
根據本公開的一些實施例，一種製造封裝體的方法包括至少以下步驟。提供載板。所述載板上形成有剝離層。在所述剝離層上形成導電結構。通過黏合層將晶粒貼合到所述剝離層上。所述晶粒包括半導體基板及覆蓋所述半導體基板的非晶層。所述非晶層貼合到所述黏合層。在所述晶粒及所述導電結構上形成重佈線結構。移除載板。執行乾式蝕刻製程以移除所述剝離層。執行濕式蝕刻製程以移除所述黏合層，且在執行所述濕式蝕刻製程之後留下所述非晶層以覆蓋所述晶粒的所述半導體基板。
根據本公開的一些實施例，所述導電結構包括貼合到所述剝離層的晶種層，且執行所述乾式蝕刻製程還包括移除所述晶種層的一部分。
根據本公開的一些實施例，所述乾式蝕刻製程的蝕刻劑包含CF4氣體。
根據本公開的一些實施例，所述製造封裝體的方法還包括用包封體包封所述晶粒及所述導電結構。
根據本公開的一些實施例，執行所述濕式蝕刻製程還包括移除所述包封體的一部分。
以上概述了若干實施例的特徵，以使所屬領域中的技術 人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
10、20:封裝
100:導電結構
114b:第二子層
120a:導電圖案
200:晶粒
212:非晶層
300:包封體
400:重佈線結構
400a:層間介電層
400b:重佈線導電圖案
500:導電端子
600:連接端子
700:底部填充膠
1000:疊層封裝結構

Claims (10)

  1. 一種疊層封裝結構，包括：第一封裝，包括：晶粒，具有主動表面及與所述主動表面相對的後表面，其中所述晶粒包括位於所述後表面上的非晶層；多個導電結構，環繞所述晶粒；包封體，包封所述晶粒及所述多個導電結構；以及重佈線結構，位於所述晶粒的所述主動表面上，其中所述重佈線結構與所述多個導電結構及所述晶粒電性連接；以及第二封裝，堆疊在所述第一封裝上。
  2. 如申請專利範圍第1項所述的疊層封裝結構，其中所述非晶層的表面與所述包封體的表面實質上共面。
  3. 一種疊層封裝結構，包括：第一封裝，包括：晶粒，具有主動表面及與所述主動表面相對的後表面，其中所述晶粒包括位於所述後表面上的非晶層；包封體，包封所述晶粒，其中所述晶粒的厚度小於所述包封體的厚度；以及重佈線結構，位於所述晶粒的所述主動表面上，其中所述重佈線結構與所述晶粒電性連接；以及第二封裝，堆疊在所述第一封裝上。
  4. 如申請專利範圍第3項所述的疊層封裝結構，其中所述非晶層包括非晶矽層。
  5. 一種疊層封裝結構，包括：第一封裝，包括：晶粒，具有主動表面及與所述主動表面相對的後表面，其中所述晶粒包括位於所述後表面上的非晶層；多個導電結構，環繞所述晶粒，其中每一所述多個導電結構包括導電圖案及配置在所述導電圖案上的晶種層圖案；以及包封體，包封所述晶粒及所述多個導電結構，其中所述晶種層圖案的頂表面位於比所述包封體的頂表面低的水平高度處；以及第二封裝，堆疊在所述第一封裝上。
  6. 一種製造封裝體的方法，包括：提供載板，其中所述載板上形成有剝離層；在所述剝離層上形成導電結構，其中所述導電結構包括貼合到所述剝離層的晶種層；通過黏合層將晶粒貼合到所述剝離層上，其中所述晶粒包括貼合到所述黏合層的非晶層；移除載板；移除所述剝離層及所述黏合層以暴露出所述非晶層；以及在移除所述剝離層及所述黏合層之後，移除所述晶種層的一部分。
  7. 如申請專利範圍第6項所述的製造封裝體的方法，其中移除所述剝離層及所述黏合層包括執行乾式蝕刻製程。
  8. 一種製造封裝體的方法，包括：提供載板，其中所述載板上形成有剝離層；在所述剝離層上形成導電結構；通過黏合層將晶粒貼合到所述剝離層上，其中所述晶粒包括半導體基板及覆蓋所述半導體基板的非晶層，且所述非晶層貼合到所述黏合層；在所述晶粒及所述導電結構上形成重佈線結構；移除載板；執行乾式蝕刻製程以移除所述剝離層；以及執行濕式蝕刻製程以移除所述黏合層，且在執行所述濕式蝕刻製程之後留下所述非晶層以覆蓋所述晶粒的所述半導體基板。
  9. 如申請專利範圍第8項所述的製造封裝體的方法，其中所述導電結構包括貼合到所述剝離層的晶種層，且執行所述乾式蝕刻製程還包括移除所述晶種層的一部分。
  10. 一種製造封裝體的方法，包括：提供剝離層；在所述剝離層上形成導電結構，其中所述導電結構包括貼合到所述剝離層的晶種層；通過黏合層將晶粒貼合到所述剝離層上，其中所述晶粒包括貼合到所述黏合層的非晶層； 移除所述剝離層及所述黏合層以暴露出所述非晶層；在移除所述剝離層及所述黏合層之後，移除所述晶種層的一部分；用包封體包封所述晶粒及所述導電結構；以及移除所述包封體的一部分。
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