CN110660750A - 叠层封装结构 - Google Patents

叠层封装结构 Download PDF

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Publication number
CN110660750A
CN110660750A CN201811196282.1A CN201811196282A CN110660750A CN 110660750 A CN110660750 A CN 110660750A CN 201811196282 A CN201811196282 A CN 201811196282A CN 110660750 A CN110660750 A CN 110660750A
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Prior art keywords
layer
die
package
conductive
etching process
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CN201811196282.1A
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CN110660750B (zh
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郑礼辉
高金福
简智源
卢思维
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种叠层封装(package‑on‑package，PoP)结构包括第一封装及堆叠在所述第一封装上的第二封装。所述第一封装包括管芯、多个导电结构、包封体及重布线结构。所述管芯具有有源表面及与所述有源表面相对的后表面。所述管芯包括位于后表面上的非晶层。所述导电结构环绕所述管芯。所述包封体包封所述管芯及所述导电结构。所述重布线结构位于所述管芯的有源表面上且与所述导电结构及所述管芯电连接。

Description

叠层封装结构
技术领域
本发明实施例涉及一种叠层封装结构。更具体来说，本发明实施例涉及一种在管芯中包括非晶层的叠层封装结构。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续提高，半导体行业已经历快速增长。在很大程度上，集成密度的此种提高来自于最小特征大小(minimum feature size)的重复减小，此使得更多较小的组件能够集成到给定区域中。这些较小的电子组件也需要与先前的封装相比利用较小区域的较小的封装。当前，集成扇出型封装因其紧凑性而正变得日渐流行。如何确保集成扇出型封装的可靠性已成为此领域中的挑战。
发明内容
一种叠层封装结构包括第一封装及堆叠在所述第一封装上的第二封装。所述第一封装具有管芯、多个导电结构、包封体及重布线结构。所述管芯具有有源表面及与所述有源表面相对的后表面。所述管芯包括位于后表面上的非晶层。所述导电结构环绕所述管芯。所述包封体包封所述管芯及所述导电结构。所述重布线结构位于所述管芯的有源表面上且与所述导电结构及所述管芯电连接。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A到图1R是根据本公开一些实施例的叠层封装(package-on-package，PoP)结构的制造工艺的示意性剖视图。
图2A是根据本公开一些替代性实施例的叠层封装结构的制造工艺的中间阶段的示意性剖视图。
图2B是根据本公开一些替代性实施例的叠层封装结构的制造工艺的中间阶段的示意性剖视图。
图3A到图3D是根据本公开一些替代性实施例的叠层封装结构的制造工艺的混合刻蚀工艺(hybrid etching process)的示意性剖视图。
附图标号说明
10、20：封装
10a：封装阵列
100、100’：导电结构
110a：晶种材料层
110b：晶种层
112a、112b：第一子层
114a、114b：第二子层
120’：导电材料
120a：导电图案
200：管芯
100a’、200a、300a、300a’：顶表面
100b、200b、300b：后表面
200c：有源表面
202：半导体衬底
204：导电接垫
206：钝化层
208：导通孔
210、210a：保护层
212：非晶层
300：包封体
300’：包封材料
400：重布线结构
400a：层间介电层
400b：重布线导电图案
500：导电端子
600：连接端子
700：底部填充胶
1000：叠层封装结构
AD：粘合层
C：载板
DB：剥离层
DE：干式刻蚀工艺
M：掩模
OP：开口
R1、R2：凹槽
T200、T212：厚度
TP：胶带
WE：湿式刻蚀工艺
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开。当然，这些仅为实例而非旨在进行限制。举例来说，在以下说明中，在第二特征之上或第二特征上形成第一特征可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成附加特征从而使得第一特征与第二特征可不直接接触的实施例。另外，本公开在各种实例中可重复使用参考编号和/或字母。此种重复使用是为了简明及清晰起见，且自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等空间相对性用语来阐述图中所示一个元件或特征与另一(其他)元件或特征的关系。除附图中所绘示的取向以外，所述空间相对性用语旨在涵盖装置在使用或操作中的不同取向。设备可被另外取向(旋转90度或处于其他取向)，且本文所使用的空间相对性描述语可同样相应地作出解释。
本公开也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(three-dimensional，3D)封装或三维集成电路(three-dimensional integratedcircuit，3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫，以使得能够对三维封装或三维集成电路进行测试、对探针和/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包括对已知良好管芯(known good die)进行中间验证的测试方法来使用，以提高良率并降低成本。
图1A到图1R是根据本公开一些实施例的叠层封装(PoP)结构1000的制造工艺的示意性剖视图。参照图1A，提供上面形成有剥离层DB的载板C。在一些实施例中，剥离层DB形成在载板C的顶表面上。载板C为例如玻璃衬底。另一方面，在一些实施例中，剥离层DB可为形成在所述玻璃衬底上的光热转换(light-to-heat conversion，LTHC)释放层。在一些替代性实施例中，剥离层可由胶(glue)或聚合物系材料(polymer-based material)制成。然而，以上列出的载板C及剥离层DB的材料仅用于示例性说明，且本公开并非仅限于此。在一些替代性实施例中，其他材料可适合作为载板C，只要所述材料能够在承载/支撑随后形成的元件的同时经受随后的工艺即可。类似地，其他材料可适合作为剥离层DB，只要所述材料能够在后续工艺中执行释放功能即可。
参照图1B，在剥离层DB上形成晶种材料层110a。在一些实施例中，晶种材料层110a可为由不同的材料所形成的复合层。举例来说，晶种材料层110a可包括第一子层112a及第二子层114a。在一些实施例中，第二子层114a形成在第一子层112a上。举例来说，第一子层112a夹置在剥离层DB与第二子层114a之间。在一些实施例中，第一子层112a的材料可包括钛、氮化钛、钽、氮化钽、其他合适的材料或其组合。另一方面，第二子层114a的材料可包括例如铜、铜合金或其他合适的材料选择。在一些实施例中，第一子层112a及第二子层114a是通过物理气相沉积或其他合适的方法来形成。第一子层112a可具有大约0.01μm到大约1μm的厚度。另一方面，第二子层114a的厚度也可介于约0.01μm到约1μm之间。
参照图1C，在晶种材料层110a上形成掩模M。对掩模M进行图案化以形成多个开口OP。在一些实施例中，开口OP暴露出随后形成的导电结构100’(示于图1F中)的预期位置。在一些实施例中，掩模M的开口OP暴露出晶种材料层110a的一部分。举例来说，掩模M暴露出第二子层114a的一部分。在一些实施例中，掩模M可由感光性材料来形成。举例来说，掩模M可为光刻胶或干膜(dry film)。
参照图1D，将导电材料120’填充到掩模M的开口OP中。在一些实施例中，导电材料120’形成在晶种材料110a的第二子层114a的被掩模M的开口OP暴露出的部分上。在一些实施例中，可通过镀覆工艺来形成导电材料120’。镀覆工艺例如为电镀、无电镀覆、浸镀等。导电材料120’例如为铜、铜合金等。换句话说，晶种材料层110a的第二子层114a及导电材料120’可由同一种材料制成。然而，本公开并非仅限于此。在一些替代性实施例中，第二子层114a与导电材料120’可包含不同的材料。
参照图1D及图1E，随后移除掩模M以得到位于晶种材料层110a上的多个导电图案120a。在一些实施例中，可通过剥除工艺、刻蚀工艺及/或清洁工艺来移除掩模M。由于导电图案120a是通过将导电材料120’填充到掩模M的开口OP中所形成，因此导电图案120a可具有与掩模M的开口OP相同的轮廓。
参照图1E及图1F，对晶种材料层110a进行图案化以形成晶种层110b。如图1F所示，晶种层110b可由与导电图案120a对应的多个晶种层图案构成。以下将阐述晶种材料层110a的图案化。
在一些实施例中，通过第一刻蚀工艺选择性地移除第二子层114a被导电图案120a暴露出的部分。在一些实施例中，第一刻蚀工艺可包括例如干式刻蚀等各向异性刻蚀工艺或例如湿式刻蚀等各向同性刻蚀工艺。在一些实施例中，氩气(Ar)气体、氮气(N2)气体、氧气(O2)气体、四氟甲烷(tetrafluoromethane，CF4)气体或其组合可作为干式刻蚀的刻蚀剂。在一些替代性实施例中，氟化氢(hydrogen fluoride，HF)溶液、磷酸(phosphoric acid，H3PO4)溶液、过氧化氢(hydrogen peroxide，H2O2)溶液、氢氧化铵(ammonium hydroxide，NH4OH)溶液或其组合可作为湿式刻蚀的刻蚀剂。第一刻蚀工艺移除第二子层114a的部分以形成第二子层114b。应注意的是，以上所列出的刻蚀剂仅用于示例性说明，且其他类型的刻蚀剂也可作为对第二子层114a进行刻蚀的刻蚀剂。
在移除第二子层114a的部分之后，第一子层112a的部分会被导电图案120a及剩余的第二子层114b暴露出。可通过第二刻蚀工艺来移除第一子层112a被暴露的部分。在一些实施例中，可通过干式刻蚀工艺或湿式刻蚀工艺对第一子层112a进行刻蚀以得到第一子层112b。用于移除第一子层112a的刻蚀剂可包括氟系气体，例如四氟甲烷(CF4)气体、三氟甲烷(fluoroform，CHF3)气体、其他合适的气体或其组合。在一些替代性实施例中，用于移除第一子层112a的刻蚀剂可包括氟化氢(HF)溶液或其他合适的刻蚀溶液。应注意的是，以上所列出的刻蚀剂仅用于示例性说明，且其他类型的刻蚀剂也可作为对第一子层112a进行刻蚀的刻蚀剂。
在一些实施例中，可将导电图案120a及晶种层110b(包括第一子层112b及第二子层114b)统称为导电结构100’。换句话说，如图1F所示，导电结构100’形成在剥离层DB上。在一些实施例中，每一导电结构100’包括贴合到剥离层DB的晶种层110b。举例来说，导电结构100’的晶种层110b直接接触剥离层DB。
参照图1G，将多个管芯200放置在剥离层DB上。在一些实施例中，管芯200位于导电结构100’之间。举例来说，管芯200排列成阵列且被导电结构100’环绕。在一些实施例中，每一管芯200具有顶表面200a及与顶表面200a相对的后表面200b。如图1G所示，管芯200被放置成顶表面200a朝上而后表面200b面对剥离层DB。在一些实施例中，通过拾取及放置工艺(pick-and-place process)将管芯200放置在剥离层DB上。在一些实施例中，每一管芯200可为存储器管芯(即，动态随机存取存储器(dynamic random access memory，DRAM)、静态随机存取存储器(static random access memory，SRAM)、非易失性随机存取存储器(nonvolatile random access memory，NVRAM)及/或类似管芯)、逻辑管芯、射频(radiofrequency，RF)管芯或处理器管芯(即，加速处理器(accelerated processor，AP)等)。以下将阐述每一管芯200的样态。
在一些实施例中，每一管芯200包括半导体衬底202、多个导电接垫204、钝化层206、多个导通孔208、保护层210及非晶层(amorphous layer)212。在一些实施例中，半导体衬底202可为硅衬底。在一些替代性实施例中，半导体衬底202可由下列制成：合适的元素半导体，例如金刚石或锗；合适的化合物半导体，例如砷化镓、碳化硅、砷化铟或磷化铟；或者合适的合金半导体，例如碳化硅锗(silicon germanium carbide)、磷化镓砷(galliumarsenic phosphide)或磷化镓铟(gallium indium phosphide)。在一些实施例中，半导体衬底202包括形成在半导体衬底202中的有源组件(例如，晶体管等)及无源组件(例如，电阻器、电容器、电感器等)。
在一些实施例中，导电接垫204分布在半导体衬底202上。导电接垫204可为铝接垫、铜接垫或其他合适的金属接垫。钝化层206形成在半导体衬底202上且具有局部地暴露出导电接垫204的接触开口。钝化层206可为氧化硅层、氮化硅层、氮氧化硅层或由其他合适的介电材料形成的介电层。在一些实施例中，可在钝化层206上进一步形成后钝化层(未示出)。另外，导通孔208形成在导电接垫204上。在一些实施例中，导通孔208被镀覆在导电接垫204上以使得导通孔208与导电接垫204电连接。导通孔208可为铜通孔或其他合适的金属通孔。保护层210形成在钝化层206上以覆盖导通孔208。在一些实施例中，保护层210可为聚苯并恶唑(polybenzoxazole，PBO)层、聚酰亚胺(polyimide，PI)层或由其他合适的聚合物制成的层。在一些替代性实施例中，保护层210可由无机材料制成。
在一些实施例中，在将管芯200放置在剥离层DB上之前，对每一管芯200执行薄化工艺。举例来说，可对每一管芯200的后表面200b执行背侧研磨工艺以减小管芯200的总厚度。在薄化工艺期间，部分半导体衬底202会被研磨。在研磨工艺期间产生的应力会破坏半导体衬底202位于经研磨表面上的部分的晶格，从而在管芯200的后表面200b上形成非晶层212。如图1G所示，非晶层212位于半导体衬底202上且与半导体接垫204相对。在一些实施例中，非晶层212直接接触半导体衬底202且覆盖半导体衬底202。在一些实施例中，当半导体衬底202为硅衬底时，非晶层212可为非晶硅层。另一方面，当半导体衬底202包括其他类型的半导体时，非晶层212可为其他类型的非晶半导体层。在一些实施例中，非晶层212的厚度T212介于约1nm与约300nm之间。另一方面，管芯200的厚度T200介于约40μm与约250μm之间。在一些实施例中，非晶层212的厚度T212对管芯200的厚度T200的比率介于约1:133.3与约1:250000之间。
在一些实施例中，管芯200通过粘合层AD粘附到剥离层DB。在一些实施例中，位于管芯200的后表面200b上的非晶层212贴合到粘合层AD。举例来说，非晶层212可直接接触粘合层AD而使得粘合层AD夹置在非晶层212与剥离层DB之间。在一些实施例中，粘合层AD可包括管芯贴合膜(die attach film，DAF)。然而，本公开并非仅限于此。在一些替代性实施例中，其他材料可作为粘合层AD，只要所述材料能够加强管芯20与剥离层DB之间的粘附性即可。
参照图1H，在剥离层DB上形成包封材料300’以包封导电结构100’及管芯200。在一些实施例中，包封材料300’是模制化合物、模制底部填充胶(molding underfill)、树脂(例如环氧树脂)等。可通过模制工艺(例如压缩模制工艺(compression molding process))来形成包封材料300’。在一些实施例中，包封材料300’的顶表面300a’位于比管芯200的顶表面200a及导电结构100’的顶表面100a’高的水平高度处。换句话说，导电结构100’及每一管芯200的保护层210不会被显露出而是被包封材料300’很好地保护住。
参照图1H及图1I，研磨包封材料300’及管芯200的保护层210，直到暴露出导电结构100’的顶表面100a’以及管芯200的导通孔208的顶表面为止。在对包封材料300’进行研磨之后，包封体300形成在剥离层DB上以包封导电结构100’及管芯200。包封体300暴露出每一管芯200的至少部分以及每一导电结构100’的至少部分。在一些实施例中，通过机械研磨、化学机械抛光(chemical mechanical polishing，CMP)或其他合适的机制来研磨包封材料300’。在研磨工艺期间，保护层210的部分也受到研磨以显露出导通孔208，由此形成保护层210a。在一些实施例中，在包封材料300’及保护层210的研磨工艺期间，导电结构100’的部分及/或导通孔208的部分也可受到轻微地研磨。在研磨之后，每一管芯200具有与后表面200b相对的有源表面200c。导通孔208被暴露出的部分位于管芯200的有源表面200c上。应注意的是，导电结构100’的顶表面100a’、包封体300的顶表面300a及管芯200的有源表面200c实质上彼此共面。
参照图1J，在导电结构100’、管芯200及包封体300上形成重布线结构400。在一些实施例中，重布线结构400形成在导电结构100’的顶表面100a’、管芯200的有源表面200c及包封体300的顶表面300a上，以与导电结构100’及管芯200电连接。如图1J所示，重布线结构400包括交替堆叠的多个层间介电层400a与多个重布线导电图案400b。重布线导电图案400b与嵌置在包封体300中的管芯200的导通孔208以及导电结构100’电连接。在一些实施例中，最底的层间介电层400a局部地覆盖导通孔208的顶表面及导电结构100’的顶表面100a’以形成多个接触开口。最底的重布线导电图案400b延伸到最底的层间介电层400的接触开口中以物理接触(physical contact)导通孔208的顶表面及导电结构100’的顶表面100a’。如图1J所示，最顶的重布线导电图案400b包括多个接垫。在一些实施例中，上述接垫可包括多个球下金属(under-ball metallurgy，UBM)图案以用于球安装。在一些替代性实施例中，上述接垫还可包括用于安装无源组件的多个连接垫。
在一些实施例中，重布线导电图案400b的材料包括铝、钛、铜、镍、钨及/或其合金。可通过例如电镀、沉积及/或光刻以及刻蚀来形成重布线导电图案400b。在一些实施例中，层间介电层400a的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(PBO)或其他合适的聚合物系介电材料。可通过例如旋转涂布(spin-on coating)、化学气相沉积(chemical vapor deposition，CVD)、等离子体增强型化学气相沉积(plasma-enhanced chemical vapor deposition，PECVD)等合适的制作技术来形成层间介电层400a。
参照图1K，在形成重布线结构400之后，将多个导电端子500放置在重布线结构400的最顶的重布线导电图案400b(UBM图案)上。在一些实施例中，导电端子500包括焊料球。在一些实施例中，可通过植球工艺或其他合适的工艺将导电端子500放置在UBM图案上。
参照图1K及图1L，在重布线结构400上形成导电端子500之后，移除载板C。在一些实施例中，可利用紫外(UV)激光照射剥离层DB(例如，LTHC释放层)而使得载板C可被剥落来实现载板C的移除。在剥落工艺期间，剥离层DB的一部分会黏附在载板C上且可被载板C带走。同时，剥离层DB的另一部分留在粘合层AD、包封体300及导电结构100’上。在移除载板C之后，将此结构上下颠倒，使得管芯200的后表面200b朝上。将经颠倒的结构放置在胶带TP上以供进一步处理，如图1L所示。
在一些实施例中，移除剩余的剥离层DB而暴露出导电结构100’以用于未来的电连接。在一些实施例中，粘合层AD具有较差的导热性，这将会导致在管芯200的操作期间产生的热量积聚在随后形成的封装10(示于图1R中)内，因而会损害随后形成的封装10的性能及寿命。因此，在一些实施例中，可移除粘合层AD以增强随后形成的封装10的性能及寿命。在一些实施例中，为了进一步增强导电结构100’与随后形成的元件之间的粘附性，可移除晶种层110b的第一子层112b以暴露出第二子层114b。在一些实施例中，可通过包括多个刻蚀步骤的混合刻蚀工艺(hybrid etching process)来实现剥离层DB、粘合层AD及晶种层110b的第一子层112b的移除。举例来说，混合刻蚀工艺可包括湿式刻蚀工艺及在其之前执行的干式刻蚀工艺。以下将结合图1M到图1P来论述混合刻蚀工艺。
参照图1M及图1N，对图1M所示结构执行干式刻蚀工艺DE，以移除剥离层DB及粘合层AD。在一些实施例中，干式刻蚀工艺DE的刻蚀剂不含氟化合物。举例来说，干式刻蚀工艺DE的刻蚀剂不包含四氟甲烷(CF4)气体。另一方面，干式刻蚀工艺DE的刻蚀剂可包含氩气(Ar)气体、氮气(N2)气体及/或氧气(O2)气体。应注意的是，以上所列出的刻蚀剂仅用于示例性说明，且其他气体也可作为干式刻蚀工艺DE的刻蚀剂，只要不包含氟化合物即可。在一些实施例中，干式刻蚀工艺DE的持续时间为10秒到300秒。如图1N所示，干式刻蚀工艺DE不会移除位于粘合层AD下的非晶层212。即，在整个干式刻蚀工艺DE中，每一管芯200的半导体衬底202被非晶层212覆盖。因此，非晶层212可充当障壁层(barrier layer)以防止在干式刻蚀工艺DE期间产生的杂质损坏半导体衬底202或扩散到半导体衬底202中，由此确保管芯200的可靠性。
如图1N所示，干式刻蚀工艺DE移除粘合层AD以在包封体300中形成凹槽R1。在一些实施例中，凹槽R1暴露出每一管芯200的非晶层212。由于非晶层212位于凹槽R1中，因此非晶层212的表面(即，管芯200的后表面200b)位于与包封体300的后表面300b不同的水平高度处。举例来说，非晶层212的表面可位于比包封体300的后表面300b低的水平高度处。即，包封体300的厚度可大于管芯200的厚度。
参照图1O及图1P，在干式刻蚀工艺DE之后，对图1O所示结构执行湿式刻蚀工艺WE以移除晶种层110b的一部分。举例来说，可通过湿式刻蚀工艺WE来移除晶种层110b的第一子层112b。在一些实施例中，湿式刻蚀工艺WE的刻蚀剂包括氟化氢(HF)溶液、磷酸(H3PO4)溶液、过氧化氢(H2O2)溶液、氢氧化铵(NH4OH)溶液或其组合。应注意的是，以上所列出的刻蚀剂仅用于示例性说明，且其他溶液也可作为湿式刻蚀工艺WE的刻蚀剂。如图1P所示，湿式刻蚀工艺WE不会移除被暴露的非晶层212。即，在整个湿式刻蚀工艺WE中，每一管芯200的半导体衬底202被非晶层212覆盖。因此，非晶层212可充当障壁层以防止在湿式刻蚀工艺WE期间产生的金属杂质(例如，晶种层110a中的铜或钛)破坏半导体衬底202或扩散到半导体衬底202中。因此，可消除铜化合物扩散到半导体衬底202中的鳍式铜问题(copper-in-finissue)，且可确保管芯200的可靠性。
如图1P所示，在执行混合刻蚀工艺之后得到封装阵列10a。在一些实施例中，在混合刻蚀工艺之后，非晶层212仍保留在每一管芯200的后表面200b上以覆盖半导体衬底202。如图1P所示，湿式刻蚀工艺WE移除晶种层110a的第一子层112b以在包封体300中形成凹槽R2。在一些实施例中，凹槽R2暴露出晶种层110b的第二子层114b。在一些实施例中，晶种层110b的第二子层114b与导电图案120a构成多个导电结构100。由于晶种层110b的第二子层114b位于凹槽R2中，因此导电结构100的后表面100b位于与包封体300的后表面300b不同的水平高度处。举例而言，导电结构100的后表面100b可位于比包封体300的后表面300b低的水平高度处。应注意的是，尽管导电结构100的后表面100b、管芯200的后表面200b及包封体300的后表面300b被示出为位于不同的水平高度处，然而本公开并非仅限于此。在一些替代性实施例中，在混合刻蚀工艺期间，可移除包封体300的一部分从而呈现出不同的样态。以下将结合图2A及图2B来论述不同的样态。
图2A是根据本公开一些替代性实施例的叠层封装结构1000的制造工艺的中间阶段的示意性剖视图。参照图2A，在干式刻蚀工艺DE及/或湿式刻蚀工艺WE期间，可对包封体300的一部分进行刻蚀。因此，导电结构100的后表面100b及/或管芯200的后表面200b可与包封体300的后表面300b实质上共面。即，包封体300的厚度可实质上等于管芯200的厚度。
图2B是根据本公开一些替代性实施例的叠层封装结构1000的制造工艺的中间阶段的示意性剖视图。参照图2B，在干式刻蚀工艺DE及/或湿式刻蚀工艺WE期间，可对包封体300的一部分进行刻蚀。因此，包封体300的后表面300b可位于与管芯200的后表面200b及导电结构100的后表面100b不同的水平高度处。举例来说，包封体300的后表面300b可位于比管芯200的后表面200b及导电结构100的后表面100b低的水平高度处。即，包封体300的厚度可小于管芯200的厚度。
应注意的是，图1M到图1P所示步骤仅为混合刻蚀工艺的示例性说明，且本公开并非仅限于此。在一些替代性实施例中，混合刻蚀工艺可包括不同的步骤。以下将结合图3A到图3D来论述移除剥离层DB、粘合层AD及晶种层110b的第一子层112b的另一示例性混合刻蚀工艺。
图3A到图3D是根据本公开一些替代性实施例的叠层封装结构1000的制造工艺的混合刻蚀工艺的示意性剖视图。参照图3A及图3B，对图3A所示结构执行干式刻蚀工艺DE，以移除剥离层DB以及晶种层110b的一部分。举例来说，可通过干式刻蚀工艺DE来移除剥离层DB以及晶种层110b的第一子层112b。在一些实施例中，干式刻蚀工艺DE的刻蚀剂包含四氟甲烷(CF4)气体。在一些实施例中，干式刻蚀工艺DE的刻蚀剂还可进一步包含氩气(Ar)气体、氮气(N2)气体及/或氧气(O2)气体。应注意的是，以上所列出的刻蚀剂仅用于示例性说明，且其他气体也可作为干式刻蚀工艺DE的刻蚀剂。在一些实施例中，干式刻蚀工艺DE的持续时间为10秒到180秒。通过将干式刻蚀工艺DE的持续时间控制在上述范围内，可充分移除剥离层DB以及晶种层110b的第一子层112b而不会完全移除粘合层AD。换句话说，在整个干式刻蚀工艺DE中，每一管芯200的半导体衬底202以及非晶层212被粘合层AD覆盖。因此，粘合层AD及非晶层212可充当障壁层以防止在干式刻蚀工艺DE期间产生的金属杂质(例如，晶种层110a中的铜或钛)重新沉积或扩散到半导体衬底202中。因此，可消除铜化合物扩散到半导体衬底202中的鳍式铜问题，且可确保管芯200的可靠性。
参照图3C及图3D，在干式刻蚀工艺DE之后，对图3C所示结构执行湿式刻蚀工艺WE，以移除粘合层AD。在一些实施例中，湿式刻蚀工艺WE的刻蚀剂包括氟化氢(HF)溶液、磷酸(H3PO4)溶液、过氧化氢(H2O2)溶液、氢氧化铵(NH4OH)溶液或其组合。应注意的是，以上所列出的刻蚀剂仅用于示例性说明，且其他溶液也可作为湿式刻蚀工艺WE的刻蚀剂。如图3D所示，在湿式刻蚀工艺WE之后，非晶层212保留在管芯200的后表面200b上。即，在整个湿式刻蚀工艺WE中，每一管芯200的半导体衬底202被非晶层212覆盖。因此，非晶层212可充当障壁层以防止在湿式刻蚀工艺WE期间产生的杂质损坏半导体衬底202或扩散到半导体衬底202中，由此确保管芯200的可靠性。
返回参照图1Q，在执行混合刻蚀工艺之后，在封装阵列10a上堆叠多个封装20。在一些实施例中，封装阵列10a具有双侧端子设计以容置封装20。封装20例如为集成电路(integrated circuit，IC)封装。封装20通过夹置在封装20与封装阵列10a之间的多个连接端子600与封装阵列10a电连接。在一些实施例中，连接端子600为通过植球工艺及/或回焊工艺而形成的焊料接头(solder joint)。应注意的是，图1Q仅充当示例性说明，且本公开并非仅限于此。在一些替代性实施例中，可在封装阵列10a上堆叠例如集成扇出型(integrated fan-out，InFO)封装、存储器装置、球栅阵列封装(ball grid array，BGA)或晶片(wafer)等其他电子装置来取代封装20。
参照图1R，对封装阵列10a进行切割或单体化，以形成上面堆叠有封装20的多个封装10。在一些实施例中，切割工艺或单体化工艺通常涉及利用旋转刀片或激光束进行切割。换句话说，切割或单体化工艺为例如激光切割工艺、机械切割工艺或其他合适的工艺。在一些实施例中，可将封装10称为集成扇出型封装。在一些实施例中，形成底部填充胶700以包封连接端子600。在一些实施例中，底部填充胶700的至少一部分位于封装10与封装20之间。举例来说，底部填充胶700可填充封装10与封装20之间的间隙，使得底部填充胶700直接接触管芯200的非晶层212。在形成底部填充胶700之后，得到叠层封装结构1000。
根据本公开的一些实施例，一种叠层封装(PoP)结构包括第一封装及堆叠在所述第一封装上的第二封装。所述第一封装具有管芯、多个导电结构、包封体及重布线结构。所述管芯具有有源表面及与所述有源表面相对的后表面。所述管芯包括位于后表面上的非晶层。所述导电结构环绕所述管芯。所述包封体包封所述管芯及所述导电结构。所述重布线结构位于所述管芯的有源表面上且与所述导电结构及所述管芯电连接。
根据本公开的一些实施例，所述非晶层包括非晶硅层。
根据本公开的一些实施例，所述非晶层的厚度对所述管芯的厚度的比率介于约1:133.3与约1:250000之间。
根据本公开的一些实施例，所述非晶层的厚度介于约1nm与约300nm之间。
根据本公开的一些实施例，所述非晶层的表面与所述包封体的表面实质上共面。
根据本公开的一些实施例，所述非晶层的表面位于与所述包封体的表面不同的水平高度处。
根据本公开的一些实施例，所述叠层封装还包括位于所述重布线结构上的多个导电端子。
根据本公开的一些实施例，所述叠层封装还包括多个连接端子以及底部填充胶。所述多个连接端子夹置在所述第一封装与所述第二封装之间。所述底部填充胶包封所述多个连接端子。
根据本公开的一些实施例，所述底部填充胶直接接触所述非晶层。
根据本公开的一些实施例，一种制造封装体的方法包括至少以下步骤。提供载板。所述载板上形成有剥离层。在所述剥离层上形成导电结构。所述导电结构包括贴合到所述剥离层的晶种层。通过粘合层将管芯贴合到所述剥离层上。所述管芯包括贴合到所述粘合层的非晶层。移除载板。移除所述剥离层及所述粘合层以暴露出所述非晶层。在移除所述剥离层及所述粘合层之后，移除所述晶种层的一部分。
根据本公开的一些实施例，移除所述剥离层及所述粘合层包括执行干式刻蚀工艺。
根据本公开的一些实施例，所述干式刻蚀工艺的刻蚀剂不含CF4气体。
根据本公开的一些实施例，所述干式刻蚀工艺的刻蚀剂包含氩气(Ar)气体、氮气(N2)气体、氧气(O2)气体或其组合。
根据本公开的一些实施例，所述干式刻蚀工艺的持续时间为10秒到180秒。
根据本公开的一些实施例，所述制造封装体的方法还包括至少以下步骤。在所述管芯及所述导电结构上形成重布线结构。在所述重布线结构上形成导电端子。
根据本公开的一些实施例，一种制造封装体的方法包括至少以下步骤。提供载板。所述载板上形成有剥离层。在所述剥离层上形成导电结构。通过粘合层将管芯贴合到所述剥离层上。所述管芯包括半导体衬底及覆盖所述半导体衬底的非晶层。所述非晶层贴合到所述粘合层。在所述管芯及所述导电结构上形成重布线结构。移除载板。执行干式刻蚀工艺以移除所述剥离层。执行湿式刻蚀工艺以移除所述粘合层，且在执行所述湿式刻蚀工艺之后留下所述非晶层以覆盖所述管芯的所述半导体衬底。
根据本公开的一些实施例，所述导电结构包括贴合到所述剥离层的晶种层，且执行所述干式刻蚀工艺还包括移除所述晶种层的一部分。
根据本公开的一些实施例，所述干式刻蚀工艺的刻蚀剂包含CF4气体。
根据本公开的一些实施例，所述制造封装体的方法还包括用包封体包封所述管芯及所述导电结构。
根据本公开的一些实施例，执行所述湿式刻蚀工艺还包括移除所述包封体的一部分。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种叠层封装结构，其特征在于，包括：
第一封装，包括：
管芯，具有有源表面及与所述有源表面相对的后表面，其中所述管芯包括位于所述后表面上的非晶层；
多个导电结构，环绕所述管芯；
包封体，包封所述管芯及所述多个导电结构；以及
重布线结构，位于所述管芯的所述有源表面上，其中所述重布线结构与所述多个导电结构及所述管芯电连接；以及
第二封装，堆叠在所述第一封装上。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879221B2 (en) * 2019-05-16 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure
US11410902B2 (en) * 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100001363A1 (en) * 2008-07-02 2010-01-07 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Electrostatic Discharge Protection for Integrated Passive Devices
CN101692602A (zh) * 2009-09-28 2010-04-07 清华大学 单层电极薄膜体声波谐振器结构及其制造方法
CN102664196A (zh) * 2012-02-16 2012-09-12 友达光电股份有限公司 阵列基板及多晶硅层的制作方法
US20180040546A1 (en) * 2016-08-05 2018-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dense redistribution layers in semiconductor packages and methods of forming the same
CN107792828A (zh) * 2016-09-02 2018-03-13 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
CN108122861A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 具有虚设管芯的扇出型封装结构

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110906B2 (en) * 2007-01-23 2012-02-07 Infineon Technologies Ag Semiconductor device including isolation layer
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US20150206866A1 (en) * 2014-01-17 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Package and Methods of Forming Same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
KR20160086759A (ko) * 2014-12-15 2016-07-20 인텔 코포레이션 오포섬-다이 패키지-온-패키지 장치
US20170098629A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
WO2017078717A1 (en) * 2015-11-05 2017-05-11 Intel Corporation Stacked package assembly with voltage reference plane
JP6278035B2 (ja) * 2015-11-27 2018-02-14 日亜化学工業株式会社 発光装置の製造方法
US9935009B2 (en) * 2016-03-30 2018-04-03 International Business Machines Corporation IR assisted fan-out wafer level packaging using silicon handler
US9881903B2 (en) * 2016-05-31 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with epoxy flux residue
US20180076179A1 (en) * 2016-09-09 2018-03-15 Powertech Technology Inc. Stacked type chip package structure and manufacturing method thereof
US9893035B1 (en) * 2016-11-07 2018-02-13 Nanya Technology Corporation Stacked package structure and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100001363A1 (en) * 2008-07-02 2010-01-07 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Electrostatic Discharge Protection for Integrated Passive Devices
CN101692602A (zh) * 2009-09-28 2010-04-07 清华大学 单层电极薄膜体声波谐振器结构及其制造方法
CN102664196A (zh) * 2012-02-16 2012-09-12 友达光电股份有限公司 阵列基板及多晶硅层的制作方法
US20180040546A1 (en) * 2016-08-05 2018-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dense redistribution layers in semiconductor packages and methods of forming the same
CN107792828A (zh) * 2016-09-02 2018-03-13 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
CN108122861A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 具有虚设管芯的扇出型封装结构

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