CN110660750A

CN110660750A - Laminated packaging structure

Info

Publication number: CN110660750A
Application number: CN201811196282.1A
Authority: CN
Inventors: 郑礼辉; 高金福; 简智源; 卢思维
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-06-29
Filing date: 2018-10-15
Publication date: 2020-01-07
Anticipated expiration: 2038-10-15
Also published as: CN110660750B; US10510591B1; TWI710080B; US20200144110A1; US10867849B2; US20200006133A1; TW202002204A

Abstract

A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a back surface opposite the active surface. The die includes an amorphous layer on the back surface. The conductive structure surrounds the die. The encapsulant encapsulates the die and the conductive structure. The rewiring structure is located on the active surface of the die and is electrically connected to the conductive structure and the die.

Description

Laminated packaging structure

Technical Field

The embodiment of the invention relates to a laminated packaging structure. More particularly, embodiments of the invention relate to a stacked package structure including an amorphous layer in a die.

Background

The semiconductor industry has experienced rapid growth due to the continued increase in integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density comes from a repeated reduction in minimum feature size (minimum feature size), which enables more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize smaller areas than previous packages. Currently, integrated fan-out packages are becoming increasingly popular because of their compactness. How to ensure the reliability of integrated fan-out packages has become a challenge in this field.

Disclosure of Invention

A package on package structure includes a first package and a second package stacked on the first package. The first package has a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a back surface opposite the active surface. The die includes an amorphous layer on the back surface. The conductive structure surrounds the die. The encapsulant encapsulates the die and the conductive structure. The rewiring structure is located on the active surface of the die and is electrically connected to the conductive structure and the die.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A through 1R are schematic cross-sectional views of a fabrication process of a package-on-package (PoP) structure according to some embodiments of the present disclosure.

Fig. 2A is a schematic cross-sectional view of an intermediate stage of a fabrication process of a stacked package structure according to some alternative embodiments of the present disclosure.

Fig. 2B is a schematic cross-sectional view of an intermediate stage of a manufacturing process of a stacked package structure according to some alternative embodiments of the present disclosure.

Fig. 3A to 3D are schematic cross-sectional views of a hybrid etching process (hybrid etching process) of a manufacturing process of a stacked package structure according to some alternative embodiments of the present disclosure.

Description of the reference numerals

10. 20: package with a metal layer

10 a: package array

100. 100': conductive structure

110 a: seed material layer

110 b: seed layer

112a, 112 b: first sublayer

114a, 114 b: second sub-layer

120': conductive material

120 a: conductive pattern

200: tube core

100a ', 200a, 300 a': top surface

100b, 200b, 300 b: rear surface

200 c: active surface

202: semiconductor substrate

204: conductive pad

206: passivation layer

208: conducting hole

210. 210 a: protective layer

212: amorphous layer

300: package body

300': encapsulation material

400: heavy wiring structure

400 a: interlayer dielectric layer

400 b: rewiring conductive pattern

500: conductive terminal

600: connecting terminal

700: underfill

1000: laminated packaging structure

AD: adhesive layer

C: support plate

DB: peeling layer

DE: dry etching process

M: mask and method for manufacturing the same

OP: opening of the container

R1, R2: groove

T₂₀₀、T₂₁₂: thickness of

TP: adhesive tape

WE: wet etching process

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or feature's relationship to another (other) element or feature for ease of description. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

The present disclosure may also include other features and processes. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structure may, for example, include test pads formed in a redistribution layer or on a substrate to enable testing of a three-dimensional package or three-dimensional integrated circuit, use of probes and/or probe cards (probe cards), and the like. Verification tests may be performed on the intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that include intermediate verification of known good dies (known good die) to improve yield and reduce cost.

Fig. 1A through 1R are schematic cross-sectional views of a fabrication process of a package on package (PoP) structure 1000 according to some embodiments of the present disclosure. Referring to fig. 1A, a carrier C having a release layer DB formed thereon is provided. In some embodiments, the peeling layer DB is formed on the top surface of the carrier sheet C. The carrier C is, for example, a glass substrate. On the other hand, in some embodiments, the release layer DB may be a light-to-heat conversion (LTHC) release layer formed on the glass substrate. In some alternative embodiments, the release layer may be made of glue (glue) or polymer-based material (polymer-based material). However, the materials of the carrier sheet C and the release layer DB listed above are merely for illustrative purposes, and the present disclosure is not limited thereto. In some alternative embodiments, other materials may be suitable as carrier plate C, as long as the material is capable of undergoing subsequent processes while carrying/supporting subsequently formed components. Similarly, other materials may be suitable as the release layer DB as long as the materials can perform a releasing function in a subsequent process.

Referring to fig. 1B, a seed material layer 110a is formed on the peeling layer DB. In some embodiments, the seed material layer 110a may be a composite layer formed of different materials. For example, the seed material layer 110a may include a first sub-layer 112a and a second sub-layer 114 a. In some embodiments, the second sub-layer 114a is formed on the first sub-layer 112 a. For example, the first sub-layer 112a is interposed between the peeling layer DB and the second sub-layer 114 a. In some embodiments, the material of the first sub-layer 112a may include titanium, titanium nitride, tantalum nitride, other suitable materials, or a combination thereof. Alternatively, the material of the second sub-layer 114a may include, for example, copper, a copper alloy, or other suitable material selection. In some embodiments, the first sub-layer 112a and the second sub-layer 114a are formed by physical vapor deposition or other suitable methods. The first sub-layer 112a may have a thickness of about 0.01 μm to about 1 μm. On the other hand, the thickness of the second sub-layer 114a may also be between about 0.01 μm and about 1 μm.

Referring to fig. 1C, a mask M is formed on the seed material layer 110 a. The mask M is patterned to form a plurality of openings OP. In some embodiments, the opening OP exposes a desired location of a subsequently formed conductive structure 100' (shown in fig. 1F). In some embodiments, the opening OP of the mask M exposes a portion of the seed material layer 110 a. For example, the mask M exposes a portion of the second sub-layer 114 a. In some embodiments, the mask M may be formed of a photosensitive material. For example, the mask M may be a photoresist or a dry film (dry film).

Referring to fig. 1D, a conductive material 120' is filled into the opening OP of the mask M. In some embodiments, the conductive material 120' is formed on the portion of the second sub-layer 114a of the seed material 110a exposed by the opening OP of the mask M. In some embodiments, the conductive material 120' may be formed by a plating process. The plating process is, for example, electroplating, electroless plating, immersion plating, or the like. The conductive material 120' is, for example, copper, a copper alloy, or the like. In other words, the second sub-layer 114a of the seed material layer 110a and the conductive material 120' may be made of the same material. However, the present disclosure is not limited thereto. In some alternative embodiments, the second sub-layer 114a and the conductive material 120' may comprise different materials.

Referring to fig. 1D and 1E, the mask M is then removed to obtain a plurality of conductive patterns 120a on the seed material layer 110 a. In some embodiments, the mask M may be removed by a stripping process, an etching process, and/or a cleaning process. Since the conductive pattern 120a is formed by filling the conductive material 120' into the opening OP of the mask M, the conductive pattern 120a may have the same profile as the opening OP of the mask M.

Referring to fig. 1E and 1F, the seed material layer 110a is patterned to form a seed layer 110 b. As shown in fig. 1F, the seed layer 110b may be composed of a plurality of seed layer patterns corresponding to the conductive patterns 120 a. The patterning of the seed material layer 110a will be described below.

In some embodiments, the portion of the second sub-layer 114a exposed by the conductive pattern 120a is selectively removed by a first etching process. In some embodiments, the first etching process may include an anisotropic etching process such as dry etching or an isotropic etching process such as wet etching. In some embodiments, argon (Ar) gas, nitrogen (N)₂) Gas, oxygen (O)₂) Gas, tetrafluoromethane (CF)₄) Gases or combinations thereof may act as an etchant for dry etching. In some alternative embodiments, Hydrogen Fluoride (HF) solution, phosphoric acid (H, H) solution₃PO₄) Solution, hydrogen peroxide (H)₂O₂) Solution, ammonium hydroxide (NH)₄OH) solution or a combination thereof may be used as an etchant for wet etching. The first etch process removes portions of the second sub-layer 114a to form the second sub-layer 114 b. It should be noted that the etchants listed above are for illustrative purposes only, and that other types of etchants may also be used as etchants for etching the second sub-layer 114 a.

After removing a portion of the second sub-layer 114a, a portion of the first sub-layer 112a is exposed by the conductive pattern 120a and the remaining second sub-layer 114 b. The exposed portion of the first sub-layer 112a may be removed by a second etching process. In some embodiments, the first sub-layer 112a may be etched by a dry etching process or a wet etching process to obtain the first sub-layer 112 b. The etchant for removing the first sub-layer 112a may include a fluorine-based gas, such as tetrafluoromethane (CF)₄) Gas, trifluoromethane (CHF)₃) A gas, other suitable gas, or a combination thereof. In some alternative embodiments, the etchant used to remove the first sub-layer 112a may include a Hydrogen Fluoride (HF) solution or other suitable etching solution. It should be noted that the etchants listed above are for illustrative purposes only, and other types of etchants may also be used as the etchant for etching the first sub-layer 112 a.

In some embodiments, the conductive pattern 120a and the seed layer 110b (including the first sub-layer 112b and the second sub-layer 114b) may be collectively referred to as the conductive structure 100'. In other words, as shown in fig. 1F, the conductive structure 100' is formed on the peeling layer DB. In some embodiments, each conductive structure 100' includes a seed layer 110b attached to the release layer DB. For example, the seed layer 110b of the conductive structure 100' directly contacts the release layer DB.

Referring to fig. 1G, a plurality of dies 200 are placed on the peeling layer DB. In some embodiments, the die 200 is located between the conductive structures 100'. For example, the dies 200 are arranged in an array and surrounded by the conductive structure 100'. In some embodiments, each die 200 has a top surface 200a and a back surface 200b opposite the top surface 200 a. As shown in fig. 1G, the die 200 is placed with the top surface 200a facing upward and the back surface 200b facing the release layer DB. In some embodiments, the die 200 is placed on the release layer DB by a pick-and-place process. In some embodiments, each die 200 may be a memory die (i.e., a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a non-volatile random access memory (NVRAM), and/or the like), a logic die, a Radio Frequency (RF) die, or a processor die (i.e., an Accelerated Processor (AP), etc.). The aspect of each die 200 will be described below.

In some embodiments, each die 200 includes a semiconductor substrate 202, a plurality of conductive pads 204, a passivation layer 206, a plurality of vias 208, a passivation layer 210, and an amorphous layer (amorphous layer) 212. In some embodiments, the semiconductor substrate 202 may be a silicon substrate. In some alternative embodiments, the semiconductor substrate 202 may be made of: suitable elemental semiconductors, such as diamond or germanium; a suitable compound semiconductor such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor such as silicon germanium carbide (sic), gallium arsenic phosphide (gaas), or gallium indium phosphide (inp). In some embodiments, the semiconductor substrate 202 includes active components (e.g., transistors, etc.) and passive components (e.g., resistors, capacitors, inductors, etc.) formed in the semiconductor substrate 202.

In some embodiments, the conductive pads 204 are distributed on the semiconductor substrate 202. The conductive pads 204 may be aluminum pads, copper pads, or other suitable metal pads. A passivation layer 206 is formed on the semiconductor substrate 202 and has a contact opening that partially exposes the conductive pad 204. The passivation layer 206 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed from other suitable dielectric materials. In some embodiments, a post-passivation layer (not shown) may be further formed on the passivation layer 206. In addition, the via hole 208 is formed on the conductive pad 204. In some embodiments, the via hole 208 is plated on the conductive pad 204 such that the via hole 208 is electrically connected to the conductive pad 204. The via 208 may be a copper via or other suitable metal via. A protective layer 210 is formed on the passivation layer 206 to cover the via hole 208. In some embodiments, the protective layer 210 may be a Polybenzoxazole (PBO) layer, a Polyimide (PI) layer, or a layer made of other suitable polymers. In some alternative embodiments, the protective layer 210 may be made of an inorganic material.

In some embodiments, a thinning process is performed on each die 200 prior to placing the die 200 on the lift-off layer DB. For example, a back side grinding process may be performed on the back surface 200b of each die 200 to reduce the overall thickness of the die 200. During the thinning process, a portion of the semiconductor substrate 202 may be ground. The stresses generated during the grinding process may damage the crystal lattice of the portion of semiconductor substrate 202 on the ground surface, thereby forming amorphous layer 212 on back surface 200b of die 200. As shown in fig. 1G, the amorphous layer 212 is disposed on the semiconductor substrate 202 and opposite to the semiconductor pad 204. In some embodiments, amorphous layer 212 directly contacts semiconductor substrate 202 and covers semiconductor substrate 202. In some embodiments, when the semiconductor substrate 202 is a silicon substrate, the amorphous layer 212 may be an amorphous silicon layer. On the other hand, when the semiconductor substrate 202 includes other types of semiconductors, the amorphous layer 212 may be other types of amorphous semiconductor layers. In some embodiments, thickness T of amorphous layer 212₂₁₂Between about 1nm and about 300 nm. On the other hand, the thickness T of the die 200₂₀₀Between about 40 μm and about 250 μm. In some embodiments, thickness T of amorphous layer 212₂₁₂Thickness T to die 200₂₀₀Is between about 1:133.3 and about 1: 250000.

In some embodiments, the die 200 is adhered to the release layer DB by an adhesive layer AD. In some embodiments, the amorphous layer 212 on the back surface 200b of the die 200 is attached to the adhesion layer AD. For example, the amorphous layer 212 may directly contact the adhesion layer AD such that the adhesion layer AD is interposed between the amorphous layer 212 and the peeling layer DB. In some embodiments, the adhesive layer AD may include a Die Attach Film (DAF). However, the present disclosure is not limited thereto. In some alternative embodiments, other materials may be used as the adhesive layer AD, as long as the materials can enhance the adhesion between the die 20 and the release layer DB.

Referring to fig. 1H, an encapsulation material 300 'is formed on the peeling layer DB to encapsulate the conductive structure 100' and the die 200. In some embodiments, the encapsulant material 300' is a molding compound, molding underfill (molding underfill), resin (e.g., epoxy), or the like. The encapsulation material 300' may be formed by a molding process, such as a compression molding process. In some embodiments, the top surface 300a 'of the encapsulation material 300' is located at a higher level than the top surface 200a of the die 200 and the top surface 100a 'of the conductive structure 100'. In other words, the conductive structure 100 'and the protective layer 210 of each die 200 are not exposed but well protected by the encapsulation material 300'.

Referring to fig. 1H and 1I, the encapsulant 300 ' and the passivation layer 210 of the die 200 are polished until the top surface 100a ' of the conductive structure 100 ' and the top surface of the via 208 of the die 200 are exposed. After the grinding of the encapsulation material 300 ', the encapsulant 300 is formed on the release layer DB to encapsulate the conductive structure 100' and the die 200. Encapsulant 300 exposes at least a portion of each die 200 and at least a portion of each conductive structure 100'. In some embodiments, the encapsulant material 300' is abraded by mechanical abrasion, Chemical Mechanical Polishing (CMP), or other suitable mechanism. During the grinding process, a portion of the protection layer 210 is also ground to expose the via hole 208, thereby forming a protection layer 210 a. In some embodiments, during the polishing process of the encapsulant 300 'and the protection layer 210, portions of the conductive structure 100' and/or portions of the via 208 may also be slightly polished. After grinding, each die 200 has an active surface 200c opposite the back surface 200 b. The exposed portion of via 208 is located on active surface 200c of die 200. It should be noted that the top surface 100a 'of the conductive structure 100', the top surface 300a of the encapsulant 300, and the active surface 200c of the die 200 are substantially coplanar with one another.

Referring to fig. 1J, a redistribution structure 400 is formed on the conductive structure 100', the die 200, and the encapsulant 300. In some embodiments, the rerouting structure 400 is formed on the top surface 100a ' of the conductive structure 100 ', the active surface 200c of the die 200, and the top surface 300a of the encapsulant 300 to electrically connect the conductive structure 100 ' and the die 200. As shown in fig. 1J, the rerouting structure 400 includes a plurality of interlayer dielectric layers 400a and a plurality of rerouting conductive patterns 400b alternately stacked. The re-wiring conductive pattern 400b is electrically connected to the via hole 208 of the die 200 embedded in the encapsulation 300 and the conductive structure 100'. In some embodiments, the bottommost interlayer dielectric layer 400a partially covers the top surface of the via hole 208 and the top surface 100a 'of the conductive structure 100' to form a plurality of contact openings. The lowermost re-wiring conductive pattern 400b extends into the contact opening of the lowermost interlayer dielectric layer 400 to physically contact the top surface of the via 208 and the top surface 100a 'of the conductive structure 100'. As shown in fig. 1J, the topmost re-wiring conductive pattern 400b includes a plurality of pads. In some embodiments, the pads may include a plurality of under-ball metallurgy (UBM) patterns for ball mounting. In some alternative embodiments, the pad may further include a plurality of connection pads for mounting passive components.

In some embodiments, the material of the rerouting conductive pattern 400b includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. The rerouting conductive pattern 400b may be formed by, for example, plating, deposition and/or photolithography and etching. In some embodiments, the material of the interlayer dielectric layer 400a includes polyimide, epoxy, acrylic, phenolic, benzocyclobutene (BCB), Polybenzoxazole (PBO), or other suitable polymer-based dielectric material. The interlayer dielectric layer 400a may be formed by a suitable fabrication technique, such as spin-on coating (spin-on coating), Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and the like.

Referring to fig. 1K, after the re-routing structure 400 is formed, a plurality of conductive terminals 500 are placed on the topmost re-routing conductive pattern 400b (UBM pattern) of the re-routing structure 400. In some embodiments, the conductive terminals 500 comprise solder balls. In some embodiments, the conductive terminal 500 may be placed on the UBM pattern by a ball-planting process or other suitable process.

Referring to fig. 1K and 1L, after the conductive terminals 500 are formed on the redistribution structure 400, the carrier C is removed. In some embodiments, the removal of the carrier sheet C may be achieved by irradiating the release layer DB (e.g., LTHC release layer) with an Ultraviolet (UV) laser so that the carrier sheet C may be peeled off. During the peeling process, a portion of the peeling layer DB adheres to the carrier C and can be carried away by the carrier C. Meanwhile, another portion of the release layer DB remains on the adhesive layer AD, the encapsulant 300, and the conductive structure 100'. After removal of the carrier plate C, the structure is turned upside down so that the rear surface 200b of the die 200 faces upward. The inverted structure is placed on tape TP for further processing, as shown in FIG. 1L.

In some embodiments, the remaining exfoliation layer DB is removed to expose the conductive structure 100' for future electrical connection. In some embodiments, the adhesive layer AD has poor thermal conductivity, which may cause heat generated during operation of the die 200 to accumulate within the subsequently formed package 10 (shown in fig. 1R), thereby compromising the performance and lifetime of the subsequently formed package 10. Thus, in some embodiments, the adhesive layer AD may be removed to enhance the performance and lifetime of the subsequently formed package 10. In some embodiments, to further enhance adhesion between the conductive structure 100' and subsequently formed elements, the first sub-layer 112b of the seed layer 110b may be removed to expose the second sub-layer 114 b. In some embodiments, the removal of the release layer DB, the adhesion layer AD, and the first sub-layer 112b of the seed layer 110b may be achieved by a hybrid etching process (hybrid etching process) including a plurality of etching steps. For example, the hybrid etching process may include a wet etching process and a dry etching process performed before the wet etching process. The hybrid etch process will be discussed below in conjunction with fig. 1M through 1P.

Referring to fig. 1M and 1N, a dry etching process DE is performed on the structure shown in fig. 1M to remove the peeling layer DB and the adhesion layer AD. In some embodiments, the etchant of the dry etch process DE is free of fluorine compounds. For example, the etchant for the dry etching process DE does not contain tetrafluoromethane (CF)₄) A gas. On the other hand, the etchant for the dry etching process DE may include argon (Ar) gas, nitrogen (N)₂) Gas and/or oxygen (O)₂) A gas. It should be noted that the etchants listed above are for illustrative purposes only, and other gases may also be used as etchants for the dry etching process DE as long as no fluorine-containing compound is included. In some embodiments, the duration of the dry etching process DE is 10 seconds to 300 seconds. As shown in fig. 1N, the dry etching process DE does not remove the amorphous layer 212 located under the adhesion layer AD. That is, throughout the dry etch process DE, the semiconductor substrate 202 of each die 200 is covered by the amorphous layer 212. Accordingly, the amorphous layer 212 may function as a barrier layer (barrier layer) to prevent impurities generated during the dry etching process DE from damaging the semiconductor substrate 202 or diffusing into the semiconductor substrate 202, thereby ensuring reliability of the die 200.

As shown in fig. 1N, dry etching process DE removes adhesion layer AD to form recess R1 in encapsulant 300. In some embodiments, recess R1 exposes amorphous layer 212 of each die 200. Since amorphous layer 212 is located in recess R1, the surface of amorphous layer 212 (i.e., back surface 200b of die 200) is located at a different level than back surface 300b of encapsulant 300. For example, the surface of amorphous layer 212 may be located at a lower level than rear surface 300b of encapsulant 300. That is, the encapsulant 300 may have a thickness greater than a thickness of the die 200.

Referring to fig. 1O and 1P, after the dry etching process DE, a wet etching process WE is performed on the structure shown in fig. 1O to remove a portion of the seed layer 110 b. For example, the first sub-layer 112b of the seed layer 110b may be removed by a wet etching process WE. In some embodiments, the etchant of the wet etching process WE includes Hydrogen Fluoride (HF) solution, phosphoric acid (H)₃PO₄) Solution, hydrogen peroxide (H)₂O₂) Solution, ammonium hydroxide (NH)₄OH) solution or combinations thereof. It should be noted that the etchants listed above are for illustrative purposes only, and that other solutions may also be used as etchants for the wet etching process WE. As shown in fig. 1P, the exposed amorphous layer 212 is not removed by the wet etching process WE. That is, throughout the wet etch process WE, the semiconductor substrate 202 of each die 200 is covered by the amorphous layer 212. Accordingly, the amorphous layer 212 may act as a barrier layer to prevent metal impurities (e.g., copper or titanium in the seed layer 110 a) generated during the wet etching process WE from damaging the semiconductor substrate 202 or diffusing into the semiconductor substrate 202. Accordingly, a fin-in-copper problem of diffusion of copper compounds into the semiconductor substrate 202 may be eliminated, and reliability of the die 200 may be ensured.

As shown in fig. 1P, the package array 10a is obtained after performing the hybrid etching process. In some embodiments, amorphous layer 212 remains on back surface 200b of each die 200 to cover semiconductor substrate 202 after the hybrid etching process. As shown in fig. 1P, a wet etch process WE removes the first sub-layer 112b of the seed layer 110a to form a recess R2 in the encapsulant 300. In some embodiments, the groove R2 exposes the second sub-layer 114b of the seed layer 110 b. In some embodiments, the second sub-layer 114b of the seed layer 110b and the conductive pattern 120a constitute a plurality of conductive structures 100. Since the second sub-layer 114b of the seed layer 110b is located in the recess R2, the rear surface 100b of the conductive structure 100 is located at a different level than the rear surface 300b of the encapsulant 300. For example, the rear surface 100b of the conductive structure 100 may be located at a lower level than the rear surface 300b of the encapsulant 300. It should be noted that although the rear surface 100b of the conductive structure 100, the rear surface 200b of the die 200, and the rear surface 300b of the encapsulant 300 are shown at different levels, the present disclosure is not limited thereto. In some alternative embodiments, a portion of the encapsulant 300 may be removed to assume a different aspect during the hybrid etch process. Different aspects will be discussed below in conjunction with fig. 2A and 2B.

Fig. 2A is a schematic cross-sectional view of an intermediate stage of a manufacturing process of a package on package structure 1000 according to some alternative embodiments of the present disclosure. Referring to fig. 2A, a portion of the encapsulant 300 may be etched during the dry etch process DE and/or the wet etch process WE. Accordingly, the back surface 100b of the conductive structure 100 and/or the back surface 200b of the die 200 may be substantially coplanar with the back surface 300b of the encapsulant 300. That is, the thickness of encapsulant 300 may be substantially equal to the thickness of die 200.

Fig. 2B is a schematic cross-sectional view of an intermediate stage of a manufacturing process of a package on package structure 1000 according to some alternative embodiments of the present disclosure. Referring to fig. 2B, a portion of the encapsulant 300 may be etched during the dry etch process DE and/or the wet etch process WE. Accordingly, the rear surface 300b of the encapsulant 300 may be located at a different level than the rear surface 200b of the die 200 and the rear surface 100b of the conductive structure 100. For example, the back surface 300b of the encapsulant 300 may be located at a lower level than the back surface 200b of the die 200 and the back surface 100b of the conductive structure 100. That is, the encapsulant 300 may have a thickness less than the thickness of the die 200.

It should be noted that the steps shown in fig. 1M to 1P are merely exemplary of the hybrid etching process, and the disclosure is not limited thereto. In some alternative embodiments, the hybrid etching process may include different steps. Another exemplary hybrid etching process to remove the release layer DB, the adhesion layer AD, and the first sub-layer 112b of the seed layer 110b will be discussed below in conjunction with fig. 3A-3D.

Fig. 3A through 3D are schematic cross-sectional views of a hybrid etching process of a manufacturing process of a package on package structure 1000 according to some alternative embodiments of the present disclosure. Referring to fig. 3A and 3B, a dry etching process DE is performed on the structure shown in fig. 3A to remove the peeling layer DB to removeAnd a portion of seed layer 110 b. For example, the release layer DB and the first sub-layer 112b of the seed layer 110b may be removed by a dry etching process DE. In some embodiments, the etchant for the dry etch process DE comprises tetrafluoromethane (CF)₄) A gas. In some embodiments, the etchant for the dry etching process DE may further comprise argon (Ar) gas, nitrogen (N)₂) Gas and/or oxygen (O)₂) A gas. It should be noted that the etchants listed above are for illustrative purposes only, and other gases may also be used as etchants for the dry etching process DE. In some embodiments, the duration of the dry etching process DE is 10 seconds to 180 seconds. By controlling the duration of the dry etching process DE within the above range, the peeling layer DB and the first sub-layer 112b of the seed layer 110b may be sufficiently removed without completely removing the adhesion layer AD. In other words, throughout the dry etching process DE, the semiconductor substrate 202 and the amorphous layer 212 of each die 200 are covered by the adhesion layer AD. Accordingly, the adhesion layer AD and the amorphous layer 212 may act as a barrier layer to prevent metal impurities (e.g., copper or titanium in the seed layer 110 a) generated during the dry etching process DE from being redeposited or diffused into the semiconductor substrate 202. Accordingly, the problem of fin-type copper in which copper compounds diffuse into the semiconductor substrate 202 can be eliminated, and the reliability of the die 200 can be ensured.

Referring to fig. 3C and 3D, after the dry etching process DE, a wet etching process WE is performed on the structure shown in fig. 3C to remove the adhesion layer AD. In some embodiments, the etchant of the wet etching process WE includes Hydrogen Fluoride (HF) solution, phosphoric acid (H)₃PO₄) Solution, hydrogen peroxide (H)₂O₂) Solution, ammonium hydroxide (NH)₄OH) solution or combinations thereof. It should be noted that the etchants listed above are for illustrative purposes only, and that other solutions may also be used as etchants for the wet etching process WE. As shown in fig. 3D, amorphous layer 212 remains on back surface 200b of die 200 after wet etch process WE. That is, throughout the wet etch process WE, the semiconductor substrate 202 of each die 200 is covered by the amorphous layer 212. Thus, the amorphous layer 212 may act as a barrier layer to prevent impurities generated during the wet etch process WE from damaging the semiconductorThe conductor substrate 202 is either diffused into the semiconductor substrate 202, thereby ensuring the reliability of the die 200.

Referring back to fig. 1Q, after performing the hybrid etching process, a plurality of packages 20 are stacked on the package array 10 a. In some embodiments, the package array 10a has a two-sided terminal design to accommodate the package 20. The package 20 is, for example, an Integrated Circuit (IC) package. The package 20 is electrically connected to the package array 10a through a plurality of connection terminals 600 interposed between the package 20 and the package array 10 a. In some embodiments, the connection terminal 600 is a solder joint (solder joint) formed by a ball-planting process and/or a reflow process. It should be noted that fig. 1Q serves only as an exemplary illustration, and the present disclosure is not limited thereto. In some alternative embodiments, other electronic devices such as integrated fan-out (InFO) packages, memory devices, Ball Grid Array (BGA) packages, or wafers (wafers) may be stacked on the package array 10a in place of the package 20.

Referring to fig. 1R, the package array 10a is cut or singulated to form a plurality of packages 10 on which packages 20 are stacked. In some embodiments, the cutting process or singulation process generally involves cutting with a rotating blade or laser beam. In other words, the cutting or singulation process is, for example, a laser cutting process, a mechanical cutting process, or other suitable process. In some embodiments, the package 10 may be referred to as an integrated fan-out package. In some embodiments, the underfill 700 is formed to encapsulate the connection terminal 600. In some embodiments, at least a portion of the underfill 700 is located between the

packages

10 and 20. For example, underfill 700 may fill a gap between package 10 and package 20 such that underfill 700 directly contacts amorphous layer 212 of die 200. After the underfill 700 is formed, the package on package structure 1000 is obtained.

According to some embodiments of the present disclosure, a package on package (PoP) structure includes a first package and a second package stacked on the first package. The first package has a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a back surface opposite the active surface. The die includes an amorphous layer on the back surface. The conductive structure surrounds the die. The encapsulant encapsulates the die and the conductive structure. The rewiring structure is located on the active surface of the die and is electrically connected to the conductive structure and the die.

According to some embodiments of the present disclosure, the amorphous layer comprises an amorphous silicon layer.

According to some embodiments of the present disclosure, a ratio of a thickness of the amorphous layer to a thickness of the die is between about 1:133.3 and about 1: 250000.

According to some embodiments of the present disclosure, the amorphous layer has a thickness between about 1nm and about 300 nm.

According to some embodiments of the disclosure, a surface of the amorphous layer is substantially coplanar with a surface of the encapsulant.

According to some embodiments of the disclosure, a surface of the amorphous layer is located at a different level than a surface of the encapsulant.

According to some embodiments of the present disclosure, the package on package further includes a plurality of conductive terminals on the redistribution structure.

According to some embodiments of the present disclosure, the stack package further includes a plurality of connection terminals and an underfill. The plurality of connection terminals are interposed between the first package and the second package. The underfill encapsulates the plurality of connection terminals.

According to some embodiments of the present disclosure, the underfill directly contacts the amorphous layer.

According to some embodiments of the present disclosure, a method of manufacturing a package includes at least the following steps. A carrier plate is provided. A peeling layer is formed on the carrier plate. Forming a conductive structure on the peeling layer. The conductive structure includes a seed layer conforming to the release layer. A die is attached to the release layer by an adhesive layer. The die includes an amorphous layer attached to the bonding layer. And removing the carrier plate. The lift-off layer and the adhesion layer are removed to expose the amorphous layer. After removing the release layer and the adhesion layer, a portion of the seed layer is removed.

According to some embodiments of the present disclosure, removing the peeling layer and the adhesion layer includes performing a dry etching process.

According to some embodiments of the present disclosure, the etchant of the dry etch process is CF-free₄A gas.

According to some embodiments of the present disclosure, the etchant of the dry etching process includes argon (Ar) gas, nitrogen (N)₂) Gas, oxygen (O)₂) A gas or a combination thereof.

According to some embodiments of the present disclosure, the dry etching process has a duration of 10 seconds to 180 seconds.

According to some embodiments of the present disclosure, the method of manufacturing a package further comprises at least the following steps. Forming a redistribution structure on the die and the conductive structure. And forming a conductive terminal on the rewiring structure.

According to some embodiments of the present disclosure, a method of manufacturing a package includes at least the following steps. A carrier plate is provided. A peeling layer is formed on the carrier plate. Forming a conductive structure on the peeling layer. A die is attached to the release layer by an adhesive layer. The die includes a semiconductor substrate and an amorphous layer overlying the semiconductor substrate. The amorphous layer is attached to the bonding layer. Forming a redistribution structure on the die and the conductive structure. And removing the carrier plate. A dry etching process is performed to remove the lift-off layer. A wet etch process is performed to remove the adhesion layer, and the amorphous layer is left to cover the semiconductor substrate of the die after the wet etch process is performed.

According to some embodiments of the present disclosure, the conductive structure includes a seed layer conforming to the release layer, and performing the dry etching process further includes removing a portion of the seed layer.

According to some embodiments of the present disclosure, the etchant of the dry etching process comprises CF₄A gas.

According to some embodiments of the present disclosure, the method of manufacturing a package further comprises encapsulating the die and the conductive structure with an encapsulant.

According to some embodiments of the present disclosure, performing the wet etching process further includes removing a portion of the encapsulant.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A package on package structure, comprising:

a first package comprising:

a die having an active surface and a back surface opposite the active surface, wherein the die includes an amorphous layer on the back surface;

a plurality of conductive structures surrounding the die;

an encapsulant encapsulating the die and the plurality of conductive structures; and

a rewiring structure on the active surface of the die, wherein the rewiring structure is electrically connected to the plurality of conductive structures and the die; and

a second package stacked on the first package.