CN109860019A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN109860019A
CN109860019A CN201810589182.9A CN201810589182A CN109860019A CN 109860019 A CN109860019 A CN 109860019A CN 201810589182 A CN201810589182 A CN 201810589182A CN 109860019 A CN109860019 A CN 109860019A
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layer
interface layer
interface
dielectric constant
high dielectric
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张志宇
张翔笔
方子韦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置的制造方法包含在半导体基板上形成通道区域。在通道区域上形成介面层。使用三甲基铝(TMA)处理介面层。在使用TMA处理介面层之后在介面层上形成高介电常数(高介电常数)介电质层。在高介电常数介电质层上形成栅极。使用TMA处理介面层和形成高介电常数介电质层是在同一腔室中进行。在使用TMA处理介面层之前退火介面层。退火介面层和使用TMA处理介面层是在不同的腔室中进行。

Description

半导体装置的制造方法
技术领域
本揭示涉及一种半导体装置的制造方法。
背景技术
使用有意生长的介面层(interfacial layer,IL)以便在通道区域和栅极绝缘体之间配置良好的介面，特别是使用高介电常数(高介电常数)介电质(例如二氧化铪(HfO2)、硅酸铪(HfSiO4)、二氧化锆(ZrO2)、硅酸锆(ZrSiO4)等)，并以抑制金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistors,MOSFET)中通道载子迁移率的降低。
然而，当通道区域含有硅锗时，介面层的形成常常会导致介面层表面上的悬键。悬键会降低通道区域的电子迁移率。去除悬键的方法之一是在通道区域上磊晶生长覆盖层。然而附加的覆盖层会增加通道区域的厚度，并使元件的尺寸必须因此妥协。
发明内容
本揭露内容的一态样提供一种制造半导体装置的方法，包含下列步骤：形成通道区域于半导体基板上；形成介面层于通道区域上；使用三甲基铝处理介面层；在使用三甲基铝处理介面层之后，在介面层上形成一高介电常数介电质层；以及形成栅极于高介电常数介电质层上。
附图说明
当结合附图阅读时，根据以下详细描述可以最好地理解本揭露的各方面。应注意，根据业界的标准惯例，各种特征并未按比例绘制。实际上，为了清楚讨论，各种特征的尺寸可以任意增加或减小。
图1绘示根据本揭露的部分实施例中制造半导体装置的方法的流程图；
图2至图18是根据本揭露的部分实施例中在替换栅极堆叠形成制程中处于不同阶段的部分的半导体装置的横截面图；以及
图19A至图19D是根据本揭露的部分实施例中介面层处理制程中部分的半导体装置的横截面图。
具体实施方式
以下公开提供了用于实现所提供的主题的不同特征的许多不同实施例或示例。以下描述组件和布置的具体示例以简化本揭露。当然，这些仅仅是示例，并不意在限制。例如，在下面的描述中，在第二特征上方或之上形成第一特征可以包含其中第一特征和第二特征形成为直接接触的实施例，并且还可以包含其中可以在第一特征和第二特征之间形成额外特征，使得第一特征和第二特征可以不直接接触。另外，本揭露可以在各种示例中重复附图标记和/或文字。这种重复是为了简单和清楚的目的，并且本身并不指定所讨论的各种实施例和/或配置之间的关系。
此外，为了便于描述，在此可以使用例如“在...之下”、“在...下方”、“低于”、“在...之上”、“高于”等等的空间相对术语来描述一个元件或特征与如附图所示的另一个元件或特征的关系。除了附图中描绘的方向之外，空间相对术语旨在涵盖使用或操作中的装置的不同方位。此装置可以以其他方式定向(旋转90度或在其他方位)并且同样可以相应地解释这里使用的空间相关描述符号。
鳍片可以透过任何合适的方法来图案化。例如，可以使用一种或多种光刻制程(包括双重图案化或多重图案化制程)来图案化鳍片。通常，双重图案化或多重图案化制程结合了光刻和自对准制程，从而允许创建具有例如比使用单一直接光刻制程可获得的间距小的间距的图案。例如，在一个实施例中，在基板上方形成牺牲层并使用光刻制程进行图案化。使用自对准制程沿着图案化的牺牲层形成间隔物。然后移除牺牲层，接着可以使用其余的间隔物来图案化鳍片。
根据各种示例性实施例提供了一种金属氧化物半导体(metal-oxide-semiconductor,MOS)装置及其形成方法。绘示了形成金属氧化物半导体装置的中间阶段。讨论实施例的变化。在各种视图和说明性实施例中，相同的附图标记用于表示相同的元件。
参照图1，其是根据本揭露的部分实施例中制造半导体装置的方法100的流程图。此方法从操作110开始，其中在半导体基板上形成通道区域。此方法继续进行操作120，其中在通道区域上形成介面层。随后，执行操作130，使用三甲基铝(trimethyl aluminium,TMA)处理介面层。此方法继续操作140，其中在使用三甲基铝处理介面层之后在介面层上形成高介电常数介电质层。此方法继续进行操作150，其中在高介电常数介电质层上形成栅极。下面的讨论示出了可以根据图1的方法100制造的半导体装置的实施例。虽然方法100在下面被图示和描述为一系列步骤或事件，但是应该理解，所示出的这些步骤或事件的顺序不应被解释为限制意义。例如，一些步骤可以以不同的顺序发生和/或与除本文所示和/或描述的那些之外的其他步骤或事件同时发生。另外，并非所有示出的步骤都需要以实施本文描述的一个或多个方面或实施例。此外，这里描述的一个或多个步骤可以在一个或多个单独的步骤和/或阶段中执行。
图2至图12是根据一些示例性实施例中形成金属氧化物半导体装置的中间阶段的横截面图。请参考图2提供了包括半导体基板20的晶片10。硅锗(Si1-xGex)层202形成在半导体基板20上，并且x的范围在约0.15和约0.95之间。在x小于0.15的情况下，得到的硅锗层的锗含量太低因此会产生不利的影响。在部分实施例中，x可以高于0.95，并且它表示所得硅锗中GeOx的高比例。Si1-xGex层202磊晶生长在半导体基板20的表面上。锗具有比硅更高的晶格常数，因此所得到的Si1-xGex层202的晶格结构允许比半导体基板20更高的电子空穴迁移率(electron hole mobility)。浅沟槽隔离(shallow trench isolation,STI)区域(未绘示)形成在Si1-xGex层202中并用于限定金属氧化物半导体装置的主动区域(activeregions)。
请继续参考图2在Si1-xGex层202上方形成虚设栅极堆叠22。虚设栅极堆叠22包括虚设栅极介电质24和虚设栅极26。虚设栅极介电质24在一些示例性实施例中包括氧化硅。在其他实施例中，也可使用例如氮化硅、碳化硅、或其相似物等的其他材料。虚设栅极26可以包括多晶硅。在部分实施例中，虚设栅极堆叠22进一步包括在虚设栅极26上方的硬掩模28。例如，硬掩模28可以包括例如氮化硅，然而也可以使用例如碳化硅、氮氧化硅、或其相似物等的其它材料。在部分的实施例中，不形成硬掩模28。虚设栅极堆叠22在Si1-xGex层202中限定通道区域32。源极和漏极区域(以下称为源极/漏极区域)38(图3)随后形成在通道区域32的相对侧上。
请继续参考图2。例如透过将p型杂质(例如硼和/或铟)注入到Si1-xGex层202中以形成轻掺杂源极和漏极(lightly-doped source and drain,LDD)区域30。例如，当金属氧化物半导体装置是p型金属氧化物半导体(pMOS)装置时，轻掺杂源极和漏极区域30是p型区域。虚设栅极堆叠22用作注入掩模，使得轻掺杂源极和漏极区域30的边缘与虚设栅极堆叠22的边缘大致对齐。
参考图3。在虚设栅极堆叠22的侧壁上形成栅极间隔物34。在部分实施例中，每个栅极间隔物34包括氮氧化硅层和氧化硅层。在其他实施例中，栅极间隔物34包括一层或多层，每个层包括氧化硅、氮化硅、氮氧化硅和/或其他介电质材料。栅极间隔物34的形成方法包括但不限于等离子辅助化学气相沉积(plasma enhanced chemical vapor deposition,PECVD)、低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)、次大气压化学气相沉积(sub-atmospheric chemical vapor deposition,SACVD)和其他沉积方法。
请继续参考图3。在Si1-xGex层202中形成源极/漏极区域38。在其中金属氧化物半导体装置是p型金属氧化物半导体装置的实施例中，源极/漏极区域38是p型。在部分实施例中，在Si1-xGex层202中形成源极/漏极应力源(source/drain stressors)。源极/漏极应力源形成源极/漏极区域38的至少一部分。图3绘示了其中源极/漏极区域38完全重叠各自的源极/漏极应力源。
在金属氧化物半导体装置是p型金属氧化物半导体装置的部分实施例中，源极/漏极应力源可以包括合适的掺杂剂。可以透过蚀刻Si1-xGex层202和半导体基板20以在其中形成凹陷，然后执行磊晶以在凹陷中生长源极/漏极应力源来形成源极/漏极应力源。
请参考图4。在虚设栅极堆叠22和源极/漏极区域38之上形成接触蚀刻停止层(contact etch stop layer,CESL)40。在部分实施例中，接触蚀刻停止层40包括氮化硅、碳化硅或其他介电质材料。在接触蚀刻停止层40上方形成层间介电质(interlayerdielectric,ILD)层42。层间介电质层42毯式地形成到高于虚设栅极堆叠22的顶面的高度。层间介电质层42可包括使用例如可流动化学气相沉积(lowable chemical vapordeposition,FCVD)形成的可流动氧化物。层间介电质层42也可以是使用旋转涂布形成的旋涂玻璃。例如，层间介电质层42可以包括磷硅酸盐玻璃(phospho-silicate glass,PSG)、硼硅酸盐玻璃(boro-silicate glass,BSG)、硼掺杂磷硅酸盐玻璃(boron-doped phospho-silicate glass,BPSG)、四乙氧基硅烷(tetraethyl orthosilicate,TEOS)氧化物、氮化钛(TiN)、碳氧化硅(SiOC)或其他低介电常数多孔介电质材料。
请参考图5。图5绘示使用例如化学机械平坦化(chemical mechanical polish,CMP)进行的平坦化步骤。执行化学机械平坦化以移除层间介电质层42和接触蚀刻停止层40的多余部分。移除硬掩模28顶表面上方的多余部分。因此，暴露虚设栅极堆叠22。在另外的实施例中，在化学机械平坦化期间移除硬掩模28，其中化学机械平坦化停止于虚设栅极26的顶表面上。
请参考图6。接着，移除虚设栅极堆叠22。移除虚设栅极堆叠22的结果为形成凹槽44，其中所得的结构绘示于图6中。移除虚设栅极堆叠22暴露了下面的Si1-xGex层202。
图7至图12绘示替代栅极堆叠的形成。请参考图7。在通道区域32上形成介面层52。使用介面层52以便在Si1-xGex层202和栅极绝缘体之间配置良好的介面，特别是使用高介电常数介电质(例如二氧化铪(HfO2)、硅酸铪(HfSiO4)、二氧化锆(ZrO2)、硅酸锆(ZrSiO4)等)，以抑制金属氧化物半导体场效应晶体管(MOSFET)的通道载子的迁移率的降低。透过稀释的氢氟酸、标准清洁1(Standard Clean 1,SC1)和标准清洁2(Standard Clean 1,SC2)、等离子氧化、臭氧化去离子水处理、快速热氧化(rapid thermal oxidation,RTO)、或其类似物等制备的化学氧化物可在替代栅极堆叠时用于形成介面层52。例如，臭氧化的氧化物可以透过以气相或预先溶解在去离子(de-ionized,DI)水中的高臭氧气体生长。在部分实施例中，介面层52与通道区域32接触。
在Si1-xGex层202氧化之后，在通道区域32的表面上形成介面层52的薄膜。介面层52包括氧化硅(SiOy，其中y大于0)和氧化锗(GeOy，其中y大于0的)。由氧化处理产生的介面层52中的氧化锗的比例高度依赖于半导体基板20上的Si1-xGex层202中的锗含量。Si1-xGex层202中锗的含量越高，则介面层52中氧化锗的含量也越高。Si1-xGex层202中锗的含量越低，则介面层52中氧化锗的含量也越低。氧化锗对于形成在Si1-xGex通道区域上的介面层的品质是有害的。带电的介面状态的增加证明了对通道区域的危害。对通道区域的危害也可由随着介面层中氧化锗的含量的增加而导致的迁移率降低来证明。因此，本揭露描述了用于从介面层52清除或去除氧化锗的方法，其包括形成在Si1-xGex层202上的氧化锗和氧化硅。在部分实施例中，氧化锗实质上从介面层52中移除，而留下氧化硅。在其他实施例中，在清除步骤之后，残留的氧化锗例如小于5％。
参考图8。下面描述透过清除步骤从介面层52除去氧化锗。未标号的箭头表示对晶片10的热退火处理。清除步骤的第一阶段透过在约500℃至约900℃的温度下加热晶片10约1分钟来进行。如果加热温度低于500℃，则不能从介面层52完全除去氧化锗。如果加热温度高于900℃，则可能发生源极和漏极劣化或介面粗糙。此热退火在约1托(Torr)至约760托的气压中进行。热退火处理在基本上无氧的条件且具有例如氮气(N2)的惰性气体的情况下进行以防止氧化。清除步骤是有效的，因为氧化锗中的锗-氧键比氧化硅中的硅-氧键和Si1- xGex层202中的硅-锗键弱得多。因此，氧化锗容易被除去，留下氧化硅保留在位于Si1-xGex层202上的介面层52a内。清除步骤的第一阶段在晶片10转移到原子层沉积(atomic layerdeposition,ALD)反应室之前去除介面层52中大部分的氧化锗。
请参考图9。从介面层52a中去除氧化锗持续到第二阶段。未标号的箭头显示了对晶片10原位的三甲基铝(TMA)预处理。在基本上无氧的条件下进行三甲基铝预处理。在氧化锗清除步骤的第一阶段之后，将晶片10转移到原子层沉积反应室(未绘示)，以准备沉积高介电常数介电质层。在沉积高介电常数介电质层之前，晶片10在原子层沉积反应室中经历三甲基铝预处理。三甲基铝是强还原剂，并且提供三甲基铝的前驱物约30秒。三甲基铝预处理在约150℃至约300℃的温度下进行。这种三甲基铝预处理是在透过原子层沉积沉积高介电常数介电质层之前的连续制程，并且三甲基铝预处理的反应条件类似于高介电常数介电质层沉积的原子层沉积的反应条件。三甲基铝前驱物的流量在约200每分钟标准毫升数(standard cubic centimeter per minute,sccm)至约600sccm的范围内。低于200sccm的流量可能导致氧化锗的不完全去除。根据流量选择气压。在部分实施例中，在三甲基铝预处理期间的气压在约1托至约25托的范围内。接着，透过三甲基铝预处理去除介面层52a中剩余的氧化锗。在部分实施例中，在不同的腔室中进行热退火处理和三甲基铝预处理。
请参考图19A至图19D，其绘示氧化锗清除步骤的示意图。如图19A所示，形成硅锗(Si1-xGex)层202。透过图19B所示的氧化步骤，在Si1-xGex层202上形成介面层52。介面层52包括氧化硅和氧化锗，并且氧化硅和氧化锗的含量取决于Si1-xGex层202的硅锗比率。如图19C所示，未标号的箭头表示清除氧化锗的第一阶段，其中热退火处理中断锗和氧的键结，以将氧化锗从介面层52中移除。氧化硅仍为介面层52a的成分。如图19D所示，接着进行三甲基铝预处理以从介面层52a去除剩余的氧化锗。三甲基铝预处理是在高介电常数介电质层原子层沉积制程中原位进行的。不需要将晶片10移动到不同的腔室以进行三甲基铝预处理，这将简化了制造过程。介面层52的厚度保持相对地不变。
请参考图10。在部分实施例中，在沉积高介电常数介电质层之前，执行原位氮化处理。氮化处理在原子层沉积反应室中进行。未编号的箭头显示氮化过程。透过包括热退火和三甲基铝预处理的两阶段清除步骤除去氧化锗。透过用含氮试剂进行氮化处理，将介面层52b的剩余氧化硅转化为氮氧化硅(SiOaNb)，其中a和b皆大于0。氮化处理包括例如在等离子辅助原子层沉积(plasma enhanced atomic layer deposition,PEALD)的氨(NH3)等离子中约5秒至30秒，在等离子辅助原子层沉积的氮(N2)等离子中约5秒至30秒，或者在氨(NH3)气体在约300℃至500℃的等离子辅助原子层沉积中退火约1分钟。如果等离子处理的持续时间短于5秒，则氮化效果可能不足，导致后续制程中形成氧化锗。如果等离子处理的持续时间长于30秒，则等离子的强度可能会损坏介面层52b。如果氨(NH3)气体退火的温度低于300℃，则可能不会在介面层52b上发生氮化，并且此持续时间将允许足够的氮氧化硅的形成。此氮化处理进一步防止Si1-xGex层202的锗向外扩散。然后，介面层52c便是含氮层，例如是覆盖Si1-xGex层202的通道区域32的氮氧化硅层。
在部分实施例中，氮化处理可以延伸到介面层52c与Si1-xGex层202之间的介面。这防止了Si1-xGex层202的锗向外扩散。这也避免了介面层52c具有未处理的部分。此未处理部分会增加栅极堆叠的等效氧化物厚度(effective oxide thickness,EOT)，导致装置的栅极控制能力较低。在部分实施例中，氮化的介面层52c在其中包含氮，并且氮化的介面层52c的厚度在约5埃至约10埃的范围内。如果氮化的介面层52c的厚度小于约5埃，则氮化的介面层52c可能不够厚以防止Si1-xGex层202的锗向外扩散，导致在随后的制程中形成氧化锗。另一方面，如果氮化介面层52c大于约10埃，则栅极堆叠的等效氧化物厚度可能太厚，导致装置的栅极控制能力较低。
在部分实施例中，在氮化处理期间，半导体基板20的温度在约300℃至约1000℃的范围内。如果在氮化处理期间半导体基板20的温度低于约300℃，则氮化效果可能不足，导致在后续制程中形成氧化锗。如果半导体基板20的温度大于约1000℃，则氮化处理可能会影响下面的Si1-xGex层202，导致栅极堆叠的等效氧化物厚度增加，这将导致装置的栅极控制能力较低。
在部分实施例中，氮化处理的等离子功率在约50瓦(w)至约650瓦的范围内。如果氮化处理的等离子功率低于约50瓦，则氮化效果可能不足，导致在后续制程中形成氧化锗。如果氮化处理的等离子功率大于约650瓦，则氮化处理可能影响下面的Si1-xGex层202，导致栅极堆叠的等效氧化物厚度增加，这将导致装置的栅极控制能力较低。
请参考图11。形成高介电常数介电质层54。高介电常数介电质层54包括例如氧化铪、氧化镧、氧化铝等的高介电常数介电质材料。高介电常数介电质材料的介电常数(k值)高于3.9，并且可能高于约7，有时高达21或更高。高介电常数介电质层54覆盖介面层52c。在原子层沉积反应室中形成高介电常数介电质层54。功函数金属层62形成在高介电常数介电质层54上。根据部分实施例，功函数金属层62可以包括钛铝(TiAl)。在部分实施例中，在功函数金属层62和高介电常数介电质层54之间插入隔离层(未绘示)。隔离层可以包括氮化钛(TiN)、氮化钽(TaN)或其复合物。例如，隔离层可以包括氮化钛层(隔离层的下部)和在氮化钛层上的氮化钽层(隔离层的上部)。
请继续参考图11。在部分实施例中，随后形成的金属层可以包括阻挡层(未绘示)、润湿层(未绘示)和金属栅极64。阻挡层可以包括氮化钛，并且润湿层可以是钴层。金属栅极64可以包括钨、钨合金、铝、铝合金等。
参考图12，绘示平坦化步骤。平坦化步骤可以是例如使用化学机械平坦化以去除位于层间介电质层42上方的多余的高介电常数介电质层54、功函数金属层62和金属栅极64。介面层52c、高介电常数介电质层54、功函数金属层62和金属栅极形成替代栅极堆叠72。
替代栅极堆叠72具有位于高介电常数介电质层54和Si1-xGex层202之间的含氮介面层52c。介面层52c经历热退火和三甲基铝预处理并且进一步进行氮化处理。这些制程确保氧化锗从介面层52c中脱附，并且因此在介面层52c和Si1-xGex层202之间的介面处保持较低的介面能态密度(interface state density,Dit)。较低的介面能态密度较不可能使开关切换曲线变平坦并允许在通道区域具有较高的电子迁移率。可以省略处理Si1-xGex层202表面的磊晶制程，因为一系列介面层处理已使其上的悬键最小化。如果在通道区域上不添加磊晶盖，则可以实现通道体的缩小，特别是在例如超薄体绝缘体上硅锗(SiliconGermanium on Insulator,SiGe-OI)场效应晶体管(Field Effect Transistor,FET)、鳍式场效应晶体管(FinFET)、纳米线场效应晶体管等的装置中。
图13至图15绘示在部分实施例中替代栅极堆叠的形成。请参考图13，图13绘示高介电常数钝化层82的形成。在如图2至图6所示的移除虚设栅极堆叠22并且形成凹槽44之后，介面层52经过一系列处理，包括热退火和原位三甲基铝预处理，如图7至图9所示。当在高介电常数介电质层沉积之前并在将三甲基铝前驱物引入反应室时，晶片10位于原子层沉积反应室中。在退火和三甲基铝预处理之后，氧化锗已从介面层52b中去除，留下氧化硅作为介面层52b中的关键组分。在部分实施例中，在此过程中省略介面层的氮化。或者，在经过热退火和三甲基铝预处理的介面层52b上形成高介电常数钝化层82。
在同一原子层沉积反应室中，在高介电常数介电质层沉积之前，透过原子层沉积形成高介电常数钝化层82。高介电常数钝化层82与替代栅极凹槽44一致，其中栅极间隔物34的侧壁和介面层52b的顶表面因此被覆盖。高介电常数钝化层82与介面层52b反应。因此，高介电常数钝化层82在其底部包括例如高介电常数硅酸盐、锗酸盐或其组合。随着与介面层52b的距离的增加，高介电常数钝化层82中的高介电常数硅酸盐或锗酸盐的浓度减小。高介电常数钝化层82中的高介电常数材料的实例可以是氧化铝(Al2O3)、氧化镧(La2O3)、氧化钇(Y3O3)或其组合。此高介电常数钝化层82可防止Si1-xGex层202的锗向外扩散。高介电常数钝化层82的厚度可以在约5埃和10埃之间的范围内。
在部分实施例中，高介电常数钝化层82的厚度在从大约5埃到大约10埃的范围内。如果高介电常数钝化层82的厚度小于约5埃，则高介电常数钝化层82可能不够厚以防止Si1-xGex层202的锗向外扩散，导致在随后的过程中形成氧化锗。如果高介电常数钝化层82的厚度大于约10埃，则栅极堆叠的等效氧化物厚度(EOT)可能太厚，导致装置的栅极控制能力较低。
请参考图14。高介电常数介电质层54形成在高介电常数钝化层82上。高介电常数介电质层54包括高介电常数介电质材料，例如氧化铪、氧化镧、氧化铝或其相似物等。在原子层沉积反应室中执行高介电常数介电质层54的形成。高介电常数钝化层82插入在高介电常数介电质层54和介面层52b之间。与图11中所示的实施例不同，由于插入高介电常数钝化层82，因此高介电常数介电质层54与介面层52b间隔开。形成功函数金属层62于高介电常数介电质层54上。根据部分实施例，功函数金属层62可以包括钛铝(TiAl)。
请继续参考图14。在部分实施例中，随后形成的金属层可以包括阻挡层(未绘示)、润湿层(未绘示)和金属栅极64。阻挡层可以包括氮化钛(TiN)，并且润湿层可以是钴层。金属栅极64可以包括钨、钨合金、铝、铝合金，或其相似物等。
请参考图15，其绘示平坦化步骤。平坦化步骤可以例如是使用化学机械平坦化以移除位于层间介电质层42上的高介电常数钝化层82、高介电常数介电质层54、功函数金属层62和金属栅极64的多余部分。介面层52b、高介电常数钝化层82、高介电常数介电质层54、功函数金属层62和金属栅极64形成替代栅极堆叠92。
替代栅极堆叠92具有介于介面层52b和高介电常数介电质层54之间的高介电常数钝化层82。介面层52b经历热退火和三甲基铝预处理以去除其上的悬键，并且高介电常数钝化层82防止锗从Si1-xGex层202向外扩散。这些制程确保无锗氧化物的介面层52b，并且来自Si1-xGex层202的锗被限制在其内。较低的介面能态密度(Dit)因此可以保持在介面层52b和Si1-xGex层202之间的介面处。较低的介面能态密度(Dit)较不可能使开关切换曲线变平坦并且允许在通道区域处具有较高的电子迁移率。即使在通道区域上没有添加磊晶盖，氧化锗已被去除，并且剩余的自由锗也不会扩散出Si1-xGex层202。
请参考图16。在部分实施例中，在进行原位氮化处理(参见图10)之后，高介电常数钝化层82形成在是氧氮化硅层的介面层52c上。在原子层沉积反应室中进行高介电常数钝化层82的形成。介面层52c覆盖通道区域32，并且高介电常数钝化层82覆盖介面层52c。高介电常数钝化层82与替换栅极凹槽44一致，其中栅极间隔物34的侧壁和介面层52c的顶表面因此被覆盖。高介电常数钝化层82与介面层52c反应。因此，高介电常数钝化层82在其覆盖介面层52c的底部中包含例如高介电常数硅酸盐、锗酸盐或其组合。随着与介面层52c的距离的增加，高介电常数钝化层82中的高介电常数硅酸盐或锗酸盐的浓度降低。高介电常数钝化层82中的高介电常数材料的实例可以是氧化铝(Al2O3)、氧化镧(La2O3)、氧化钇(Y3O3)或其组合。此高介电常数钝化层82防止Si1-xGex层202的锗向外扩散。高介电常数钝化层82的厚度可以在约5埃和10埃之间的范围内。
请参考图17。形成高介电常数介电质层54。高介电常数介电质层54包括例如氧化铪、氧化镧、氧化铝或其相似物等的高介电常数介电质材料。在原子层沉积反应室中执行高介电常数介电质层54的形成。高介电常数介电质材料的介电常数(k值)高于3.9，并且可能高于约7，有时高达21或更高。高介电常数介电质层54覆盖高介电常数钝化层82。功函数金属层62形成在高介电常数介电质层54上。根据部分实施例，功函数金属层62可以包括钛铝(TiAl)。在部分实施例中，在功函数金属层62和高介电常数介电质层54之间插入隔离层(未绘示)。隔离层可以包括氮化钛(TiN)、氮化钽(TaN)或其复合物。例如，例如，隔离层可以包括氮化钛层(隔离层的下部)和在氮化钛层上的氮化钽层(隔离层的上部)。
请参考图17。在部分实施例中，随后形成的金属层可以包括阻挡层(未绘示)、润湿层(未绘示)和金属栅极64。阻挡层可以包括氮化钛(TiN)，并且润湿层可以是钴层。金属栅极64可以包括钨、钨合金、铝、铝合金，或其相似物。
请参考图18，此图绘示平坦化步骤。平坦化步骤可以是例如化学机械平坦化，以用于移除位于层间介电质层42上的高介电常数钝化层82、高介电常数介电质层54、功函数金属层62和金属栅极64的多余部分。介面层52c、高介电常数钝化层82、高介电常数介电质层54、功函数金属层62和金属栅极64形成替代栅极堆叠92。
替代栅极堆叠92具有含氮介面层52c和介于介面层52c和高介电常数介电质层54之间的高介电常数钝化层82。介面层52c经历热退火和三甲基铝预处理，以便去除其上的悬键。介面层52c防止锗从Si1-xGex层202向外扩散，并且高介电常数钝化层82是防止锗向外扩散的第二阻挡层。由于介面层52c和高介电常数钝化层82，剩余的锗牢固地固定在Si1-xGex层202中。因此可以在介面层52c和Si1-xGex层202之间的介面处保持较低的介面能态密度(Dit)。较低的介面能态密度(Dit)较不可能使开关切换曲线变平坦并且允许在通道区域32处具有较高的电子迁移率。
在介面层形成之后，首先对介面层进行退火以除去氧化锗。随后，进行涉及在介面层上使用三甲基铝前驱物的三甲基铝预处理。三甲基铝预处理进一步从介面层中去除剩余的氧化锗。接着，介面层可以经历氮化以形成氮氧化硅层。或者，可以在介面层上形成高介电常数钝化层。氮化过程或高介电常数钝化层防止锗从Si1-xGex层向外扩散。由于去除了氧化锗并且阻碍了锗外扩散，因此可以在介面层和Si1-xGex层之间的介面处实现较低的介面能态密度(Dit)，因而使通道区具有更高的电子迁移率。
在部分实施例中，一种方法包括在半导体基板上形成通道区域。在通道区域上形成介面层。使用三甲基铝(TMA)处理介面层。在使用三甲基铝处理介面层之后在介面层上形成高介电常数介电质层。在高介电常数介电质层上形成栅极。
在部分实施例中，使用三甲基铝处理介面层和形成高介电常数介电质层是在同一腔室中进行。
在一些实施方案中，此方法还包含在使用三甲基铝处理介面层之前退火介面层。
在部分实施方案中，退火介面层和使用三甲基铝处理介面层是在不同的腔室中进行。
在部分实施例中，此方法还包含在形成高介电常数介电质层之前用含氮试剂处理介面层。
在部分实施例中，用含氮试剂处理介面层是在使用三甲基铝处理介面层之后进行的。
在部分实施例中，此方法还包含在形成高介电常数介电质层之前在介面层上形成高介电常数钝化层，其中高介电常数钝化层包括高介电常数硅酸盐、高介电常数锗酸盐，或其组合。
在部分实施例中，高介电常数钝化层包括氧化铝(Al2O3)、氧化镧(La2O3)、氧化钇(Y3O3)或其组合。
在部分实施例中，在使用三甲基铝处理介面层之后形成高介电常数钝化层。
在部分实施例中，通道区域包括硅锗。
在一些实施方式中，使用三甲基铝处理介面层是在基本上无氧的条件下进行。
在部分实施例中，一种方法包括在半导体基板上形成通道区域。在通道区域上形成介面层。高介电常数钝化层形成在介面层上。高介电常数钝化层包括高介电常数硅酸盐、高介电常数锗酸盐或其组合。高介电常数介电质层形成在高介电常数钝化层上。在高介电常数介电质层上形成栅极。
在部分实施例中，此方法还包含在形成高介电常数钝化层之前在介面层上执行氮化制程。
在部分实施例中，氮化制程包括氨(NH3)等离子处理、氮(N2)等离子处理、氨(NH3)气退火或其组合。
在部分实施例中，此方法还包含在形成高介电常数钝化层之前退火介面层。
在部分实施例中，介面层的退火是在基本上无氧的条件下进行。
在部分实施例中，装置具有半导体基板，此半导体基板包括通道区域、在通道区域上的介面层、以及在介面层上的高介电常数钝化层。高介电常数钝化层包括高介电常数硅酸盐、高介电常数锗酸盐或其组合。高介电常数介电质层设置在高介电常数钝化层上。金属栅极设置在高介电常数介电质层上。
在部分实施例中，介面层包括氮氧化硅。
在部分实施例中，高介电常数钝化层包括氧化铝(Al2O3)、氧化镧(La2O3)、氧化钇(Y3O3)或其组合。
在部分实施例中，介面层与通道区域接触。
以上概述了若干实施例的特征，以便本领域技术人员可以更好地理解本揭露的各方面。本领域的技术人员应该理解，他们可以容易地使用本揭露作为用于设计或修改用于实现相同目的和/或实现本文介绍的实施例的相同优点的其他过程和结构的基础。本领域技术人员还应该认识到，这样的等同构造不脱离本揭露的精神和范围，并且可以在不脱离本揭露的精神和范围的情况下进行各种改变、替换和变更。

Claims (1)

1.一种半导体装置的制造方法，其特征在于，包含：
形成一通道区域于一半导体基板上；
形成一介面层于该通道区域上；
使用三甲基铝处理该介面层；
在使用三甲基铝处理该介面层之后，在该介面层上形成一高介电常数介电质层；以及
形成一栅极于该高介电常数介电质层上。
CN201810589182.9A 2017-11-30 2018-06-08 半导体装置的制造方法 Pending CN109860019A (zh)

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Application publication date: 20190607