TW201926461A - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

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TW201926461A
TW201926461A TW107120829A TW107120829A TW201926461A TW 201926461 A TW201926461 A TW 201926461A TW 107120829 A TW107120829 A TW 107120829A TW 107120829 A TW107120829 A TW 107120829A TW 201926461 A TW201926461 A TW 201926461A
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layer
dielectric constant
interface
interface layer
high dielectric
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TW107120829A
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張志宇
張翔筆
方子韋
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台灣積體電路製造股份有限公司
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Abstract

一種方法包含在半導體基板上形成通道區域。在通道區域上形成介面層。使用三甲基鋁(TMA)處理介面層。在使用TMA處理介面層之後在介面層上形成高介電常數(高介電常數)介電質層。在高介電常數介電質層上形成閘極。使用TMA處理介面層和形成高介電常數介電質層係在同一腔室中進行。在使用TMA處理介面層之前退火介面層。退火介面層和使用TMA處理介面層係在不同的腔室中進行。

Description

半導體裝置的製造方法
本揭露涉及一種半導體裝置的製造方法。
使用有意生長的介面層(interfacial layer,IL)以便在通道區域和閘極絕緣體之間配置良好的介面，特別是使用高介電常數(高介電常數)介電質(例如二氧化鉿(HfO2)、矽酸鉿(HfSiO4)、二氧化鋯(ZrO2)、矽酸鋯(ZrSiO4)等)，並以抑制金屬氧化物半導體場效應電晶體(metal-oxide-semiconductor field-effect transistors,MOSFET)中通道載子遷移率的降低。
然而，當通道區域含有矽鍺時，介面層的形成常常會導致介面層表面上的懸鍵。懸鍵會降低通道區域的電子遷移率。去除懸鍵的方法之一是在通道區域上磊晶生長覆蓋層。然而附加的覆蓋層會增加通道區域的厚度，並使元件的尺寸必須因此妥協。
本揭露內容之一態樣提供一種製造半導體裝置之 方法，包含下列步驟：形成通道區域於半導體基板上；形成介面層於通道區域上；使用三甲基鋁處理介面層；在使用三甲基鋁處理介面層之後，在介面層上形成一高介電常數介電質層；以及形成閘極於高介電常數介電質層上。
100‧‧‧方法
110、120、130、140、150‧‧‧操作
10‧‧‧晶片
20‧‧‧半導體基板
22‧‧‧虛設閘極堆疊
24‧‧‧虛設閘極介電質
26‧‧‧虛設閘極
28‧‧‧硬掩模
30‧‧‧源極和汲極區域
32‧‧‧通道區域
34‧‧‧閘極間隔物
38‧‧‧源極/汲極區域
40‧‧‧接觸蝕刻停止層
42‧‧‧層間介電質層
44‧‧‧凹槽
52、52a、52b、52c‧‧‧介面層
54‧‧‧高介電常數介電質層
62‧‧‧功函數金屬層
64‧‧‧金屬閘極
72‧‧‧替代閘極堆疊
202‧‧‧Si1-xGex層
當結合附圖閱讀時，根據以下詳細描述可以最好地理解本揭露的各方面。應注意，根據業界的標準慣例，各種特徵並未按比例繪製。實際上，為了清楚討論，各種特徵的尺寸可以任意增加或減小。
第1圖繪示根據本揭露之部分實施例中製造半導體裝置的方法的流程圖； 第2圖至第18圖是根據本揭露之部分實施例中在替換閘極堆疊形成製程中處於不同階段之部分的半導體裝置的橫截面圖；以及 第19A圖至第19D圖是根據本揭露之部分實施例中介面層處理製程中部分之半導體裝置的橫截面圖。
以下公開提供了用於實現所提供之主題的不同特徵的許多不同實施例或示例。以下描述組件和佈置的具體示例以簡化本揭露。當然，這些僅僅是示例，並不意在限制。例如，在下面的描述中，在第二特徵上方或之上形成第一特徵可以包 含其中第一特徵和第二特徵形成為直接接觸的實施例，並且還可以包含其中可以在第一特徵和第二特徵之間形成額外特徵，使得第一特徵和第二特徵可以不直接接觸。另外，本揭露可以在各種示例中重複附圖標記和/或文字。這種重複是為了簡單和清楚的目的，並且本身並不指定所討論的各種實施例和/或配置之間的關係。
此外，為了便於描述，在此可以使用例如「在...之下」、「在...下方」、「低於」、「在...之上」、「高於」等等的空間相對術語來描述一個元件或特徵與如附圖所示的另一個元件或特徵的關係。除了附圖中描繪的方向之外，空間相對術語旨在涵蓋使用或操作中的裝置的不同方位。此裝置可以以其他方式定向(旋轉90度或在其他方位)並且同樣可以相應地解釋這裡使用的空間相關描述符號。
鰭片可以透過任何合適的方法來圖案化。例如，可以使用一種或多種光刻製程(包括雙重圖案化或多重圖案化製程)來圖案化鰭片。通常，雙重圖案化或多重圖案化製程結合了光刻和自對準製程，從而允許創建具有例如比使用單一直接光刻製程可獲得之間距小的間距的圖案。例如，在一個實施例中，在基板上方形成犧牲層並使用光刻製程進行圖案化。使用自對準製程沿著圖案化的犧牲層形成間隔物。然後移除犧牲層，接著可以使用其餘的間隔物來圖案化鰭片。
根據各種示例性實施例提供了一種金屬氧化物半導體(metal-oxide-semiconductor,MOS)裝置及其形成方法。繪示了形成金屬氧化物半導體裝置的中間階段。討論實施 例的變化。在各種視圖和說明性實施例中，相同的附圖標記用於表示相同的元件。
參照第1圖，其係根據本揭露之部分實施例中製造半導體裝置的方法100的流程圖。此方法從操作110開始，其中在半導體基板上形成通道區域。此方法繼續進行操作120，其中在通道區域上形成介面層。隨後，執行操作130，使用三甲基鋁(trimethyl aluminium,TMA)處理介面層。此方法繼續操作140，其中在使用三甲基鋁處理介面層之後在介面層上形成高介電常數介電質層。此方法繼續進行操作150，其中在高介電常數介電質層上形成閘極。下面的討論示出了可以根據第1圖的方法100製造的半導體裝置的實施例。雖然方法100在下面被圖示和描述為一系列步驟或事件，但是應該理解，所示出的這些步驟或事件的順序不應被解釋為限制意義。例如，一些步驟可以以不同的順序發生和/或與除本文所示和/或描述的那些之外的其他步驟或事件同時發生。另外，並非所有示出的步驟都需要以實施本文描述的一個或多個方面或實施例。此外，這裡描述的一個或多個步驟可以在一個或多個單獨的步驟和/或階段中執行。
第2圖至第12圖是根據一些示例性實施例中形成金屬氧化物半導體裝置的中間階段的橫截面圖。請參考第2圖提供了包括半導體基板20的晶片10。矽鍺(Si1-xGex)層202形成在半導體基板20上，並且x的範圍在約0.15和約0.95之間。在x小於0.15的情況下，得到的矽鍺層的鍺含量太低因此會產生不利的影響。在部分實施例中，x可以高於0.95，並且 它表示所得矽鍺中GeOx的高比例。Si1-xGex層202磊晶生長在半導體基板20的表面上。鍺具有比矽更高的晶格常數，因此所得到的Si1-xGex層202的晶格結構允許比半導體基板20更高的電子空穴遷移率(electron hole mobility)。淺溝槽隔離(shallow trench isolation,STI)區域(未繪示)形成在Si1-xGex層202中並用於限定金屬氧化物半導體裝置的主動區域(active regions)。
請繼續參考第2圖在Si1-xGex層202上方形成虛設閘極堆疊22。虛設閘極堆疊22包括虛設閘極介電質24和虛設閘極26。虛設閘極介電質24在一些示例性實施例中包括氧化矽。在其他實施例中，也可使用例如氮化矽、碳化矽、或其相似物等的其他材料。虛設閘極26可以包括多晶矽。在部分實施例中，虛設閘極堆疊22進一步包括在虛設閘極26上方的硬掩模28。例如，硬掩模28可以包括例如氮化矽，然而也可以使用例如碳化矽、氮氧化矽、或其相似物等的其它材料。在部分的實施例中，不形成硬掩模28。虛設閘極堆疊22在Si1-xGex層202中限定通道區域32。源極和汲極區域(以下稱為源極/汲極區域)38(第3圖)隨後形成在通道區域32的相對側上。
請繼續參考第2圖。例如透過將p型雜質(例如硼和/或銦)注入到Si1-xGex層202中以形成輕摻雜源極和汲極(lightly-doped source and drain,LDD)區域30。例如，當金屬氧化物半導體裝置是p型金屬氧化物半導體(pMOS)裝置時，輕摻雜源極和汲極區域30是p型區域。虛設閘極堆疊22用作注入掩模，使得輕摻雜源極和汲極區域30的邊緣與虛 設閘極堆疊22的邊緣大致對齊。
參考第3圖。在虛設閘極堆疊22的側壁上形成閘極間隔物34。在部分實施例中，每個閘極間隔物34包括氮氧化矽層和氧化矽層。在其他實施例中，閘極間隔物34包括一層或多層，每個層包括氧化矽、氮化矽、氮氧化矽和/或其他介電質材料。閘極間隔物34的形成方法包括但不限於電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)、低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)、次大氣壓化學氣相沉積(sub-atmospheric chemical vapor deposition,SACVD)和其他沉積方法。
請繼續參考第3圖。在Si1-xGex層202中形成源極/汲極區域38。在其中金屬氧化物半導體裝置是p型金屬氧化物半導體裝置的實施例中，源極/汲極區域38是p型。在部分實施例中，在Si1-xGex層202中形成源極/汲極應力源(source/drain stressors)。源極/汲極應力源形成源極/汲極區域38的至少一部分。第3圖繪示了其中源極/汲極區域38完全重疊各自的源極/汲極應力源。
在金屬氧化物半導體裝置是p型金屬氧化物半導體裝置之部分實施例中，源極/汲極應力源可以包括合適的摻雜劑。可以透過蝕刻Si1-xGex層202和半導體基板20以在其中形成凹陷，然後執行磊晶以在凹陷中生長源極/汲極應力源來形成源極/汲極應力源。
請參考第4圖。在虛設閘極堆疊22和源極/汲極區 域38之上形成接觸蝕刻停止層(contact etch stop layer,CESL)40。在部分實施例中，接觸蝕刻停止層40包括氮化矽、碳化矽或其他介電質材料。在接觸蝕刻停止層40上方形成層間介電質(interlayer dielectric,ILD)層42。層間介電質層42毯式地形成到高於虛設閘極堆疊22的頂面的高度。層間介電質層42可包括使用例如可流動化學氣相沉積(lowable chemical vapot deposition,FCVD)形成的可流動氧化物。層間介電質層42也可以是使用旋轉塗佈形成的旋塗玻璃。例如，層間介電質層42可以包括磷矽酸鹽玻璃(phospho-silicate glass,PSG)、硼矽酸鹽玻璃(boro-silicate glass,BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phospho-silicate glass,BPSG)、四乙氧基矽烷(tetraethyl orthosilicate,TEOS)氧化物、氮化鈦(TiN)、碳氧化矽(SiOC)或其他低介電常數多孔介電質材料。
請參考第5圖。第5圖繪示使用例如化學機械平坦化(chemical mechanical polish,CMP)進行的平坦化步驟。執行化學機械平坦化以移除層間介電質層42和接觸蝕刻停止層40的多餘部分。移除硬掩模28頂表面上方的多餘部分。因此，暴露虛設閘極堆疊22。在另外的實施例中，在化學機械平坦化期間移除硬掩模28，其中化學機械平坦化停止於虛設閘極26的頂表面上。
請參考第6圖。接著，移除虛設閘極堆疊22。移除虛設閘極堆疊22的結果為形成凹槽44，其中所得之結構繪示於第6圖中。移除虛設閘極堆疊22暴露了下面的Si1-xGex層 202。
第7圖至第12圖繪示替代閘極堆疊的形成。請參考第7圖。在通道區域32上形成介面層52。使用介面層52以便在Si1-xGex層202和閘極絕緣體之間配置良好的介面，特別是使用高介電常數介電質(例如二氧化鉿(HfO2)、矽酸鉿(HfSiO4)、二氧化鋯(ZrO2)、矽酸鋯(ZrSiO4)等)，以抑制金屬氧化物半導體場效應電晶體(MOSFET)的通道載子之遷移率的降低。透過稀釋的氫氟酸、標準清潔1(Standard Clean 1,SC1)和標準清潔2(Standard Clean 1,SC2)、電漿氧化、臭氧化去離子水處理、快速熱氧化(rapid thermal oxidation,RTO)、或其類似物等製備的化學氧化物可在替代閘極堆疊時用於形成介面層52。例如，臭氧化的氧化物可以透過以氣相或預先溶解在去離子(de-ionized,DI)水中的高臭氧氣體生長。在部分實施例中，介面層52與通道區域32接觸。
在Si1-xGex層202氧化之後，在通道區域32的表面上形成介面層52的薄膜。介面層52包括氧化矽(SiOy，其中y大於0)和氧化鍺(GeOy，其中y大於0的)。由氧化處理產生的介面層52中的氧化鍺的比例高度依賴於半導體基板20上的Si1-xGex層202中的鍺含量。Si1-xGex層202中鍺的含量越高，則介面層52中氧化鍺的含量也越高。Si1-xGex層202中鍺的含量越低，則介面層52中氧化鍺的含量也越低。氧化鍺對於形成在Si1-xGex通道區域上的介面層的品質是有害的。帶電的介面狀態的增加證明了對通道區域的危害。對通道區域的危害也可由隨著介面層中氧化鍺的含量的增加而導致的遷移率降 低來證明。因此，本揭露描述了用於從介面層52清除或去除氧化鍺的方法，其包括形成在Si1-xGex層202上的氧化鍺和氧化矽。在部分實施例中，氧化鍺實質上從介面層52中移除，而留下氧化矽。在其他實施例中，在清除步驟之後，殘留的氧化鍺例如小於5%。
參考第8圖。下面描述透過清除步驟從介面層52除去氧化鍺。未標號的箭頭表示對晶片10的熱退火處理。清除步驟的第一階段透過在約500℃至約900℃的溫度下加熱晶片10約1分鐘來進行。如果加熱溫度低於500℃，則不能從介面層52完全除去氧化鍺。如果加熱溫度高於900℃，則可能發生源極和汲極劣化或介面粗糙。此熱退火在約1托(Torr)至約760托的氣壓中進行。熱退火處理在基本上無氧的條件且具有例如氮氣(N2)的惰性氣體的情況下進行以防止氧化。清除步驟是有效的，因為氧化鍺中的鍺-氧鍵比氧化矽中的矽-氧鍵和Si1-xGex層202中的矽-鍺鍵弱得多。因此，氧化鍺容易被除去，留下氧化矽保留在位於Si1-xGex層202上的介面層52a內。清除步驟的第一階段在晶片10轉移到原子層沉積(atomic layer deposition,ALD)反應室之前去除介面層52中大部分的氧化鍺。
請參考第9圖。從介面層52a中去除氧化鍺持續到第二階段。未標號的箭頭顯示了對晶片10原位的三甲基鋁(TMA)預處理。在基本上無氧的條件下進行三甲基鋁預處理。在氧化鍺清除步驟的第一階段之後，將晶片10轉移到原子層沉積反應室(未繪示)，以準備沉積高介電常數介電質層。 在沉積高介電常數介電質層之前，晶片10在原子層沉積反應室中經歷三甲基鋁預處理。三甲基鋁是強還原劑，並且提供三甲基鋁的前驅物約30秒。三甲基鋁預處理在約150℃至約300℃的溫度下進行。這種三甲基鋁預處理是在透過原子層沉積沉積高介電常數介電質層之前的連續製程，並且三甲基鋁預處理的反應條件類似於高介電常數介電質層沉積之原子層沉積的反應條件。三甲基鋁前驅物的流量在約200每分鐘標準毫升數(standard cubic centimeter per minute,sccm)至約600sccm的範圍內。低於200sccm的流量可能導致氧化鍺的不完全去除。根據流量選擇氣壓。在部分實施例中，在三甲基鋁預處理期間的氣壓在約1托至約25托的範圍內。接著，透過三甲基鋁預處理去除介面層52a中剩餘的氧化鍺。在部分實施例中，在不同的腔室中進行熱退火處理和三甲基鋁預處理。
請參考第19A圖至第19D圖，其繪示氧化鍺清除步驟的示意圖。如第19A圖所示，形成矽鍺(Si1-xGex)層202。透過第19B圖所示的氧化步驟，在Si1-xGex層202上形成介面層52。介面層52包括氧化矽和氧化鍺，並且氧化矽和氧化鍺的含量取決於Si1-xGex層202的矽鍺比率。如第19C圖所示，未標號的箭頭表示清除氧化鍺的第一階段，其中熱退火處理中斷鍺和氧的鍵結，以將氧化鍺從介面層52中移除。氧化矽仍為介面層52a的成分。如第19D圖所示，接著進行三甲基鋁預處理以從介面層52a去除剩餘的氧化鍺。三甲基鋁預處理是在高介電常數介電質層原子層沉積製程中原位進行的。不需要將晶片10移動到不同的腔室以進行三甲基鋁預處理，這將簡化了製 造過程。介面層52的厚度保持相對地不變。
請參考第10圖。在部分實施例中，在沉積高介電常數介電質層之前，執行原位氮化處理。氮化處理在原子層沉積反應室中進行。未編號的箭頭顯示氮化過程。透過包括熱退火和三甲基鋁預處理的兩階段清除步驟除去氧化鍺。透過用含氮試劑進行氮化處理，將介面層52b的剩餘氧化矽轉化為氮氧化矽(SiOaNb)，其中a和b皆大於0。氮化處理包括例如在電漿輔助原子層沉積(plasma enhanced atomic layer deposition,PEALD)的氨(NH3)電漿中約5秒至30秒，在電漿輔助原子層沉積的氮(N2)電漿中約5秒至30秒，或者在氨(NH3)氣體在約300℃至500℃的電漿輔助原子層沉積中退火約1分鐘。如果電漿處理的持續時間短於5秒，則氮化效果可能不足，導致後續製程中形成氧化鍺。如果電漿處理的持續時間長於30秒，則電漿的強度可能會損壞介面層52b。如果氨(NH3)氣體退火的溫度低於300℃，則可能不會在介面層52b上發生氮化，並且此持續時間將允許足夠的氮氧化矽的形成。此氮化處理進一步防止Si1-xGex層202的鍺向外擴散。然後，介面層52c便是含氮層，例如是覆蓋Si1-xGex層202的通道區域32的氮氧化矽層。
在部分實施例中，氮化處理可以延伸到介面層52c與Si1-xGex層202之間的介面。這防止了Si1-xGex層202的鍺向外擴散。這也避免了介面層52c具有未處理的部分。此未處理部分會增加閘極堆疊的等效氧化物厚度(effective oxide thickness,EOT)，導致裝置的閘極控制能力較低。在部分實 施例中，氮化的介面層52c在其中包含氮，並且氮化的介面層52c的厚度在約5埃(Å)至約10埃的範圍內。如果氮化的介面層52c的厚度小於約5埃，則氮化的介面層52c可能不夠厚以防止Si1-xGex層202的鍺向外擴散，導致在隨後的製程中形成氧化鍺。另一方面，如果氮化介面層52c大於約10埃，則閘極堆疊的等效氧化物厚度可能太厚，導致裝置的閘極控制能力較低。
在部分實施例中，在氮化處理期間，半導體基板20的溫度在約300℃至約1000℃的範圍內。如果在氮化處理期間半導體基板20的溫度低於約300℃，則氮化效果可能不足，導致在後續製程中形成氧化鍺。如果半導體基板20的溫度大於約1000℃，則氮化處理可能會影響下面的Si1-xGex層202，導致閘極堆疊的等效氧化物厚度增加，這將導致裝置的閘極控制能力較低。
在部分實施例中，氮化處理的電漿功率在約50瓦(w)至約650瓦的範圍內。如果氮化處理的電漿功率低於約50瓦，則氮化效果可能不足，導致在後續製程中形成氧化鍺。如果氮化處理的電漿功率大於約650瓦，則氮化處理可能影響下面的Si1-xGex層202，導致閘極堆疊的等效氧化物厚度增加，這將導致裝置的閘極控制能力較低。
請參考第11圖。形成高介電常數介電質層54。高介電常數介電質層54包括例如氧化鉿、氧化鑭、氧化鋁等的高介電常數介電質材料。高介電常數介電質材料的介電常數(k值)高於3.9，並且可能高於約7，有時高達21或更高。高介電 常數介電質層54覆蓋介面層52c。在原子層沉積反應室中形成高介電常數介電質層54。功函數金屬層62形成在高介電常數介電質層54上。根據部分實施例，功函數金屬層62可以包括鈦鋁(TiAl)。在部分實施例中，在功函數金屬層62和高介電常數介電質層54之間插入隔離層(未繪示)。隔離層可以包括氮化鈦(TiN)、氮化鉭(TaN)或其複合物。例如，隔離層可以包括氮化鈦層(隔離層的下部)和在氮化鈦層上的氮化鉭層(隔離層的上部)。
請繼續參考第11圖。在部分實施例中，隨後形成的金屬層可以包括阻擋層(未繪示)、潤濕層(未繪示)和金屬閘極64。阻擋層可以包括氮化鈦，並且潤濕層可以是鈷層。金屬閘極64可以包括鎢、鎢合金、鋁、鋁合金等。
參考第12圖，繪示平坦化步驟。平坦化步驟可以是例如使用化學機械平坦化以去除位於層間介電質層42上方之多餘的高介電常數介電質層54、功函數金屬層62和金屬閘極64。介面層52c、高介電常數介電質層54、功函數金屬層62和金屬閘極形成替代閘極堆疊72。
替代閘極堆疊72具有位於高介電常數介電質層54和Si1-xGex層202之間的含氮介面層52c。介面層52c經歷熱退火和三甲基鋁預處理並且進一步進行氮化處理。這些製程確保氧化鍺從介面層52c中脫附，並且因此在介面層52c和Si1-xGex層202之間的介面處保持較低的介面能態密度(interface state density,Dit)。較低的介面能態密度較不可能使開關切換曲線變平坦並允許在通道區域具有較高的電 子遷移率。可以省略處理Si1-xGex層202表面的磊晶製程，因為一系列介面層處理已使其上的懸鍵最小化。如果在通道區域上不添加磊晶蓋，則可以實現通道體的縮小，特別是在例如超薄體絕緣體上矽鍺(Silicon Germanium on Insulator,SiGe-OI)場效應電晶體(Field Effect Transistor,FET)、鰭式場效應電晶體(FinFET)、奈米線場效應電晶體等的裝置中。
第13圖至第15圖繪示在部分實施例中替代閘極堆疊的形成。請參考第13圖，第13圖繪示高介電常數鈍化層82的形成。在如第2圖至第6圖所示之移除虛設閘極堆疊22並且形成凹槽44之後，介面層52經過一系列處理，包括熱退火和原位三甲基鋁預處理，如第7圖至第9圖所示。當在高介電常數介電質層沉積之前並在將三甲基鋁前驅物引入反應室時，晶片10位於原子層沉積反應室中。在退火和三甲基鋁預處理之後，氧化鍺已從介面層52b中去除，留下氧化矽作為介面層52b中的關鍵組分。在部分實施例中，在此過程中省略介面層的氮化。或者，在經過熱退火和三甲基鋁預處理的介面層52b上形成高介電常數鈍化層82。
在同一原子層沉積反應室中，在高介電常數介電質層沉積之前，透過原子層沉積形成高介電常數鈍化層82。高介電常數鈍化層82與替代閘極凹槽44一致，其中閘極間隔物34的側壁和介面層52b的頂表面因此被覆蓋。高介電常數鈍化層82與介面層52b反應。因此，高介電常數鈍化層82在其底部包括例如高介電常數矽酸鹽、鍺酸鹽或其組合。隨著與介面層 52b的距離的增加，高介電常數鈍化層82中的高介電常數矽酸鹽或鍺酸鹽的濃度減小。高介電常數鈍化層82中的高介電常數材料的實例可以是氧化鋁(Al2O3)、氧化鑭(La2O3)、氧化釔(Y3O3)或其組合。此高介電常數鈍化層82可防止Si1-xGex層202的鍺向外擴散。高介電常數鈍化層82的厚度可以在約5埃和10埃之間的範圍內。
在部分實施例中，高介電常數鈍化層82的厚度在從大約5埃到大約10埃的範圍內。如果高介電常數鈍化層82的厚度小於約5埃，則高介電常數鈍化層82可能不夠厚以防止Si1-xGex層202的鍺向外擴散，導致在隨後的過程中形成氧化鍺。如果高介電常數鈍化層82的厚度大於約10埃，則閘極堆疊的等效氧化物厚度(EOT)可能太厚，導致裝置的閘極控制能力較低。
請參考第14圖。高介電常數介電質層54形成在高介電常數鈍化層82上。高介電常數介電質層54包括高介電常數介電質材料，例如氧化鉿、氧化鑭、氧化鋁或其相似物等。在原子層沉積反應室中執行高介電常數介電質層54的形成。高介電常數鈍化層82插入在高介電常數介電質層54和介面層52b之間。與第11圖中所示的實施例不同，由於插入高介電常數鈍化層82，因此高介電常數介電質層54與介面層52b間隔開。形成功函數金屬層62於高介電常數介電質層54上。根據部分實施例，功函數金屬層62可以包括鈦鋁(TiAl)。
請繼續參考第14圖。在部分實施例中，隨後形成的金屬層可以包括阻擋層(未繪示)、潤濕層(未繪示)和金 屬閘極64。阻擋層可以包括氮化鈦(TiN)，並且潤濕層可以是鈷層。金屬閘極64可以包括鎢、鎢合金、鋁、鋁合金，或其相似物等。
請參考第15圖，其繪示平坦化步驟。平坦化步驟可以例如是使用化學機械平坦化以移除位於層間介電質層42上的高介電常數鈍化層82、高介電常數介電質層54、功函數金屬層62和金屬閘極64的多餘部分。介面層52b、高介電常數鈍化層82、高介電常數介電質層54、功函數金屬層62和金屬閘極64形成替代閘極堆疊92。
替代閘極堆疊92具有介於介面層52b和高介電常數介電質層54之間的高介電常數鈍化層82。介面層52b經歷熱退火和三甲基鋁預處理以去除其上的懸鍵，並且高介電常數鈍化層82防止鍺從Si1-xGex層202向外擴散。這些製程確保無鍺氧化物的介面層52b，並且來自Si1-xGex層202的鍺被限制在其內。較低的介面能態密度(Dit)因此可以保持在介面層52b和Si1-xGex層202之間的介面處。較低的介面能態密度(Dit)較不可能使開關切換曲線變平坦並且允許在通道區域處具有較高的電子遷移率。即使在通道區域上沒有添加磊晶蓋，氧化鍺已被去除，並且剩餘的自由鍺也不會擴散出Si1-xGex層202。
請參考第16圖。在部分實施例中，在進行原位氮化處理(參見第10圖)之後，高介電常數鈍化層82形成在是氧氮化矽層的介面層52c上。在原子層沉積反應室中進行高介電常數鈍化層82的形成。介面層52c覆蓋通道區域32，並且高介電常數鈍化層82覆蓋介面層52c。高介電常數鈍化層82與替 換閘極凹槽44一致，其中閘極間隔物34的側壁和介面層52c的頂表面因此被覆蓋。高介電常數鈍化層82與介面層52c反應。因此，高介電常數鈍化層82在其覆蓋介面層52c的底部中包含例如高介電常數矽酸鹽、鍺酸鹽或其組合。隨著與介面層52c的距離的增加，高介電常數鈍化層82中的高介電常數矽酸鹽或鍺酸鹽的濃度降低。高介電常數鈍化層82中的高介電常數材料的實例可以是氧化鋁(Al2O3)、氧化鑭(La2O3)、氧化釔(Y3O3)或其組合。此高介電常數鈍化層82防止Si1-xGex層202的鍺向外擴散。高介電常數鈍化層82的厚度可以在約5埃和10埃之間的範圍內。
請參考第17圖。形成高介電常數介電質層54。高介電常數介電質層54包括例如氧化鉿、氧化鑭、氧化鋁或其相似物等的高介電常數介電質材料。在原子層沉積反應室中執行高介電常數介電質層54的形成。高介電常數介電質材料的介電常數(k值)高於3.9，並且可能高於約7，有時高達21或更高。高介電常數介電質層54覆蓋高介電常數鈍化層82。功函數金屬層62形成在高介電常數介電質層54上。根據部分實施例，功函數金屬層62可以包括鈦鋁(TiAl)。在部分實施例中，在功函數金屬層62和高介電常數介電質層54之間插入隔離層(未繪示)。隔離層可以包括氮化鈦(TiN)、氮化鉭(TaN)或其複合物。例如，例如，隔離層可以包括氮化鈦層(隔離層的下部)和在氮化鈦層上的氮化鉭層(隔離層的上部)。
請參考第17圖。在部分實施例中，隨後形成的金屬層可以包括阻擋層(未繪示)、潤濕層(未繪示)和金屬閘 極64。阻擋層可以包括氮化鈦(TiN)，並且潤濕層可以是鈷層。金屬閘極64可以包括鎢、鎢合金、鋁、鋁合金，或其相似物。
請參考第18圖，此圖繪示平坦化步驟。平坦化步驟可以是例如化學機械平坦化，以用於移除位於層間介電質層42上的高介電常數鈍化層82、高介電常數介電質層54、功函數金屬層62和金屬閘極64的多餘部分。介面層52c、高介電常數鈍化層82、高介電常數介電質層54、功函數金屬層62和金屬閘極64形成替代閘極堆疊92。
替代閘極堆疊92具有含氮介面層52c和介於介面層52c和高介電常數介電質層54之間的高介電常數鈍化層82。介面層52c經歷熱退火和三甲基鋁預處理，以便去除其上的懸鍵。介面層52c防止鍺從Si1-xGex層202向外擴散，並且高介電常數鈍化層82是防止鍺向外擴散的第二阻擋層。由於介面層52c和高介電常數鈍化層82，剩餘的鍺牢固地固定在Si1-xGex層202中。因此可以在介面層52c和Si1-xGex層202之間的介面處保持較低的介面能態密度(Dit)。較低的介面能態密度(Dit)較不可能使開關切換曲線變平坦並且允許在通道區域32處具有較高的電子遷移率。
在介面層形成之後，首先對介面層進行退火以除去氧化鍺。隨後，進行涉及在介面層上使用三甲基鋁前驅物的三甲基鋁預處理。三甲基鋁預處理進一步從介面層中去除剩餘的氧化鍺。接著，介面層可以經歷氮化以形成氮氧化矽層。或者，可以在介面層上形成高介電常數鈍化層。氮化過程或高介 電常數鈍化層防止鍺從Si1-xGex層向外擴散。由於去除了氧化鍺並且阻礙了鍺外擴散，因此可以在介面層和Si1-xGex層之間的介面處實現較低的介面能態密度(Dit)，因而使通道區具有更高的電子遷移率。
在部分實施例中，一種方法包括在半導體基板上形成通道區域。在通道區域上形成介面層。使用三甲基鋁(TMA)處理介面層。在使用三甲基鋁處理介面層之後在介面層上形成高介電常數介電質層。在高介電常數介電質層上形成閘極。
在部分實施例中，使用三甲基鋁處理介面層和形成高介電常數介電質層係在同一腔室中進行。
在一些實施方案中，此方法更包含在使用三甲基鋁處理介面層之前退火介面層。
在部分實施方案中，退火介面層和使用三甲基鋁處理介面層係在不同的腔室中進行。
在部分實施例中，此方法更包含在形成高介電常數介電質層之前用含氮試劑處理介面層。
在部分實施例中，用含氮試劑處理介面層是在使用三甲基鋁處理介面層之後進行的。
在部分實施例中，此方法更包含在形成高介電常數介電質層之前在介面層上形成高介電常數鈍化層，其中高介電常數鈍化層包括高介電常數矽酸鹽、高介電常數鍺酸鹽，或其組合。
在部分實施例中，高介電常數鈍化層包括氧化鋁 (Al2O3)、氧化鑭(La2O3)、氧化釔(Y3O3)或其組合。
在部分實施例中，在使用三甲基鋁處理介面層之後形成高介電常數鈍化層。
在部分實施例中，通道區域包括矽鍺。
在一些實施方式中，使用三甲基鋁處理介面層係在基本上無氧的條件下進行。
在部分實施例中，一種方法包括在半導體基板上形成通道區域。在通道區域上形成介面層。高介電常數鈍化層形成在介面層上。高介電常數鈍化層包括高介電常數矽酸鹽、高介電常數鍺酸鹽或其組合。高介電常數介電質層形成在高介電常數鈍化層上。在高介電常數介電質層上形成閘極。
在部分實施例中，此方法更包含在形成高介電常數鈍化層之前在介面層上執行氮化製程。
在部分實施例中，氮化製程包括氨(NH3)電漿處理、氮(N2)電漿處理、氨(NH3)氣退火或其組合。
在部分實施例中，此方法更包含在形成高介電常數鈍化層之前退火介面層。
在部分實施例中，介面層的退火係在基本上無氧的條件下進行。
在部分實施例中，裝置具有半導體基板，此半導體基板包括通道區域、在通道區域上的介面層、以及在介面層上的高介電常數鈍化層。高介電常數鈍化層包括高介電常數矽酸鹽、高介電常數鍺酸鹽或其組合。高介電常數介電質層設置在高介電常數鈍化層上。金屬閘極設置在高介電常數介電質層 上。
在部分實施例中，介面層包括氮氧化矽。
在部分實施例中，高介電常數鈍化層包括氧化鋁(Al2O3)、氧化鑭(La2O3)、氧化釔(Y3O3)或其組合。
在部分實施例中，介面層與通道區域接觸。
以上概述了若干實施例的特徵，以便本領域技術人員可以更好地理解本揭露的各方面。本領域的技術人員應該理解，他們可以容易地使用本揭露作為用於設計或修改用於實現相同目的和/或實現本文介紹的實施例的相同優點的其他過程和結構的基礎。本領域技術人員還應該認識到，這樣的等同構造不脫離本揭露的精神和範圍，並且可以在不脫離本揭露的精神和範圍的情況下進行各種改變、替換和變更。

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  1. 一種半導體裝置的製造方法，包含：形成一通道區域於一半導體基板上；形成一介面層於該通道區域上；使用三甲基鋁處理該介面層；在使用三甲基鋁處理該介面層之後，在該介面層上形成一高介電常數介電質層；以及形成一閘極於該高介電常數介電質層上。
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US10629749B2 (en) 2020-04-21
US20190165185A1 (en) 2019-05-30
US20230282753A1 (en) 2023-09-07
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US20210296507A1 (en) 2021-09-23
US20200251598A1 (en) 2020-08-06

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