CN1098558A - 无支撑板的半导体器件及其制造方法 - Google Patents
无支撑板的半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1098558A CN1098558A CN94103951A CN94103951A CN1098558A CN 1098558 A CN1098558 A CN 1098558A CN 94103951 A CN94103951 A CN 94103951A CN 94103951 A CN94103951 A CN 94103951A CN 1098558 A CN1098558 A CN 1098558A
- Authority
- CN
- China
- Prior art keywords
- chip
- connecting rod
- semiconductor device
- support section
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title description 16
- 238000004519 manufacturing process Methods 0.000 title description 10
- 238000007789 sealing Methods 0.000 claims description 2
- 239000004033 plastic Substances 0.000 abstract description 23
- 229920003023 plastic Polymers 0.000 abstract description 23
- 238000003466 welding Methods 0.000 abstract description 13
- 238000013461 design Methods 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000003822 epoxy resin Substances 0.000 description 10
- 229920000647 polyepoxide Polymers 0.000 description 10
- 239000007767 bonding agent Substances 0.000 description 9
- 230000008901 benefit Effects 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 241000272168 Laridae Species 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000008393 encapsulating agent Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000012512 characterization method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003467 diminishing effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000013354 porous framework Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29007—Layer connector smaller than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
Abstract
一种无支撑板半导体器件(10),包括一具有多个
压焊区(26)的半导体芯片(22),压焊区经焊线(28)与
多根引线(16)电连接。芯片由两个悬臂状连杆(18)
支撑。使用悬臂状连杆减少了塑料封装的器件中总
的塑料-金属界面面积,从而降低了内部剥离和外壳
龟裂的可能性。悬臂状连杆也使得相同的引线框架
设计可用于不同的芯片尺寸。悬臂状连杆合适的形
状包括(但不限于)U形、T形和H形。
Description
本发明一般来说涉及半导体器件,更具体地说,涉及无支撑板(flagless)的半导体器件及其制造方法。
外壳龟裂是塑料封装的半导体器体中存在的普遍问题。这一问题是由多种因素的组合所产生的。一个因素就是塑料封装材料和引线框架支撑板之间的内部剥离。支撑板是常规引线框架中支撑芯片的板状构件。和引线框架的其余构件一样,支撑板通常由铜、铜合金,或铁镍合金构成的,因此在大多数情况下,其热膨胀系数(CTE)与周围的注模成分或塑料的热膨胀系数不同。作为这种CTE失配的结果是当半导体器件经受温度变化时在塑料-支撑板界面处产生应力。一旦该应力达到最大阈值,就通过塑料-支撑板界面的剥离而释放出来。外壳龟裂的另一因素是湿气吸收。在塑料-支撑板界面产生了剥离之后,湿气就从周围环境经过注模成分扩散到剥离了的区域。一旦在外壳中积蓄了湿气,温度的急速增加就会引起湿气的蒸发和膨胀,从而在该剥离了的区域产生一个内部压力袋(pressure pocket)。要释放出压力及相应的应力,周围的塑料就得破裂。外壳龟裂最常发生在用户用回流钎焊工艺把塑料封装的半导体器件装到-基板上的时候。伴随着回流钎焊而产生的高温导致温度迅速上升,这往往足以引起塑料封装破裂(取决于器件的湿气含量)。
目前有许多处理外壳龟裂问题的方法。一种方法是干燥封装。这种方法就是烘烤塑料封装的半导体器件以充分降低湿气的含量,并将这些器件装在防湿的盒内。器件的用户在外壳由于暴露于大气环境中能吸入足以引起破裂的湿气的量将器件安装好。这种方法是能效的,但显著地增加了半导体器件的成本。而且,器件的用户必须一直关注器件在大气环境中已暴露了多长时间,以便确保吸入的湿气不足以引起破裂的问题。
其它一些已知的途径试图通过改进支撑板与塑料之间的粘接来减少内部剥离的可能性。例如,某些制造商把支撑板的金属表面弄粗糙,以改进粘附性。另一些制造商在支撑板表面上制造出小孔或凹坑来提供固定机能。改进粘附性的另一个方法是用窗式框架支撑板。窗式框架支撑板大体上是一种支持芯片的多孔框架,而不是一个实心的片状物。
上述那些方法通过提供与塑料封装材料较好的粘附性,的确在某种程度上降低了剥离的可能性。本发明使用从前未用过的技术同样得到了降低剥离的优点,而且还解决了上述方法所没有涉及的另一个制造问题,即,半导体制造商对其各种产品要使用不同的或定做的引线框架的问题。要对各种芯片尺寸和芯片的功能性的管腿引出头作不同的引线框架设计,就需要大量的片状构件(Piece-Parts),并且在各产品投产前需要用额外的时间和人力来设计新的引线框架。除了与大量的构件及设计相关的成本之外,引线框架本身的成本也因制造量的不充分而产生不希望有的升高。各需单独加工的引线框架的几张小数额定单比总量相同的同种引线框架的一张订单所需成本要高。因此,利用一种能被几个不同的芯片尺寸共同使用的引线框架设计能显著降低半导体制造的成本。本发明通过在半导体器件中使用一种能由各种各样芯片尺寸使用的引线框架实现了这一目标,同时,改进了引线框架和封装材料之间的粘附性以减轻外壳的破裂问题。
在本发明的一种形式中,半导体器件具有由多根引线和两个悬臂状连杆构成的引线框架。多根引线有限定出芯片容纳区的内部部分。两个连杆从芯片容纳区的两相对侧延伸出来。半导体芯片附着在连杆上并由其支撑。该芯片还与多根引线进行电连接,并由外壳本体包封。制造这种或其它的该类型半导体器件的方法也包含在本发明的范围内。
由结合附图所作的详细描述可以更清楚地了解本发明的这些和其他特征以及优点。重要的是要指出这些插图不一定是按比例画的,而且本发明还可以有其它的未作具体图解说明的实施例。
图1是本发明的部分组装的、无支撑板的半导体器件的俯视图。
图2是使用与图1所示同样的引线框架设计的本发明另一个部分组装的、无支撑板半导体器件的俯视图。
图3为本发明的完全组装好的半导体器件的截面图。
图4为本发明另一个组装好的半导体器件的截面图。
图5为说明适用于本发明的另一种连杆设计的引线框架的俯视图。
图6为说明适用于本发明的又一种连杆设计的引线框架的俯视图。
本发明能降低内部封装剥离的可能性,同时通过利用悬臂状的连杆来支撑半导体芯片的方式建立起能用于几种不同芯片尺寸的通用设计。图1和图2说明本发明所用的引线框架的通用情况及其特性,这里,用连杆而不是支撑板来支撑半导体芯片。这两个图均为本发明的半导体器件的部分俯视图。图1说明半导体器件10,图2说明半导体器件20。器件10和20均包括一个具有两根相对的横条14、多根引线16和两个悬臂状的连杆18的引线框架12。图1和图2中的半导体芯片22和半导体芯片24粘在连杆18上。每个芯片包括多个按常规方式用多根连接线28与引线16电连接的导电压焊区26。
应注意,图1和图2所示的半导体器件是部分组装后的。这些器件还没有包封在塑料外壳本体中。如本领域的普通技术人员知道的,器件10和20接着用塑料封装材料封装起来,然后从引线框架12上切下来、形成完成了的器件。切开的结果,连杆18不再与横条14相连,而是分离开来,与由图1中虚线29表示轮廓的外壳本体的一个边齐平。引线16被切下来,接着将其作成以下几种外引线形状中的一种。这几种形状有鸥翅状、J状引线状或通孔状。
引线框架12是由常用的引线框架材料,如铜、铜合金、铁镍合金或其它类似材料形成的,并由金属腐蚀或冲压等常规工艺制造的。传统的制造工艺中,称为“flag”或“paddle”的板状构件与连杆相连,用来给半导体芯片提供一个安装区域。根据本发明不使用板,而是用悬臂状的连杆来支撑芯片。例如,在图1的器件10中,连杆18支撑半导体芯片22,图2的器件20是用连杆18支撑半导体芯片24。连杆18各包括一个柄部分19和一个支撑部分21。如图1所示,芯片22完全外伸或复盖在连杆18的支撑部分21之上。而如图2所示,支撑部分可以延伸超出芯片的周边,这样就不是所有的支撑部分都在芯片的下面。
在用连杆而不是用支撑板作为芯片支座的情况下,总的塑料-金属界面面积在器件包封在塑料中之后将被减少。为了描述本发明,用短语“塑料-金属界面”,而不是用短语“塑料-支撑板界面”,这是由于本发明的实施例中没有常规的支撑板。随着塑料-金属界面面积的减少,塑料与半导体芯片直接接触的面积就增加了。塑料-金属界面面积的减少和塑料-芯片界面面积的增加,减少了剥离的机会,因为绝大部分塑料包封材料将与芯片而不是与金属表面粘接得更好。因此,如果在一个连杆与包封塑料之间的界面处发生剥离,也不会影响另一个连杆与塑料的界面。
通过图1与图2的比较,可以清楚地看到引线框架12的通用性。在这两个图中,用的是相同的引线框架,但所用的芯片尺寸是不同的。如图所示,芯片22比芯片24大得多。由于不使用支撑板,所以对两种不同尺寸的器件不需要设计新的引线框架。在常规的半导体器件中,支撑半导体芯片的板的形状制造得与芯片相同,只是尺寸稍大一点。使用支撑板的目的是将它用于在组装操作中(主要是引线焊接步骤)和直到包封为止的一般的器件处理步骤中支撑芯片。一旦将芯片包封到塑料中,芯片支撑构件就不再需要了。把支撑板制造得比芯片大的一个目的是要能够进行芯片和支撑板之间粘接状况的外观检查。半导体芯片通常用环氧树脂粘接到支撑板上。在对着覆盖在板上的环氧树脂按压芯片时,环氧树脂从芯片下面挤压出来在芯片周边形成环氧树脂的镶边(fillet)。芯片与板之间粘接的质量可通过对上述镶边的肉眼观察来判断。如果该镶边是连续的,就认为粘接充分了。
根据本发明,粘接芯片的环氧树脂涂在悬臂状连杆的支撑芯片用的那些部分上。例如在图1中,环氧树脂涂在连杆18由虚线表示出的那些部分上。对着连杆按压芯片而进行粘接时,环氧树脂就被挤压出来,沿着连杆的四周而不是芯片的周围形成镶边。这种“翻转的”镶边在图3的半导体器件30的截面图中得到了说明。器件30包括-按装在悬臂状的连杆33上的半导体芯片32。该器件包封在塑料外壳35中,该芯片通过焊线37与多根引线36电连接。引线36如图所示为通孔状,当然也可以用J引线和鸥翅状。尽管芯片32粘接在两根连杆上,但该截面图实际上是经过一根连杆的分叉状部分取的,例如取图1和图2中连杆18的U形部分作图。芯片32用常规的芯片粘接剂34,如环氧树脂,粘在连杆上。当半导体芯片全部外伸在连杆之上时(如器件10和30),环氧树脂就象图3所示那样形成翻转的镶边。粘接状况可以象常规器件那样用环氧树脂镶边的连续性来进行评价。然而,检测翻转的镶边要从器件的背面来检查,如果要用检测工艺的话,就可能要在制造者的检测工艺中稍微改变一下。
在图2所示的本发明的芯片未完全伸出在连杆之上的实施例中,一个镶边应该在连杆延伸超出芯片处的芯片周边形成。而沿着芯片伸出在连杆之上的那部分连杆的周边形成另一个翻转的镶边。图4的器件40的截面图示出两个不同的镶边。器件40包括用芯片粘接剂44粘在叉状连杆43上的半导体芯片42。该器件包封在塑料外壳45内,芯片由焊线47与多根引线46电连接。引线46如图所示为J引线状,不过,也可以用通孔和鸥翅状。
尽管在根据本发明的器件中可以把各种不同尺寸的芯片用于同样的引线框架设计,但对所用芯片的尺寸还是有限制的。例如,芯片22和24的尺寸和形状分别受限定芯片容纳区的引线16的内部部分的影响。对引线框架12所用的芯片尺寸的另一个限制可能是焊线长度。随着芯片尺寸的变小,连接芯片与引线16所需的焊线28的长度增加。因此,制造者对焊线长度设置的上限也就对芯片尺寸设置了下限。
由于不用支撑板,在制造本发明的器件时可能需要改进现有的组装步骤。例如,如上面讨论所提到的,把芯片粘接剂的涂布图形局限在一个小的连杆面积上,而不是整个支撑板的面积上。所以,可能需要对粘接剂涂布头和涂布图型作工具性改进。此外,由于芯片支撑面积(连杆)比常规的支撑板小,本发明所需的粘接剂的量较少。另外可能需要对芯片粘接剂的涂布作较严格的工艺控制。由于芯片整个伸出,或至少部分伸出在连杆之上,则在粘接芯片时,粘接剂有可能伸展超过连杆,从而弄脏下面的工作台。因此,要严密监视粘接剂用量的上限。而如上所述,涂布足够的粘接剂以提供合适的镶边同时也是重要的。
另一工艺改进在引线焊接时是有用的。既然半导体芯片没有沿着芯片的周边全部被支撑,那么在引线焊接期间提供对芯片周边的支撑可能是有益的。压焊区一般(但不始终)位于芯片的周边。要在每个压焊区上焊接引线,引线焊接工具必然在每进行一次焊接时向芯片周边加压。如果引线压焊用力很大,或者芯片没有足够的韧性,则所加的力就会引起芯片的未得到支撑的部分破裂或碎裂。因此,最好在引线焊接台上增加一个支撑机构。例如,压焊台可以设计成包括一切口,该切口与悬臂状连杆的形状及厚度相匹配,以便压焊台与连杆一起形成一个基本平整和连续的表面。这样,整个芯片在引线焊接时就由连杆和压焊台的组合结构支撑起来。重要的是应注意,对现有引线焊接操作的改进对于实施本发明可能不是必须的。对改进的要求取决于许多因素,仅列出几个就有压焊力、芯片厚度、芯片尺寸和压焊区的位置等。
图1和图2中的连杆18为叉状,以便使各连杆的内端部为U形。不过,根据本发明,也可以用其它的悬臂状连杆的形状。图5和6中说明了两个这种可供替代的形状。这两张图只是半导体器件的一部分(也就是连杆部分)的俯视说明图。如图5所示,两个悬臂状连杆52其内端部为T形,其外端部象前面所说的实施例那样延伸到引线框架的横条上。和本发明前述的实施例一样,总的金属表面面积的减少有助于在连杆被塑料包封后阻止发生剥离。由于能适用于各种芯片尺寸(如虚线54和56代表的芯片),T形连杆也是通用的。线54表示半导体芯片的两个完整的边(即“短”边)能够得到支撑,这一点可能对某种特定的引线焊接方式是有利的。但具体对存储器芯片来说,通常芯片的“长”边侧设置着压焊区。为了支撑本发明的半导体芯片的“长”边侧,悬臂状连杆可以插入到引线中。例如在图1和图2中,连杆可以在引线之中和沿着和引线平行的方向形成,从而从左和右而不是如图所示那样从上和下方在半导体芯片之下延伸。
图6说明本发明的另一种连杆形式。两个悬臂状连杆62均为H形。连杆的内端在由虚线64表示的较大的半导体芯片之下延伸,或在由虚线65所表示的较小的半导体芯片之下延伸。连杆的外端伸向引线框架的横条(未图示)。如线64所表示的半导体芯片与H形连杆的中心部分66对准,並由其支撑。然而,这不是这种连杆的形状所要求的。这种连杆形状与所示的其它连杆形状一样,可以用于各种尺寸的半导体芯片。
在本发明的其它实施例中,可对前面所述的“叉状”连杆的形状加以改进以增加连杆的刚性。例如,对U形和H形而言,可用一个附加部分将连杆的自由端连在一起,以防止或限制各端在Z轴方向(垂直方向)上的独立运动,或换句话说,保持连杆的平面性。这种附加部分可以做成直的,也可以做成圆形的,以减少封装后的器件内产生的应力。
以上的描述表明了本发明的许多优点。特别是已经披露了可以用悬臂状连杆支撑半导体芯片,以减少塑料封装器件内部的总的塑料-金属界面。该界面的减少降低了界面处内部剥离的可能性,从而降低了外壳龟裂的可能性。此外,悬臂状连杆是互相分离的这一事实减少了可能发生的任何一个剥离的面积。如有一个连杆与包封塑料的界面处发生剥离,该剥离区域也不会波及到另一根连杆。换言之,两根连杆中每一个上出现的剥离均与另一个无关。本发明的附带的优点是应用悬臂状连杆使多种尺寸的芯片可由连杆来支撑。还有一个优点是实施本发明不用增加板状构件的成本。可以用与现行引线框架同样的价格来制造本发明所用的引线框架,或由于制造量较大而导致较低的价格。随着任何工具改进所导致的其它的制造成本的增加是极少的。
显然,根据本发明的无支撑板半导体器件及其制造方法完全满足前述要求和优点。尽管已参考具体的实例描述了本发明,但这並不说明仅局限于这些实施例。本领域的熟练技术人员均可以了解在不偏离本发明精神的范围内可作出各种改进和变动。例如,本发明没有具体地限定U形、T形和H形连杆的形状。此外,本发明也没有局限于任一特殊的外壳形状。本发明的器件的连杆可以设置在低于器件的引线的位置这一点也是很重要的,这可以象图3所示那样把芯片放大器件内所需要的高度。而且,本发明器件的连杆可包括对准特征,来帮助在芯片粘结时对准半导体芯片。另外,本发明不以任何方式局限于器件所用的半导体芯片的类型。尽管使用存储器芯片的器件可能将从本发明得到不少益处,其实用其它类型的芯片(如微控制器、模拟器件等)一样可以获益。因此,本发明包括所有在所附权利要求的范围内变动和改型。
Claims (10)
1、一种无支撑板半导体器件(10),其特征是:一个包括以下两部分的引线框架:
多根具有内引线部分和外引线部分的引线(16),其中内引线部分限定出具有两个相对侧边的芯片容纳区;
两个从该芯片容纳区相对两侧边延伸到芯片容纳区之内的连杆(18),这两根连杆互相不在另一个之下延伸、互相保持分离,且各有一个柄部分(19)和支撑部分(21);
一个装在两个连杆的支撑部分上的半导体芯片(22);
用于将半导体芯片与引线的内引线部分连接的装置(28);
一个包封该半导体芯片和多根引线的内引线部分的外壳本体(35)。
2、一种无支撑板半导体器件(10),其特征是:
各具有一内引线部分和一外引线部分的多根引线(16),这些内引线部分一起限定出一个芯片容纳区,该芯片容纳区有两个第一相对侧边和两个第二相对侧边,其中各第一相对侧边短于各第二相对侧边;
两个从各第一相对侧边延伸入芯片容纳区的连杆(18),各连杆有一柄部分(19)和支撑部分(21),该柄部分基本与多根引线的外引线部分垂直,且支撑部分终止于芯片容纳区内;
粘结在各连杆上並由其支撑的一个半导体芯片(22),该芯片完全覆盖住各连杆的支撑部分;
用于将半导体芯片与多根引线电连接起来的装置(28);以及
包封该半导体芯片及多根引线的内引线部分的一个外壳本体(35)。
3、如权利要求1或2的半导体器件,其中,各连杆的支撑部分为叉状,芯片放在该叉状的支撑部分上。
4、如权利要求3的半导体器件,其中,连杆的叉状支撑部分基本为U形或H形。
5、如权利要求3的半导体器件,其中,半导体芯片伸出在两个连杆的叉状支撑部分上。
6、如权利要求1或2的半导体器件,其中,各连杆的端部为T形。
7、如权利要求1或2的半导体器件,其中,外壳本体有四个侧面,多根引线的外引线部分从外壳本体的两个相对侧向外延伸,两根连杆中的每一个的端部与从引线框架上切下来后留下的两个侧边之一齐平。
8、如权利要求1的半导体器件,其中,两个连杆的支撑部分在芯片容纳区限定出一个矩形区域,该矩形区域的面积小于芯片面积。
9、如权利要求1的半导体器件,其中,两个连杆的支撑部分在芯片容纳区限定出一个矩形区域,该矩形区域的面积大于芯片面积。
10、如权利要求1或2的半导体器件,其中,半导体芯片还部分覆盖住两个连杆的柄部分。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3496193A | 1993-03-22 | 1993-03-22 | |
US034,961 | 1993-03-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1098558A true CN1098558A (zh) | 1995-02-08 |
Family
ID=21879739
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN94103951A Pending CN1098558A (zh) | 1993-03-22 | 1994-03-21 | 无支撑板的半导体器件及其制造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US5521428A (zh) |
EP (1) | EP0623953A3 (zh) |
JP (1) | JP3681008B2 (zh) |
KR (1) | KR100325277B1 (zh) |
CN (1) | CN1098558A (zh) |
SG (1) | SG46361A1 (zh) |
TW (1) | TW276357B (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100363863C (zh) * | 2004-09-13 | 2008-01-23 | 奇鋐科技股份有限公司 | 计算机机壳 |
CN100409418C (zh) * | 2006-08-01 | 2008-08-06 | 上海凯虹科技电子有限公司 | Qfn芯片封装工艺 |
CN105742269A (zh) * | 2014-12-26 | 2016-07-06 | 瑞萨电子株式会社 | 半导体装置及半导体装置的制造方法 |
CN110672171A (zh) * | 2012-02-21 | 2020-01-10 | 日立汽车系统株式会社 | 热式空气流量测定装置 |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5714792A (en) * | 1994-09-30 | 1998-02-03 | Motorola, Inc. | Semiconductor device having a reduced die support area and method for making the same |
US5701090A (en) * | 1994-11-15 | 1997-12-23 | Mitsubishi Denki Kabushiki Kaisha | Data output circuit with reduced output noise |
JP2767404B2 (ja) * | 1994-12-14 | 1998-06-18 | アナムインダストリアル株式会社 | 半導体パッケージのリードフレーム構造 |
EP0833382B1 (en) * | 1996-09-30 | 2005-11-30 | STMicroelectronics S.r.l. | Plastic package for electronic devices |
KR100205353B1 (ko) * | 1996-12-27 | 1999-07-01 | 구본준 | 프리-몰드 패들을 갖는 반도체 패키지 제조 공정용 리드 프레임 |
DE19704343A1 (de) * | 1997-02-05 | 1998-08-20 | Siemens Ag | Montageverfahren für Halbleiterbauelemente |
TW330337B (en) * | 1997-05-23 | 1998-04-21 | Siliconware Precision Industries Co Ltd | Semiconductor package with detached die pad |
KR100475335B1 (ko) * | 1997-08-12 | 2005-05-19 | 삼성전자주식회사 | 반도체칩패키지 |
US6048744A (en) | 1997-09-15 | 2000-04-11 | Micron Technology, Inc. | Integrated circuit package alignment feature |
US6028350A (en) * | 1998-02-09 | 2000-02-22 | Advanced Micro Devices, Inc. | Lead frame with strip-shaped die bonding pad |
JP3862411B2 (ja) * | 1998-05-12 | 2006-12-27 | 三菱電機株式会社 | 半導体装置の製造方法及びその構造 |
US5998857A (en) * | 1998-08-11 | 1999-12-07 | Sampo Semiconductor Corporation | Semiconductor packaging structure with the bar on chip |
SG92624A1 (en) * | 1999-02-09 | 2002-11-19 | Inst Of Microelectronics | Lead frame for an integrated circuit chip (integrated circuit peripheral support) |
US6331728B1 (en) * | 1999-02-26 | 2001-12-18 | Cypress Semiconductor Corporation | High reliability lead frame and packaging technology containing the same |
TW410452B (en) * | 1999-04-28 | 2000-11-01 | Siliconware Precision Industries Co Ltd | Semiconductor package having dual chips attachment on the backs and the manufacturing method thereof |
US6265761B1 (en) | 1999-05-07 | 2001-07-24 | Maxim Integrated Products, Inc. | Semiconductor devices with improved lead frame structures |
KR20010111767A (ko) * | 2000-06-13 | 2001-12-20 | 마이클 디. 오브라이언 | 반도체 패키지 제조용 리드프레임 |
US6696749B1 (en) * | 2000-09-25 | 2004-02-24 | Siliconware Precision Industries Co., Ltd. | Package structure having tapering support bars and leads |
SG112799A1 (en) | 2000-10-09 | 2005-07-28 | St Assembly Test Services Ltd | Leaded semiconductor packages and method of trimming and singulating such packages |
US6686258B2 (en) | 2000-11-02 | 2004-02-03 | St Assembly Test Services Ltd. | Method of trimming and singulating leaded semiconductor packages |
US6448107B1 (en) * | 2000-11-28 | 2002-09-10 | National Semiconductor Corporation | Pin indicator for leadless leadframe packages |
DE10104868A1 (de) | 2001-02-03 | 2002-08-22 | Bosch Gmbh Robert | Mikromechanisches Bauelement sowie ein Verfahren zur Herstellung eines mikromechanischen Bauelements |
US6991960B2 (en) | 2001-08-30 | 2006-01-31 | Micron Technology, Inc. | Method of semiconductor device package alignment and method of testing |
TWI267958B (en) * | 2002-11-21 | 2006-12-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with stilts for supporting dice |
JP2005079181A (ja) * | 2003-08-28 | 2005-03-24 | Matsushita Electric Ind Co Ltd | リードフレーム、それを用いた樹脂封止型半導体装置およびその製造方法 |
KR100586699B1 (ko) * | 2004-04-29 | 2006-06-08 | 삼성전자주식회사 | 반도체 칩 패키지와 그 제조 방법 |
US20070126445A1 (en) * | 2005-11-30 | 2007-06-07 | Micron Technology, Inc. | Integrated circuit package testing devices and methods of making and using same |
US20080157299A1 (en) * | 2006-12-28 | 2008-07-03 | Jeffery Gail Holloway | Microelectronic Assembly Using Chip-On-Lead (COL) and Cantilever Leads |
US7812430B2 (en) * | 2008-03-04 | 2010-10-12 | Powertech Technology Inc. | Leadframe and semiconductor package having downset baffle paddles |
US9754861B2 (en) * | 2014-10-10 | 2017-09-05 | Stmicroelectronics Pte Ltd | Patterned lead frame |
US10109563B2 (en) | 2017-01-05 | 2018-10-23 | Stmicroelectronics, Inc. | Modified leadframe design with adhesive overflow recesses |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1907075B2 (de) * | 1969-02-13 | 1974-07-04 | Semikron Gesellschaft Fuer Gleichrichterbau Und Elektronik Mbh, 8500 Nuernberg | Verfahren zur Herstellung von Halbleiter-Kleingleichrichtern |
FR2436505A1 (fr) * | 1978-09-12 | 1980-04-11 | Radiotechnique Compelec | Dispositif optoelectronique a emetteur et recepteur couples |
JPS6042852A (ja) * | 1983-08-18 | 1985-03-07 | Toshiba Corp | リ−ドフレ−ム |
US4612564A (en) * | 1984-06-04 | 1986-09-16 | At&T Bell Laboratories | Plastic integrated circuit package |
US4829362A (en) * | 1986-04-28 | 1989-05-09 | Motorola, Inc. | Lead frame with die bond flag for ceramic packages |
JPS6340352A (ja) * | 1986-08-05 | 1988-02-20 | Furukawa Electric Co Ltd:The | 電子部品用リ−ドフレ−ム |
US4766478A (en) * | 1986-09-02 | 1988-08-23 | Dennis Richard K | Lead frame for semi-conductor device and process of connecting same |
JPS6480051A (en) * | 1987-09-21 | 1989-03-24 | Hitachi Ltd | Electric device |
JPH01161743A (ja) * | 1987-12-17 | 1989-06-26 | Toshiba Corp | 半導体装置 |
US4868635A (en) * | 1988-01-13 | 1989-09-19 | Texas Instruments Incorporated | Lead frame for integrated circuit |
US4994895A (en) * | 1988-07-11 | 1991-02-19 | Fujitsu Limited | Hybrid integrated circuit package structure |
JP2602076B2 (ja) * | 1988-09-08 | 1997-04-23 | 三菱電機株式会社 | 半導体装置用リードフレーム |
US4924291A (en) * | 1988-10-24 | 1990-05-08 | Motorola Inc. | Flagless semiconductor package |
JPH02273961A (ja) * | 1989-04-14 | 1990-11-08 | Fujitsu Ltd | リードフレームおよびそれを用いた混成集積回路 |
US5021864A (en) * | 1989-09-05 | 1991-06-04 | Micron Technology, Inc. | Die-mounting paddle for mechanical stress reduction in plastic IC packages |
JPH03139811A (ja) * | 1989-10-26 | 1991-06-14 | Tama Electric Co Ltd | リードフレーム |
JPH0415947A (ja) * | 1990-05-09 | 1992-01-21 | Hitachi Cable Ltd | 半導体装置用リードフレームおよび半導体装置 |
US5161304A (en) * | 1990-06-06 | 1992-11-10 | Sgs-Thomson Microelectronics, Inc. | Method for packaging an electronic circuit device |
JP2501953B2 (ja) * | 1991-01-18 | 1996-05-29 | 株式会社東芝 | 半導体装置 |
-
1994
- 1994-02-02 TW TW083100866A patent/TW276357B/zh not_active IP Right Cessation
- 1994-02-17 EP EP94102398A patent/EP0623953A3/en not_active Ceased
- 1994-02-17 SG SG1996003527A patent/SG46361A1/en unknown
- 1994-03-09 JP JP06435294A patent/JP3681008B2/ja not_active Expired - Lifetime
- 1994-03-21 CN CN94103951A patent/CN1098558A/zh active Pending
- 1994-03-22 KR KR1019940005694A patent/KR100325277B1/ko not_active IP Right Cessation
- 1994-08-22 US US08/293,402 patent/US5521428A/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100363863C (zh) * | 2004-09-13 | 2008-01-23 | 奇鋐科技股份有限公司 | 计算机机壳 |
CN100409418C (zh) * | 2006-08-01 | 2008-08-06 | 上海凯虹科技电子有限公司 | Qfn芯片封装工艺 |
CN110672171A (zh) * | 2012-02-21 | 2020-01-10 | 日立汽车系统株式会社 | 热式空气流量测定装置 |
CN105742269A (zh) * | 2014-12-26 | 2016-07-06 | 瑞萨电子株式会社 | 半导体装置及半导体装置的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP0623953A2 (en) | 1994-11-09 |
JPH06302755A (ja) | 1994-10-28 |
KR100325277B1 (ko) | 2002-06-20 |
SG46361A1 (en) | 1998-02-20 |
JP3681008B2 (ja) | 2005-08-10 |
EP0623953A3 (en) | 1995-05-31 |
TW276357B (zh) | 1996-05-21 |
KR940022767A (ko) | 1994-10-21 |
US5521428A (en) | 1996-05-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1098558A (zh) | 无支撑板的半导体器件及其制造方法 | |
CN101866901B (zh) | 半导体器件及其制造方法 | |
US7402459B2 (en) | Quad flat no-lead (QFN) chip package assembly apparatus and method | |
JPS60208847A (ja) | 表面実装型icに内在する水分の排出方法 | |
US4706811A (en) | Surface mount package for encapsulated tape automated bonding integrated circuit modules | |
CN104916606A (zh) | 半导体装置及其制造方法 | |
CN107636828A (zh) | 集成的夹具和引线以及制作电路的方法 | |
US11502045B2 (en) | Electronic device with step cut lead | |
US6078099A (en) | Lead frame structure for preventing the warping of semiconductor package body | |
KR950024315A (ko) | 반도체용 리드 프레임 및 그 제조방법 | |
CN103021892B (zh) | 无外引脚半导体封装构造及其制造方法与导线架条 | |
US20090098686A1 (en) | Method of forming premolded lead frame | |
CN1098557A (zh) | 带有x形管芯支托的半导体器件及其制造方法 | |
US20070205493A1 (en) | Semiconductor package structure and method for manufacturing the same | |
JPH11145369A (ja) | リードフレームおよびそれを用いた半導体装置ならびにその製造方法 | |
JP2976199B2 (ja) | ダイパッドを有する半導体パッケージ用リードフレーム | |
CN216354192U (zh) | 一种半导体芯片打线结构 | |
US11227820B2 (en) | Through hole side wettable flank | |
US20240096769A1 (en) | Method for manufacturing a semiconductor package assembly as well as a semiconductor package assembly obtained with this method | |
US20150279765A1 (en) | Semiconductor device having lead frame with notched inner leads | |
US20150028468A1 (en) | Non-leaded type semiconductor package and method of assembling same | |
JPH07193180A (ja) | 樹脂封止型半導体装置 | |
JPH08288427A (ja) | 半導体装置 | |
JPH02130864A (ja) | リードフレームのダイパッド構造 | |
JPH03225944A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: FREEDOM SEMICONDUCTORS CO. Free format text: FORMER OWNER: MOTOROLA, INC. Effective date: 20050902 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20050902 Address after: Texas in the United States Applicant after: FreeScale Semiconductor Address before: Illinois, USA Applicant before: Motorola, Inc. |
|
C12 | Rejection of a patent application after its publication | ||
RJ01 | Rejection of invention patent application after publication |