CN216354192U - 一种半导体芯片打线结构 - Google Patents

一种半导体芯片打线结构 Download PDF

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CN216354192U
CN216354192U CN202123082194.9U CN202123082194U CN216354192U CN 216354192 U CN216354192 U CN 216354192U CN 202123082194 U CN202123082194 U CN 202123082194U CN 216354192 U CN216354192 U CN 216354192U
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chip
frame
semiconductor chip
frame body
mounting groove
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吴江
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Xinzhou Integrated Circuit Shanghai Co ltd
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Xinzhou Integrated Circuit Shanghai Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

本实用新型揭示了一种半导体芯片打线结构，包括框架主体以及设置在所述框架主体上的焊接平台，所述焊接平台上设置有至少一个第一芯片，所述第一芯片远离所述焊接平台的一侧表面上通过导线连接有框架引脚，所述框架引脚设置在所述框架主体上，所述框架引脚远离所述框架主体一侧外壁上设置有第二芯片。本实用新型便于将芯片的底部信号引出，且对芯片提供一定的保护能力。

Description

一种半导体芯片打线结构
技术领域
本实用新型涉及半导体封装领域，特别是涉及一种半导体芯片打线结构。
背景技术
半导体封装是指将通过测试的晶圆按照产品型号及功能需求加工得到独立芯片的过程。封装过程为：来自晶圆前道工艺的晶圆通过划片工艺后被切割为小的晶片，然后将切割好的晶片贴装到相应的引线框架上，再利用超细的金属导线或者导电性树脂将晶片的接合焊盘连接到基板的相应引脚；然后再对独立的晶片用塑料外壳加以封装保护，塑封之后还要进行一系列操作，封装完成后进行成品测试等。在生产过程中，需要对半导体框架进行切割处理，使其形成需要的形状。
但是，半导体芯片的框架类封装类型受限于自身的结构，框架基底整体铺铜用以承载芯片，很难做到多芯片底部信号的引出，只能短接接地，存在一定缺陷。
实用新型内容
本实用新型的目的在于，提供一种半导体芯片打线结构，以实现将芯片底部信号引出。
为解决上述技术问题，本实用新型提供一种半导体芯片打线结构，包括框架主体以及设置在所述框架主体上的焊接平台，所述焊接平台上设置有至少一个第一芯片，所述第一芯片远离所述焊接平台的一侧表面上通过导线连接有框架引脚，所述框架引脚设置在所述框架主体上，所述框架引脚远离所述框架主体一侧外壁上设置有第二芯片。
进一步的，所述框架引脚远离所述框架主体一侧表面上设置有安装槽。
进一步的，所述安装槽上部均设置为弧形。
进一步的，所述第二芯片底面积小于所述安装槽底面积。
相比于现有技术，本实用新型至少具有以下有益效果：将第二芯片安装在框架主体上原有的框架引脚上，便于将第二芯片的底部信号引出；在框架引脚上设置安装槽，便于第二芯片的安装，且通过安装槽对第二芯片提供一定的保护能力，避免第二芯片在封装时受损。
附图说明
图1为本实用新型一个实施例中的整体结构示意图；
图2为本实用新型一个实施例中的引脚结构剖视图；
图3为本实用新型一个实施例中的单个芯片底部信号引出结构示意图；
图4为本实用新型一个实施例中的多个芯片连接的底部信号引出结构示意图。
具体实施方式
下面将结合示意图对本实用新型的半导体芯片打线结构进行更详细的描述，其中表示了本实用新型的优选实施例，应该理解本领域技术人员可以修改在此描述的本实用新型，而仍然实现本实用新型的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本实用新型的限制。
在下列段落中参照附图以举例方式更具体地描述本实用新型。根据下面说明和权利要求书，本实用新型的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本实用新型实施例的目的。
如图1所示，本实用新型实施例提出了一种半导体芯片打线结构，包括框架主体1以及设置在所述框架主体1上的焊接平台2，所述焊接平台2上设置有至少一个第一芯片3，所述第一芯片3远离所述焊接平台2的一侧表面上通过导线4连接有框架引脚5，所述框架引脚5设置在所述框架主体1上，所述框架引脚5远离所述框架主体1一侧外壁上设置有第二芯片6。将需要引出底部信号的第二芯片6安装在框架引脚5上表面，通过该框架引脚5将第二芯片6的信号引出，以达到预期功能。
以下列举所述半导体芯片打线结构的较优实施例，以清楚的说明本实用新型的内容，应当明确的是，本实用新型的内容并不限制于以下实施例，其他通过本领域普通技术人员的常规技术手段的改进亦在本实用新型的思想范围之内。
请参考图2，所述框架引脚5远离所述框架主体1一侧表面上设置有安装槽51。在本实施方式中，通过安装槽51的设置，在第二芯片6安装在安装槽51内时，利用安装槽51对第二芯片6进行限位，且通过安装槽51对第二芯片6进行保护，避免第二芯片6破损，导致电气性能受到影响。
所述安装槽51上部均设置为弧形。在本实施方式中，将安装槽51上部设置为弧形，使得安装槽51上部具有引导作用，便于将第二芯片6置于安装槽51内。
所述第二芯片6底面积小于所述安装槽51底面积。在本实施方式中，框架主体1在塑封后，外部的封装料对框架引脚5进行挤压，产生内部应力，设置安装槽51尺寸大于第二芯片6尺寸，使得安装槽51具有一定的缓冲保护能力，避免第二芯片6受压损坏。
具体的，请参考图3以及图4，分别为单芯片底部信号引出结构示意以及多个芯片连接的底部信号引出结构示意，通过第二芯片6底部连接的框架引脚5引出第二芯片6的底部信号。
综上所述，将第二芯片6安装在框架主体1上原有的框架引脚5上，便于将第二芯片6的底部信号引出；在框架引脚5上设置安装槽51，便于第二芯片6的安装，且通过安装槽51对第二芯片6提供一定的保护能力，避免第二芯片6在封装时受损。
显然，本领域的技术人员可以对本实用新型进行各种改动和变型而不脱离本实用新型的精神和范围。这样，倘若本实用新型的这些修改和变型属于本实用新型权利要求及其等同技术的范围之内，则本实用新型也意图包含这些改动和变型在内。

Claims (4)

1.一种半导体芯片打线结构，其特征在于，包括框架主体以及设置在所述框架主体上的焊接平台，所述焊接平台上设置有至少一个第一芯片，所述第一芯片远离所述焊接平台的一侧表面上通过导线连接有框架引脚，所述框架引脚设置在所述框架主体上，所述框架引脚远离所述框架主体一侧外壁上设置有第二芯片。
2.如权利要求1所述的半导体芯片打线结构，其特征在于，所述框架引脚远离所述框架主体一侧表面上设置有安装槽。
3.如权利要求2所述的半导体芯片打线结构，其特征在于，所述安装槽上部均设置为弧形。
4.如权利要求2所述的半导体芯片打线结构，其特征在于，所述第二芯片底面积小于所述安装槽底面积。
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