CN109493908A - 非易失性存储器胞的编程方法 - Google Patents
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Abstract
本发明提供一种非易失性存储器胞的编程方法。所述非易失性存储器胞包括基板,以及设置于基板上且互相串联耦合的选择晶体管、跟随性栅极晶体管及包括第一栅极氧化层的反熔丝晶体管。所述编程方法包括向非易失性存储器胞施加可变直流电压源,所述可变直流电压源包括于第一栅极氧化层内形成陷获路径的至少一高电压部分以及用于使陷获路径结晶成硅丝的至少一低电压部分。
Description
技术领域
本发明涉及一种编程电子装置的方法,且特别涉及一种非易失性存储器胞的编程方法。
背景技术
非易失性存储器(Nonvolatile memory,NVM)因为即使在没有供应电源的情况下,仍可以保存数据,故而广泛用于各种电子装置。
通常,非易失性存储器可以藉由浮置栅极晶体管或反熔丝晶体管(anti-fusetransistors)来实现。
以浮置栅极晶体管实施的非易失性存储器而言,藉由使用合适的控制机制,热载子可以注入浮置栅极晶体管的浮置栅极或自浮置栅极射出。因此,由浮置栅极晶体管组成的非易失性存储器可以用作多次编程存储器。
以反熔丝晶体管实施的非易失性存储器而言,反熔丝晶体管的存储状态是根据反熔丝晶体管的栅极氧化层的凿穿状态判断的。在栅极氧化层被凿穿后,栅极氧化层无法恢复。因此,由反熔丝晶体管组成的非易失性存储器可作为一次性编程存储器。
然而,在操作一次性编程存储器的既有方法中,由于栅极氧化物积集度的变化和凿穿后的栅极氧化物特性,不仅造成功率的浪费,芯片的可靠性也会受到影响。
发明内容
因此,本发明提出一种非易失性存储器胞的编程方法,藉由提供由多个部分所组成的可变直流电压源(DC voltage source),以改善功率消耗并提升芯片的可靠性。
根据本发明一实施例的一种非易失性存储器胞的编程方法包括数个步骤。所述非易失性存储器胞包括基板,以及设置于基板上且互相串联耦合的选择晶体管(selecttransistor)、跟随性栅极晶体管(following gate transistor)及包括第一栅极氧化层的反熔丝晶体管(anti-fuse transistor)。所述方法包括:向所述非易失性存储器胞施加可变直流电压源,所述可变直流电压源包括于第一栅极氧化层内形成陷获路径(trappingpath)的至少一高电压部分以及用于使所述陷获路径结晶成硅丝(silicon filament)的至少一低电压部分。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1是依照本发明一实施例所绘示的一种非易失性存储器胞的剖面示意图。
图2是依照本发明一实施例的编程操作的波形图。
【符号说明】
10:非易失性存储器胞
100:基板
102:选择晶体管
102a:选择栅极
102b:第二栅极氧化层
104:跟随性栅极晶体管
104a:跟随性栅极
104b:第三栅极氧化层
106:反熔丝晶体管
106a:反熔丝栅极
106b:第一栅极氧化层
108:P型井
110a、110b、110c、110d:掺杂区
112:隔离结构
SL:选择线
T1、T2、T3:厚度
VPP1:高电压部分
VPP2:低电压部分
具体实施方式
现在将详细参照本发明的下列实施例,其显示在图式中。在可能的情况下,图式和说明书中使用相同的元件符号来表是相同或相似的构件。再者,为了清楚起见,各构件及其相对尺寸并未按照比例绘制。
图1是依照本发明一实施例所绘示的一种非易失性存储器胞的剖面示意图。
请参照图1,非易失性存储器胞10至少包括一基板100、一选择晶体管102、一跟随性栅极晶体管104以及一反熔丝晶体管106。选择晶体管102、跟随性栅极晶体管104与反熔丝晶体管106设置于基板100上,且它们互相串联耦合。举例来说,选择晶体管102、跟随性栅极晶体管104与反熔丝晶体管106皆是位于基底100中的一低压(low voltage,LV)P型井108内的NMOS,且每个NMOS包括一栅极、位于栅极下的一低压栅极氧化层以及位于栅极旁边的低压P型井区108中的两个n+掺杂区。特别是,选择晶体管102包括一选择栅极102a、位于选择栅极102a下的一第二栅极氧化层102b,以及位于选择栅极102a旁边的基底100中的两个掺杂区110a、110b;跟随性栅极晶体管104包括一跟随性栅极104a、位于跟随性栅极104a下方的一第三栅极氧化层104b,以及位于跟随性栅极104a旁边的基底100中的两个掺杂区110b、110c;反熔丝晶体管106包括一反熔丝栅极106a、位于反熔丝栅极106a下方的一第一栅极氧化层106b,以及位于反熔丝栅极106a旁边的基底100中的两个掺杂区110c、110d。选择线SL连接至掺杂区110a,且非易失性存储器胞10被隔离结构112围绕,其中隔离结构112例如浅渠沟隔离(ShallowTrench Isolation,STI)。在一实施例中,第三栅极氧化层104b的厚度T3等于第二栅极氧化层102b的厚度T2;或者,第一栅极氧化层106b的厚度T1等于第二栅极氧化层102b的厚度T2。
在一实施例中,对非易失性存储器胞10进行编程方法包括向非易失性存储器胞10施加一可变直流电压源,其中从所述可变直流电压源输出的波形图案包括至少一高电压部分以及至少一低电压部分。文中仅显示一个高电压部分VPP1和一个低电压部分VPP2作为简化示例。
请参照图2,在初始阶段,将高电压部分VPP1施加到反熔丝晶体管106的反熔丝栅极106a,如此一来,在反熔丝栅极106a下方的第一栅极氧化层106b内会形成一陷获路径。然后,将低电压部分VPP2也施加到反熔丝晶体管106的反熔丝栅极106a,如此一来,所述陷获路径会结晶成一硅丝。在编程期间,选择线SL是接地的。
在一实施例中,低电压部分VPP2的振幅为高电压部分VPP1的振幅的1/4至3/4倍;较佳为,低电压部分VPP2的振幅为高电压部分VPP1的振幅的2/3倍。在这样的比例下,编程能力可以增强到实现稳定地硬击穿(hardbreakdown),进而增进元件效能。
在一实施例中,高电压部分VPP1的持续时间等于低电压部分VPP2的持续时间。然而,本发明并不限于此。在另一实施例中,高电压部分VPP1的持续时间可以与低电压部分VPP2的持续时间略微不同。举例来说,至少一个高压部分的持续时间可以短于至少一个低压部分的持续时间;较佳地,至少一个高压部分的持续时间与至少一个低压部分的持续时间的比例小于1/2。
在又一实施例中,反熔丝栅极106a、第一栅极氧化层106b和P型井108在编程前可一起作为电容器。在编程后,反熔丝栅极106a、第一栅极氧化层106b和P型井108可一起作为电阻器。较佳的是,第一栅极氧化层106b的厚度T1要够薄,以便容易经由通过预定的高电压部分(例如高压部分VPP1)而被凿穿。
综上所述,依据本发明的编程操作可以藉由可变直流电压源改善功率消耗与提升芯片的可靠度。
虽然本发明已以实施例公开如上,然其并非用以限定本发明,本领域技术人员在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视所附权利要求书界定范围为准。
Claims (9)
1.一种非易失性存储器胞的编程方法,所述非易失性存储器胞具有基底,以及设置于所述基底上且互相串联耦合的选择晶体管、跟随性栅极晶体管及反熔丝晶体管,所述反熔丝晶体管包括第一栅极氧化层,所述编程方法的特征在于,包括:
向所述非易失性存储器胞施加可变直流电压源,所述可变直流电压源包括于所述第一栅极氧化层内形成陷获路径的至少一高电压部分以及用于使所述陷获路径结晶成硅丝的至少一低电压部分。
2.如权利要求1所述的非易失性存储器胞的编程方法,其中所述反熔丝晶体管为电容器。
3.如权利要求1所述的非易失性存储器胞的编程方法,其中所述选择晶体管包括第二栅极氧化层,所述跟随性栅极晶体管包括第三栅极氧化层,其中所述第三栅极氧化层的厚度等于所述第二栅极氧化层的厚度。
4.如权利要求1所述的非易失性存储器胞的编程方法,其中所述选择晶体管包括第二栅极氧化层,所述第一栅极氧化层的厚度等于所述第二栅极氧化层的厚度。
5.如权利要求1所述的非易失性存储器胞的编程方法,其中所述至少一高电压部分的持续时间等于所述至少一低电压部分的持续时间。
6.如权利要求1所述的非易失性存储器胞的编程方法,其中所述至少一高电压部分的持续时间短于所述至少一低电压部分的持续时间。
7.如权利要求1所述的非易失性存储器胞的编程方法,其中所述至少一高电压部分的持续时间与所述至少一低电压部分的持续时间的比例小于1/2。
8.如权利要求1所述的非易失性存储器胞的编程方法,其中所述至少一低电压部分的振幅为所述至少一高电压部分的振幅的1/4至3/4倍。
9.如权利要求1所述的非易失性存储器胞的编程方法,其中所述至少一低电压部分的振幅为所述至少一高电压部分的振幅的2/3倍。
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CN112234063B (zh) * | 2019-11-08 | 2024-02-20 | 珠海创飞芯科技有限公司 | 一种反熔丝一次性可编程存储单元 |
CN112234061A (zh) * | 2020-01-15 | 2021-01-15 | 珠海创飞芯科技有限公司 | 一种反熔丝一次性可编程存储单元 |
CN112234061B (zh) * | 2020-01-15 | 2024-03-19 | 珠海创飞芯科技有限公司 | 一种反熔丝一次性可编程存储单元 |
CN112234062A (zh) * | 2020-02-12 | 2021-01-15 | 珠海创飞芯科技有限公司 | 一种反熔丝一次性可编程存储单元 |
CN112234062B (zh) * | 2020-02-12 | 2024-05-24 | 珠海创飞芯科技有限公司 | 一种反熔丝一次性可编程存储单元 |
CN112635468A (zh) * | 2020-03-12 | 2021-04-09 | 珠海创飞芯科技有限公司 | 一种反熔丝一次性可编程存储单元 |
CN112635468B (zh) * | 2020-03-12 | 2024-02-13 | 珠海创飞芯科技有限公司 | 一种反熔丝一次性可编程存储单元 |
CN113496988A (zh) * | 2020-04-08 | 2021-10-12 | 长鑫存储技术有限公司 | 反熔丝单元及反熔丝阵列 |
WO2021203908A1 (zh) * | 2020-04-08 | 2021-10-14 | 长鑫存储技术有限公司 | 反熔丝单元及反熔丝阵列 |
CN113496988B (zh) * | 2020-04-08 | 2023-12-12 | 长鑫存储技术有限公司 | 反熔丝单元及反熔丝阵列 |
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