TWI677152B - 物理不可複製函數單元及物理不可複製函數單元的操作方法 - Google Patents

物理不可複製函數單元及物理不可複製函數單元的操作方法 Download PDF

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TWI677152B
TWI677152B TW107128902A TW107128902A TWI677152B TW I677152 B TWI677152 B TW I677152B TW 107128902 A TW107128902 A TW 107128902A TW 107128902 A TW107128902 A TW 107128902A TW I677152 B TWI677152 B TW I677152B
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voltage
terminal
coupled
fuse transistor
transistor
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TW201914141A (zh
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陳信銘
Hsin-Ming Chen
吳孟益
Meng-Yi Wu
黃柏豪
Po-Hao Huang
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力旺電子股份有限公司
Ememory Technology Inc.
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
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Abstract

物理不可複製函數單元包含反熔絲電晶體及控制電路。反熔絲電晶體具有第一端,第二端,及閘極端。控制電路耦接於反熔絲電晶體。在註冊操作中,控制電路施加註冊電壓至反熔絲電晶體的閘極端,並施加參考電壓至反熔絲電晶體的第一端及第二端。註冊電壓高於參考電壓,且註冊電壓高到足以在反熔絲電晶體的閘極端至第一端或在反熔絲電晶體的閘極端至第二端之間產生出穿鑿路徑。

Description

物理不可複製函數單元及物理不可複製函數單元的操作方法
本發明是有關於一種物理不可複製函數單元,特別是一種具有單一反熔絲電晶體的物理不可複製函數單元。
物理不可複製函數(physically unclonable function,PUF)的積體電路因其原生的特質,而常被用來保護系統免於物理攻擊,並提高逆向工程或駭入系統所需的跨越門檻,藉以增強電子裝置的安全性。由於積體電路在製造過程中,會產生隨機而不可控制的物理參數特徵,使得物理不可複製函數能夠據以產生獨特的位元字串。製造過程的變異可能來自非常微小而無法避免的製程控制變化、材料組成及/或環境參數的偏移。這些無法避免且無法預測的變化會被物理不可複製函數放大,進而產生獨特的位元字串。
在先前技術中,物理不可複製函數單元常可以透過兩個儲存互補位元的元件來實作,藉以讓製程中所產生的變異比較容易被放大。然而,這種物理不可複製函數的技術也存在著一些破解的方法,使得其中儲存的資訊可能會被竊取,而讓資訊安全出現漏洞。舉例來說,被動式電壓對比的檢驗技術(passive voltage contrast inspection)就可能會被用來破解物理不可複製函數。也就是說, 對手可利用透射電子顯微鏡(transmission electron microscope,TEM)或掃描電子顯微鏡(scanning electron microscope,SEM)設備將電子束施加在物理不可複製函數單元中的兩個元件。更具體地說,如果物理不可複製函數單元中的元件是利用浮接閘極來儲存資訊,則對手可以透過將電子束射向浮接閘極,並利用電子感測器來吸收浮接閘極所反射的二次電子以對浮接閘極進行掃描。如果浮接閘極先前被充了負電荷,則在電子感測器吸收了由浮接閘極所反射的二次電子之後,將呈現出明亮的圖像。然而若浮接閘極並未充入電子,則電子感測器將呈現黯淡的圖像。因此,透過比較電子感測器所產生的圖像,就可以獲得物理不可複製函數單元中的位元資訊。因此,即使物理不可複製函數單元能夠產生難以預測的位元字串,資訊安全的威脅也仍然存在。
本發明之一實施例提供一種物理不可複製函數(physically unclonable function,PUF)單元。物理不可複製函數單元包含反熔絲電晶體及控制電路。
反熔絲電晶體具有第一端,第二端及閘極端。控制電路耦接於反熔絲電晶體。控制電路在註冊操作中,施加註冊電壓至反熔絲電晶體的閘極端及施加參考電壓至反熔絲電晶體的第一端及第二端。
註冊電壓高於參考電壓,且註冊電壓高到足以在反熔絲電晶體的閘極端至第一端或在反熔絲電晶體的閘極端至第二端之間產生出穿鑿路徑。
本發明之另一實施例提供一種物理不可複製函數單元的操作方法,而物理不可複製函數單元包含反熔絲電晶體及耦接於反熔絲電晶體之控制電路。
物理不可複製函數單元的操作方法包含在註冊操作時,控制電路提供註冊電壓至反熔絲電晶體的閘極端,及控制電路提供參考電壓至反熔絲電晶 體的第一端及第二端。
註冊電壓高於參考電壓,且註冊電壓高到足以在反熔絲電晶體的閘極端至第一端或在反熔絲電晶體的閘極端至第二端之間產生出穿鑿路徑。
100、200‧‧‧物理不可複製函數單元
110、210‧‧‧反熔絲電晶體
120、220‧‧‧控制電路
121‧‧‧電壓源
122‧‧‧閘極控制P型電晶體
123‧‧‧閘極控制N型電晶體
124‧‧‧第一註冊電晶體
125‧‧‧第二註冊電晶體
130、230‧‧‧差動感測電路
132、232‧‧‧第一反相器
134、234‧‧‧第二反相器
SG‧‧‧閘極選擇線
BLP‧‧‧註冊位元線
WLP‧‧‧註冊字元線
BLR‧‧‧第一讀取位元線
BLR’‧‧‧第二讀取位元線
VL‧‧‧低操作電壓
VH‧‧‧高操作電壓
VP‧‧‧註冊電壓
VR‧‧‧讀取電壓
V0‧‧‧參考電壓
226‧‧‧第一讀取電晶體
227‧‧‧第二讀取電晶體
WLR‧‧‧讀取字元線
300‧‧‧方法
S310至S340‧‧‧步驟
第1圖為本發明一實施例之物理不可複製函數單元的示意圖。
第2圖為第1圖之物理不可複製函數單元在註冊操作時所接收到的電壓。
第3圖為第1圖之物理不可複製函數單元在註冊操作時所接收到的電壓。
第4圖為本發明另一實施例之物理不可複製函數單元的示意圖。
第5圖為第1圖之物理不可複製函數單元的操作方法的流程圖。
第1圖為本發明一實施例之物理不可複製函數單元100的示意圖。物理不可複製函數單元100可包含反熔絲電晶體110,控制電路120及差動感測電路130。
反熔絲電晶體110具有第一端、第二端及閘極端。反熔絲電晶體110的第一端及第二端可以是反熔絲電晶體110的源極端及汲極端。控制電路120可耦接於反熔絲電晶體110。物理不可複製函數單元100可用來產生系統為維護資安所需的亂數位元或隨機碼。為了產生亂數位元或隨機碼,物理不可複製函數單元100可執行註冊操作(enroll)。
第2圖為物理不可複製函數單元100在註冊操作時所接收到的電壓。在註冊操作中,控制電路120可以施加註冊電壓VP至反熔絲電晶體110的閘極端,並施加參考電壓V0至反熔絲電晶體110的第一端及第二端。註冊電壓VP高 於參考電壓V0,且註冊電壓VP可高到足以在反熔絲電晶體110的閘極端至第一端或在反熔絲電晶體110的閘極端至第二端之間產生出穿鑿路徑。舉例來說,在有些實施例中,註冊電壓VP可為6V,參考電壓V0可為系統的接地電壓或0V。
透過在反熔絲電晶體110上施加大電壓,就能夠在反熔絲電晶體110的閘極氧化層上產生出低阻抗的穿鑿路徑,而這個穿鑿路徑會與反熔絲電晶體110在製造過程中於閘極氧化層所製造出的局部原生特徵有關,例如氧化層的品質,局部缺陷的分佈以及氧化層的厚薄...等等。通常來說,由於放電電流會流經阻抗最低的路徑,因此在反熔絲電晶體110的閘極端至第一端或在反熔絲電晶體110的閘極端至第二端之間最容易產生穿鑿路徑。
如果穿鑿路徑是形成在反熔絲電晶體110的閘極端至第一端之間,大部分的電流就會因為其低阻抗的特性而流過穿鑿路徑,因此會減輕反熔絲電晶體110的閘極端至第二端之間所承受的電壓。也就是說,一旦穿鑿路徑形成,這條低阻抗的路徑就會避免氧化層被再次穿鑿,因此一般來說,在註冊操作中,反熔絲電晶體110的氧化層將只會有一條穿鑿路徑。
在第1圖中,控制電路120包含電壓源121、閘極控制P型電晶體122、閘極控制N型電晶體123、第一註冊電晶體124及第二註冊電晶體125。閘極控制P型電晶體122具有第一端、第二端及控制端,閘極控制P型電晶體122的第一端耦接於電壓源121,閘極控制P型電晶體122的第二端耦接於反熔絲電晶體110的閘極端,閘極控制P型電晶體122的控制端耦接於閘極選擇線SG。閘極控制N型電晶體123具有第一端、第二端及控制端,閘極控制N型電晶體123的第一端耦接於電壓源121,閘極控制N型電晶體123的第二端耦接於反熔絲電晶體110的閘極端,而閘極控制N型電晶體123的控制端耦接於閘極選擇線SG。第一註冊電晶體124具有第一端、第二端及控制端,第一註冊電晶體124的第一端耦接於反熔絲電晶體110的第一端,第一註冊電晶體124的第二端耦接於註冊位元線BLP,第一 註冊電晶體124的控制端耦接於註冊字元線WLP。第二註冊電晶體125具有第一端、第二端及控制端,第二註冊電晶體125的第一端耦接於反熔絲電晶體110的第二端,第二註冊電晶體125的第二端耦接於註冊位元線BLP,第一註冊電晶體124的控制端耦接於註冊字元線WLP。
在第2圖中,閘極選擇線SG可在低操作電壓VL,註冊位元線BLP可在參考電壓V0,而註冊字元線WLP可在高操作電壓VH,高操作電壓VH可高於低操作電壓VL。此外,電壓源121可以在註冊操作中提供註冊電壓VP。在有些實施例中,低操作電壓VL可與參考電壓V0相等,而高操作電壓VH可高於參考電壓V0且低於註冊電壓VP。再者,高操作電壓VH可以高到足以導通第一註冊電晶體124及第二註冊電晶體125。
在此情況下,閘極控制P型電晶體122將會被導通,使得反熔絲電晶體110的閘極端可以經由閘極控制P型電晶體122接收到註冊電壓VP。此外,第一註冊電晶體124及第二註冊電晶體125也會被導通,因此反熔絲電晶體110的第一端及第二端將經由註冊位元線BLP接收到參考電壓V0。如此一來,反熔絲電晶體110將會承受巨大的電壓,因而在反熔絲電晶體110的閘極端至第一端或在反熔絲電晶體110的閘極端至第二端之間產生出穿鑿路徑。也就是說,每一個物理不可複製函數單元110都將在註冊操作中產生各自的穿鑿路徑。
在第1圖中,差動感測電路130可包含第一反相器132及第二反相器134。第一反相器132具有輸入端及輸出端,第一反相器132的輸入端可經由第一讀取位元線BLR耦接於反熔絲電晶體110的第一端,而第一反相器132的輸出端可經由第二讀取位元線BLR’耦接於反熔絲電晶體110的第二端。第二反相器134具有輸入端及輸出端,第二反相器134的輸入端可耦接第一反相器132的輸出端,而第二反相器134的輸出端可耦接於第一反相器132的輸入端。也就是說,差動感測電路130可以看做是自我回饋的閂鎖器。
第3圖為物理不可複製函數單元100在讀取操作時所接收到的電壓。在第3圖中,在讀取操作的過程中,閘極選擇線SG可以自低操作電壓VL變為高操作電壓VH,註冊位元線BLP可以在參考電壓V0,而註冊字元線WLP可以自高操作電壓VH變為低操作電壓VL。此外,電壓源121可在讀取操作時提供讀取電壓VR。
在有些實施例中,讀取電壓VR可低於註冊電壓VP,而不至於高到足以鑿穿反熔絲電晶體110的氧化層。舉例來說,註冊電壓VP可為6V,而讀取電壓VR可為2V。此外,讀取電壓VR可高於高操作電壓VH。因此閘極控制P型電晶體122會被導通,使得反熔絲電晶體110的閘極能夠經由閘極控制電晶體122接收到讀取電壓VR。此外,第一註冊電晶體124及第二註冊電晶體125會在讀取操作的初始階段先被導通,使得反熔絲電晶體110的第一端及第二端能夠先接收到參考電壓V0。在此情況下,倘若穿鑿路徑是形成於反熔絲電晶體110之閘極端與第一端之間,則大部分的電流都會經由穿鑿路徑而流至反熔絲電晶體110的第一端。
接著,註冊字元線WLP會自高操作電壓VH變為低操作電壓VL,而第一註冊電晶體124及第二註冊電晶體125會被截止。因此,自反熔絲電晶體110之第一端流出的電流就會開始對第一讀取位元線BLR充電,使得第一讀取位元線BLR及第二讀取位元線BLR’之間開始出現電壓差。如此一來,差動感測電路130就會被觸發,使得充電電流所造成的微小電壓差被放大,而儲存在反熔絲電晶體110中的位元資訊就可以快速且穩定地被讀出。
除此之外,由於差動感測電路130可以感測並放大微小的電壓差,因此沒有必要持續地對位元線進行充電,否則反而可能會干擾了差動感測電路130的操作。在註冊字元線WLP自高操作電壓VH變為低操作電壓VL之後,因為反熔絲電晶體110所產生之電流而造成位元線BLR及BLR’之間的電壓差異會逐漸穩 定。在此情況下,閘極選擇線SG將會自低操作電壓VL變為高操作電壓VH,而電壓源121也可從提供讀取電壓VR改為提供參考電壓V0。也就是說,閘極控制P型電晶體122將會截止,而閘極控制N型電晶體123會導通。因此,反熔絲電晶體110會停止產生電流,而差動感測電路130也會將電壓差異放大而進入閂鎖狀態,並將亂數位元輸出。
由於物理不可複製函數單元100可以透過單一反熔絲電晶體110的氧化層狀態來記錄其中儲存的亂數位元,因此現有技術的駭客方法,像是電子顯微鏡(TEM)和掃描電子顯微鏡(SEM)這類利用電壓對比的檢驗方式,以及透過奈米探針量測(nano-probing)的閘極掃描技術,都不再有效。舉例來說,當透過奈米探針在反熔絲電晶體110的端點上施加感測電壓時,由於電晶體的通道會被導通,因此流經過穿鑿路徑至反熔絲電晶體110之其中一端的電流也會流至反熔絲電晶體110的另一端。也就是說,根據奈米探針的探測結果,將難以分辨出穿鑿路徑是在反熔絲電晶體110之閘極端及第一端之間或者是在反熔絲電晶體110之閘極端及第二端之間。此外,由於電壓對比的檢驗探測過程會產生誤差,因此想自物理不可複製函數單元100中取出秘密的位元資訊也就更加困難。再者,由於閘極掃描難以辨識出穿鑿路徑的位置,因此也無法取得物理不可複製函數單元100所儲存的資訊。也就是說,物理不可複製函數單元100能夠以更加安全有保障的方式來產生系統所需的亂數位元。
第4圖為本發明另一實施例之物理不可複製函數單元200的示意圖。物理不可複製函數單元100及200具有相似的結構,並且可以根據相似的原理操作。然而,物理不可複製函數單元200中的控制電路220還可包含第一讀取電晶體226及第二讀取電晶體227。
第一讀取電晶體226具有第一端、第二端及控制端,第一讀取電晶體226的第一端耦接於第一讀取位元線BLR,第一讀取電晶體226的第二端耦接於 反熔絲電晶體210的第一端,而第一讀取電晶體226的控制端耦接於讀取字元線WLR。第二讀取電晶體227具有第一端、第二端及控制端,第二讀取電晶體227的第一端耦接於第二讀取位元線BLR’,第二讀取電晶體227的第二端耦接於反熔絲電晶體210的第二端,而第二讀取電晶體227的控制端耦接於讀取字元線WLR。在此情況下,差動感測電路230中的第一反相器232及第二反相器234可經由第一讀取位元線BLR及第一讀取電晶體226耦接至反熔絲電晶體210的第一端。此外,差動感測電路230中的第一反相器232及第二反相器234可經由第二讀取位元線BLR’及第二讀取電晶體227耦接至反熔絲電晶體210的第二端。
第一讀取電晶體226及第二讀取電晶體227可用來保護差動感測電路230在註冊操作的過程中受到損壞。舉例來說,第2圖所示的電壓也可應用於物理不可複製函數單元200以執行註冊操作,此時讀取字元線WLR將會在低操作電壓VL。在此情況下,第一讀取電晶體226及第二讀取電晶體227將會被截止。如此一來,差動感測電路230就不會被註冊操作過程中所產生的電流所影響。
此外,第3圖所示的電壓也可應用在物理不可複製函數單元200以執行讀取操作,此時讀取字元線WLR可自高操作電壓VH變為低操作電壓VL。在讀取操作中,當註冊字元線WLP自高操作電壓VH變為低操作電壓VL之後,由反熔絲電晶體210產生之電流所造成讀取位元線BLR及BLR’上的電壓差會逐漸穩定。此時,讀取字元線WLR可自高操作電壓VH變為低操作電壓VL,使得第一讀取電晶體226及第二讀取電晶體227被截止。如此一來,就可以停止對讀取位元線BLR及BLR’充電,而差動感測電路230就可以對應地放大讀取位元線BLR及BLR’上的電壓差,並進入閂鎖狀態以輸出亂數位元。
第5圖為操作物理不可複製函數單元100之方法300的流程圖。方法300包含步驟S310至S340,但不限於第5圖所示的順序。
S310:在註冊操作時,控制電路120提供註冊電壓VP至反熔絲電晶 體110的閘極端;S320:在註冊操作時,控制電路120提供參考電壓V0至反熔絲電晶體110的第一端及第二端;S330:在讀取操作時,控制電路120提供讀取電壓VR至反熔絲電晶體110的閘極端;S340:在讀取操作時,控制電路120提供參考電壓V0至反熔絲電晶體110的第一端及第二端。
由於註冊電壓VP與參考電壓V0之間的壓差相當大,因此能夠在反熔絲電晶體110的閘極端至第一端或在反熔絲電晶體110的閘極端至第二端之間產生出穿鑿路徑,使得反熔絲電晶體110能夠在步驟S310及S320中完成註冊寫入。
接著,在讀取操作時,在步驟S330及S340中,反熔絲電晶體110的閘極端會接收到低於註冊電壓VP的讀取電壓VR,因此可以根據反熔絲電晶體110之第一端及第二端所產生的電流對應地讀出亂數位元。
透過方法300,物理不可複製函數單元100就能夠利用單一反熔絲電晶體110完成註冊,並產生亂數位元,還可透過差動感測電路130來讀出反熔絲電晶體110中所儲存的亂數位元。此外,在有些實施例中,控制電路120也可以利用其他的結構和其他的元件來實作。舉例來說,第4圖中的控制電路220也可以用來控制反熔絲電晶體210,而方法300也可以應用在物理不可複製函數單元200。
綜上所述,本發明之實施例所提供的物理不可複製函數單元及操作物理不可複製函數單元的方法可以利用單一個反熔絲電晶體產生亂數位元。由於反熔絲電晶體的氧化層狀態可以用來記錄物理不可複製函數單元中所儲存的亂數位元,因此亂數位元能夠以更加安全的方式儲存,並且能夠免於受到現有技術之駭客方法,例如電壓對比檢測及閘極掃描等方法的威脅。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。

Claims (15)

  1. 一種物理不可複製函數(physically unclonable function,PUF)單元,包含:一反熔絲電晶體,具有一第一端,一第二端,及一閘極端;及一控制電路,耦接於該反熔絲電晶體,並用以在一註冊操作中,施加一註冊電壓至該反熔絲電晶體的該閘極端及施加一參考電壓至該反熔絲電晶體的該第一端及該第二端;其中該註冊電壓高於該參考電壓,且該註冊電壓高到足以在該反熔絲電晶體的該閘極端至該第一端或在該反熔絲電晶體的該閘極端至該第二端之間產生出一穿鑿路徑。
  2. 如請求項1所述之物理不可複製函數單元,另包含一差動感測電路,用以在一讀取操作時,根據該反熔絲電晶體之該第一端及該第二端所產生的電流輸出一亂數位元。
  3. 如請求項2所述之物理不可複製函數單元,其中該控制電路包含:一電壓源,用以在該註冊操作時提供該註冊電壓,並在該讀取操作時提供一讀取電壓,該讀取電壓低於該註冊電壓;一閘極控制P型晶體,具有一第一端耦接於該電壓源,一第二端耦接於該反熔絲電晶體的該閘極端,及一控制端耦接於一閘極選擇線;及一閘極控制N型晶體,具有一第一端耦接於該電壓源,一第二端耦接於該反熔絲電晶體的該閘極端,及一控制端耦接於該閘極選擇線。
  4. 如請求項3所述之物理不可複製函數單元,其中該控制電路另包含:一第一註冊電晶體,具有一第一端耦接於該反熔絲電晶體的該第一端,一第二端耦接於一註冊位元線,及一控制端耦接於一註冊字元線;及一第二註冊電晶體,具有一第一端耦接於該反熔絲電晶體的該第二端,一第二端耦接於該註冊位元線,及一控制端耦接於該註冊字元線。
  5. 如請求項4所述之物理不可複製函數單元,其中:在該註冊操作時,該閘極選擇線是在一低操作電壓,該註冊位元線是在該參考電壓,且該註冊字元線是在一高操作電壓,其中該低操作電壓低於該高操作電壓,該高操作電壓高於該參考電壓,且該高操作電壓低於該註冊電壓。
  6. 如請求項4所述之物理不可複製函數單元,其中該差動感測電路包含:一第一反相器,具有一輸入端經由一第一讀取位元線耦接於該反熔絲電晶體的該第一端,及一輸出端經由一第二讀取位元線耦接於該反熔絲電晶體的該第二端;及一第二反相器,具有一輸入端耦接於該第一反相器的該輸出端,及一輸出端耦接於該第一反相器的該輸入端。
  7. 如請求項6所述之物理不可複製函數單元,其中:在該讀取操作時:該閘極選擇線自一低操作電壓變為一高操作電壓;該註冊位元線是在該參考電壓;及該註冊位元線自該高操作電壓變為該低操作電壓;其中該高操作電壓高於該低操作電壓。
  8. 如請求項7所述之物理不可複製函數單元,其中:在該讀取操作時,在該註冊字元線自該高操作電壓變為該低操作電壓之後,該閘極選擇線自該低操作電壓變為該高操作電壓。
  9. 如請求項4所述之物理不可複製函數單元,其中控制電路另包含:一第一讀取電晶體,具有一第一端耦接於一第一讀取位元線,一第二端耦接於該反熔絲電晶體的該第一端,及一控制端耦接於一讀取字元線;及一第二讀取電晶體,具有一第一端耦接於一第二讀取位元線,一第二端耦接於該反熔絲電晶體的該第二端,及一控制端耦接於該讀取字元線。
  10. 如請求項9所述之物理不可複製函數單元,其中:在該註冊操作時,該閘極選擇線是在一低操作電壓,該註冊位元線是在該參考電壓,該註冊字元線是在一高操作電壓,該低操作電壓低於該高操作電壓,該高操作電壓高於該參考電壓且低於該註冊電壓,且該讀取字元線是在該低操作電壓。
  11. 如請求項9所述之物理不可複製函數單元,其中該差動感測電路包含:一第一反相器,具有一輸入端耦接於該第一讀取位元線,及一輸出端耦接於該第二讀取位元線;及一第二反相器,具有一輸入端耦接於該第一反相器的該輸出端,及一輸出端耦接於該第一反相器的該輸入端。
  12. 如請求項11所述之物理不可複製函數單元,其中:在該讀取操作時:該閘極選擇線自一低操作電壓變為一高操作電壓;該註冊位元線是在該參考電壓;該註冊字元線自該高操作電壓變為該低操作電壓;及該讀取字元線自該高操作電壓變為該低操作電壓。
  13. 如請求項12所述之物理不可複製函數單元,其中:在該讀取操作時,在該註冊字元線自該高操作電壓變為該低操作電壓之後:該閘極選擇線自該低操作電壓變為該高操作電壓;及該讀取字元線自該高操作電壓變為該低操作電壓。
  14. 一種物理不可複製函數(physically unclonable function,PUF)單元的操作方法,該物理不可複製函數單元包含一反熔絲電晶體及耦接於該反熔絲電晶體之一控制電路,該方法包含:在一註冊操作時:該控制電路提供一註冊電壓至該反熔絲電晶體的一閘極端;及該控制電路提供一參考電壓至該反熔絲電晶體的一第一端及一第二端;其中該註冊電壓高於該參考電壓,且該註冊電壓高到足以在該反熔絲電晶體的該閘極端至該第一端或在該反熔絲電晶體的該閘極端至該第二端之間產生出一穿鑿路徑。
  15. 如請求項14所述之方法,另包含:在一讀取操作時:該控制電路提供一讀取電壓至該反熔絲電晶體的該閘極端;及該控制電路提供該參考電壓至該反熔絲電晶體的該第一端及該第二端;其中該註冊電壓高於該讀取電壓,且該讀取電壓高於該參考電壓。
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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10911229B2 (en) 2016-08-04 2021-02-02 Macronix International Co., Ltd. Unchangeable physical unclonable function in non-volatile memory
US11258599B2 (en) 2016-08-04 2022-02-22 Macronix International Co., Ltd. Stable physically unclonable function
EP3680800B1 (en) * 2018-08-10 2021-10-27 Shenzhen Weitongbo Technology Co., Ltd. Physical unclonable function (puf) device
US11263331B2 (en) * 2018-09-27 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Electronic device for checking randomness of identification key device, random key checker circuit, and method of checking randomness of electronic device
EP3640945B1 (en) * 2018-10-15 2021-03-17 Nxp B.V. Non-volatile memory with physical unclonable function
KR20200082982A (ko) * 2018-12-31 2020-07-08 삼성전자주식회사 물리적 복제방지 기능의 보안을 위한 집적 회로 및 이를 포함하는 장치
CN111723408B (zh) * 2019-03-21 2023-06-02 中芯国际集成电路制造(上海)有限公司 用于生成puf特征码的装置
US11121884B2 (en) * 2019-06-10 2021-09-14 PUFsecurity Corporation Electronic system capable of self-certification
CN110309574B (zh) * 2019-06-25 2023-01-06 北京智涵芯宇科技有限公司 可感知芯片电路物理完整性的puf电路及芯片
CN112291056B (zh) * 2019-07-25 2024-02-23 熵码科技股份有限公司 加密密钥生成器及传输系统
US20210051010A1 (en) * 2019-08-16 2021-02-18 PUFsecurity Corporation Memory Device Providing Data Security
CN110491434B (zh) * 2019-08-23 2021-04-02 上海华虹宏力半导体制造有限公司 一种闪存存储器装置及其编程方法
US11456867B2 (en) * 2019-10-25 2022-09-27 International Business Machines Corporation Trust-anchoring of cryptographic objects
US11296096B2 (en) * 2019-11-08 2022-04-05 Zhuhai Chuangfeixin Technology Co., Ltd. Antifuse OTP structure with hybrid junctions
US11217595B2 (en) * 2020-01-15 2022-01-04 Zhuhai Chuangfeixin Technology Co., Ltd. Antifuse OTP structure with hybrid device and hybrid junction for select transistor
US11158641B2 (en) * 2020-02-12 2021-10-26 Zhuhai Chuangfeixin Technology Co., Ltd. Antifuse OTP structures with hybrid devices and hybrid junctions
US11189356B2 (en) * 2020-02-27 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. One-time-programmable memory
US11018143B1 (en) * 2020-03-12 2021-05-25 Zhuhai Chuangfeixin Technology Co., Ltd. Antifuse OTP structures with hybrid low-voltage devices
CN113496988B (zh) 2020-04-08 2023-12-12 长鑫存储技术有限公司 反熔丝单元及反熔丝阵列
US11233663B1 (en) * 2020-07-22 2022-01-25 Nxp Usa, Inc. Physically unclonable function having source bias transistors
US11380379B2 (en) * 2020-11-02 2022-07-05 Macronix International Co., Ltd. PUF applications in memories
CN113009817B (zh) * 2021-02-08 2022-07-05 浙江大学 一种基于控制器输出状态安全熵的工控系统入侵检测方法
US20230139712A1 (en) * 2021-11-04 2023-05-04 National Yang Ming Chiao Tung University Circuit apparatus and methods for puf source and generating random digital sequence
US12099616B2 (en) 2021-11-15 2024-09-24 International Business Machines Corporation Physically unclonable function based on a phase change material array
CN116092623B (zh) * 2023-04-12 2023-07-28 四川执象网络有限公司 一种基于基层医学质控的健康数据管理方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200731270A (en) * 2005-09-29 2007-08-16 Cypress Semiconductor Corp Antifuse circuit with current regulator for controlling programming current
TW200834893A (en) * 2006-12-22 2008-08-16 Sidense Corp Mask programmable anti-fuse architecture
US20100220511A1 (en) * 2009-02-27 2010-09-02 Sidense Corp. Low power antifuse sensing scheme with improved reliability
US20170200508A1 (en) * 2016-01-08 2017-07-13 Sidense Corp. Puf value generation using an anti-fuse memory array
TW201727657A (zh) * 2016-01-19 2017-08-01 Ememory Technology Inc 用於物理不可複製技術的一次編程記憶胞與記憶體陣列以 及相關隨機碼產生方法

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541996A (en) * 1994-12-12 1996-07-30 Itt Corporation Apparatus and method for a pseudo-random number generator for high precision numbers
US6292394B1 (en) 2000-06-29 2001-09-18 Saifun Semiconductors Ltd. Method for programming of a semiconductor memory cell
EP1359550A1 (fr) 2001-11-30 2003-11-05 STMicroelectronics S.A. Régéneration d'une quantité secrète à partir d'un identifiant d'un circuit intégré
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7177199B2 (en) 2003-10-20 2007-02-13 Sandisk Corporation Behavior based programming of non-volatile memory
US7149114B2 (en) * 2004-03-17 2006-12-12 Cypress Semiconductor Corp. Latch circuit and method for writing and reading volatile and non-volatile data to and from the latch
US6970394B2 (en) 2004-04-22 2005-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Programming method for electrical fuse cell and circuit thereof
US7133316B2 (en) 2004-06-02 2006-11-07 Macronix International Co., Ltd. Program/erase method for P-channel charge trapping memory device
US20070061595A1 (en) * 2005-09-14 2007-03-15 Huang-Chung Chen Apparatus and method for protecting data
KR100763353B1 (ko) * 2006-04-26 2007-10-04 삼성전자주식회사 인접하는 메모리셀과의 커플링 노이즈를 저감시키는불휘발성 반도체 메모리 장치
JP2008047702A (ja) * 2006-08-16 2008-02-28 Nec Electronics Corp 半導体記憶装置
TWI430275B (zh) * 2008-04-16 2014-03-11 Magnachip Semiconductor Ltd 用於程式化非揮發性記憶體裝置之方法
US8304835B2 (en) * 2009-03-27 2012-11-06 National Semiconductor Corporation Configuration and fabrication of semiconductor structure using empty and filled wells
WO2011086688A1 (ja) * 2010-01-15 2011-07-21 三菱電機株式会社 ビット列生成装置及びビット列生成方法
KR101614950B1 (ko) * 2010-04-12 2016-04-25 삼성전자주식회사 저장 장치에 물리적 식별자를 생성하는 방법 및 기계로 읽을 수 있는 저장 매체
US20120314474A1 (en) * 2011-06-09 2012-12-13 Hsin-Ming Chen Non-volatile memory cell structure and method for programming and reading the same
CN102393890B (zh) * 2011-10-09 2014-07-16 广州大学 一种抗物理入侵和旁路攻击的密码芯片系统及其实现方法
JP5831203B2 (ja) * 2011-12-20 2015-12-09 富士通株式会社 個体別情報生成装置、暗号化装置、認証システム、及び個体別情報生成方法
CN104025500B (zh) 2011-12-29 2017-07-25 英特尔公司 使用在物理上不可克隆的函数的安全密钥存储
DE102012102254B4 (de) * 2012-03-16 2020-09-24 Infineon Technologies Ag Vorrichtung und Verfahren zur Rekonstruktion einer Bitfolge unter Vorkorrektur
US9304944B2 (en) * 2012-03-29 2016-04-05 Broadcom Corporation Secure memory access controller
WO2013170387A1 (en) * 2012-05-18 2013-11-21 Sidense Corp. Circuit and method for reducing write disturb in a non-volatile memory device
US8928347B2 (en) * 2012-09-28 2015-01-06 Intel Corporation Integrated circuits having accessible and inaccessible physically unclonable functions
CN104704768B (zh) * 2012-10-04 2018-01-05 本质Id有限责任公司 用于从用作物理不可克隆功能的存储器中生成密码密钥的系统
CN103020549B (zh) * 2012-11-26 2016-05-11 北京华大信安科技有限公司 存储器的保护装置以及存储装置
US8938792B2 (en) 2012-12-28 2015-01-20 Intel Corporation Device authentication using a physically unclonable functions based key generation system
US9390291B2 (en) * 2012-12-29 2016-07-12 Intel Corporation Secure key derivation and cryptography logic for integrated circuits
US9281074B2 (en) * 2013-05-16 2016-03-08 Ememory Technology Inc. One time programmable memory cell capable of reducing leakage current and preventing slow bit response
US10235261B2 (en) 2013-07-26 2019-03-19 Ictk Holdings Co., Ltd. Apparatus and method for testing randomness
US9992031B2 (en) * 2013-09-27 2018-06-05 Intel Corporation Dark bits to reduce physically unclonable function error rates
JP6354172B2 (ja) * 2014-01-20 2018-07-11 富士通株式会社 半導体集積回路及び認証システム
US10218517B2 (en) * 2014-03-25 2019-02-26 Carnegie Mellon University Methods for generating reliable responses in physical unclonable functions (PUFs) and methods for designing strong PUFs
US10216484B2 (en) * 2014-06-10 2019-02-26 Texas Instruments Incorporated Random number generation with ferroelectric random access memory
KR102169197B1 (ko) * 2014-09-16 2020-10-22 에스케이하이닉스 주식회사 향상된 프로그램 효율을 갖는 안티퓨즈 오티피 메모리 셀 및 셀 어레이
US10129036B2 (en) 2014-09-18 2018-11-13 Intel Corporation Post-processing mechanism for physically unclonable functions
CN107004380B (zh) 2014-10-13 2020-11-13 本质Id有限责任公司 包括物理不可克隆功能的加密设备
US9460797B2 (en) * 2014-10-13 2016-10-04 Ememory Technology Inc. Non-volatile memory cell structure and non-volatile memory apparatus using the same
US10353638B2 (en) * 2014-11-18 2019-07-16 Microsemi SoC Corporation Security method and apparatus to prevent replay of external memory data to integrated circuits having only one-time programmable non-volatile memory
CN105632543B (zh) * 2014-11-21 2018-03-30 松下知识产权经营株式会社 具有防篡改性的非易失性存储装置及集成电路卡
EP3238199B1 (en) 2014-12-24 2020-06-17 Intrinsic ID B.V. Secure key generation from biased physical unclonable function
US11115022B2 (en) * 2015-05-07 2021-09-07 Northwestern University System and method for integrated circuit usage tracking circuit with fast tracking time for hardware security and re-configurability
CN104836669B (zh) * 2015-05-08 2018-04-06 东南大学 一种基于sram puf的安全认证方法及一种终端、认证系统
JP6617924B2 (ja) * 2015-06-18 2019-12-11 パナソニックIpマネジメント株式会社 耐タンパ性を有する不揮発性メモリ装置および集積回路カード、不揮発性メモリ装置の認証方法、個体識別情報生成方法
JP6587188B2 (ja) * 2015-06-18 2019-10-09 パナソニックIpマネジメント株式会社 乱数処理装置、集積回路カード、および乱数処理方法
EP3113409B1 (en) * 2015-07-01 2024-09-18 Secure-IC SAS Embedded test circuit for physically unclonable function
EP3332402B1 (en) * 2015-08-06 2020-10-07 Intrinsic ID B.V. Cryptographic device having physical unclonable function
WO2017025597A1 (en) 2015-08-11 2017-02-16 Koninklijke Philips N.V. Key sharing device and method
US9971566B2 (en) * 2015-08-13 2018-05-15 Arizona Board Of Regents Acting For And On Behalf Of Northern Arizona University Random number generating systems and related methods
CN105007285B (zh) * 2015-08-19 2018-07-24 南京万道电子技术有限公司 一种基于物理不可克隆函数的密钥保护方法和安全芯片
US10142103B2 (en) * 2015-12-07 2018-11-27 The Boeing Company Hardware assisted fast pseudorandom number generation
CN105743645B (zh) * 2016-01-25 2019-06-18 清华大学 基于puf的流秘钥生成装置、方法及数据加密、解密方法
CN106020771B (zh) 2016-05-31 2018-07-20 东南大学 一种基于puf的伪随机序列发生器
US10438025B2 (en) * 2016-10-04 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Self-destruct SRAM-based authentication circuit
US10122538B2 (en) * 2016-10-12 2018-11-06 Ememory Technology Inc. Antifuse physically unclonable function unit and associated control method
US9779832B1 (en) 2016-12-07 2017-10-03 Sandisk Technologies Llc Pulsed control line biasing in memory
JP2018113415A (ja) * 2017-01-13 2018-07-19 ルネサスエレクトロニクス株式会社 半導体装置
US11522724B2 (en) * 2017-12-11 2022-12-06 International Business Machines Corporation SRAM as random number generator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200731270A (en) * 2005-09-29 2007-08-16 Cypress Semiconductor Corp Antifuse circuit with current regulator for controlling programming current
TW200834893A (en) * 2006-12-22 2008-08-16 Sidense Corp Mask programmable anti-fuse architecture
US20100220511A1 (en) * 2009-02-27 2010-09-02 Sidense Corp. Low power antifuse sensing scheme with improved reliability
US20170200508A1 (en) * 2016-01-08 2017-07-13 Sidense Corp. Puf value generation using an anti-fuse memory array
TW201727657A (zh) * 2016-01-19 2017-08-01 Ememory Technology Inc 用於物理不可複製技術的一次編程記憶胞與記憶體陣列以 及相關隨機碼產生方法

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