JP2019054233A - 単一のアンチヒューズトランジスタを有するpufユニット - Google Patents
単一のアンチヒューズトランジスタを有するpufユニット Download PDFInfo
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- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
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- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
Description
Claims (15)
- PUFユニットであって、
第1の端子と、第2の端子と、ゲート端子とを有するアンチヒューズトランジスタと、
前記アンチヒューズトランジスタに結合され、登録動作中、前記アンチヒューズトランジスタのゲート端子に登録電圧を印加し、前記アンチヒューズトランジスタの第1の端子及び第2の端子に基準電圧を印加するように構成された制御回路と、
前記登録電圧は前記基準電圧よりも高く、前記第1の端子又は前記第2の端子への前記ゲート端子上にラプチャ経路を生成するのに十分に高い、PUFユニット。 - 読み出し動作中、前記アンチヒューズトランジスタの第1の端子及び第2の端子から発生する電流に従ってエントロピービットを出力するように構成された差動検知回路をさらに含む、請求項1に記載のPUFユニット。
- 前記制御回路は、
前記登録動作中、前記登録電圧を、前記読み出し動作中、前記登録電圧よりも低い読み出し電圧を供給するように構成された電圧源と、
前記電圧源に結合された第1の端子と、前記アンチヒューズトランジスタのゲート端子に結合された第2の端子と、選択ゲート線に結合された制御端子と、を有するP型ゲート制御トランジスタと、
前記電圧源に結合された第1の端子と、前記アンチヒューズトランジスタのゲート端子に結合された第2の端子と、前記選択ゲート線に結合された制御端子と、を有するN型ゲート制御トランジスタと、を含む、請求項2に記載のPUFユニット。 - 前記制御回路は、
前記アンチヒューズトランジスタの第1の端子に結合された第1の端子と、登録ビット線に結合された第2の端子と、登録ワード線に結合された制御端子と、を有する第1の登録トランジスタと、
前記アンチヒューズトランジスタの第2の端子に結合された第1の端子と、前記登録ビット線に結合された第2の端子と、前記登録ワード線に結合された制御端子と、を有する第2の登録トランジスタと、をさらに含む、請求項3に記載のPUFユニット。 - 登録動作中、前記選択ゲート線は高動作電圧よりも低い低動作電圧にあり、前記登録ビット線は前記基準電圧にあり、前記登録ワード線は前記基準電圧より高く前記登録電圧よりも低い前記高動作電圧にある、請求項4に記載のPUFユニット。
- 前記差動検知回路は、
第1の読み出しビット線を介して前記アンチヒューズトランジスタの第1の端子に結合された入力端子と、第2の読み出しビット線を介して前記アンチヒューズトランジスタの第2の端子に結合された出力端子と、を有する第1のインバータと、
前記第1のインバータの出力端子に結合された入力端子と、前記第1のインバータの入力端子に結合された出力端子と、を有する第2のインバータと、を含む、請求項4に記載のPUFユニット。 - 前記読み出し動作中、
前記選択ゲート線を低動作電圧から高動作電圧に変更し、
前記登録ビット線は前記基準電圧にあり、
前記登録ワード線を前記高動作電圧から前記低動作電圧に変更する、請求項6に記載のPUFユニット。 - 前記読み出し動作中、前記登録ワード線を前記高動作電圧から前記低動作電圧に変更した後に、前記選択ゲート線を前記低動作電圧から前記高動作電圧に変更する、請求項7に記載のPUFユニット。
- 前記制御回路は、
第1の読み出しビット線に結合された第1の端子と、前記アンチヒューズトランジスタの第1の端子に結合された第2の端子と、読み出しワード線に結合された制御端子と、を有する第1の読み出しトランジスタと、
第2の読み出しビット線に結合された第1の端子と、前記アンチヒューズトランジスタの第2の端子に結合された第2の端子と、前記読み出しワード線に結合された制御端子と、を有する第2の読み出しトランジスタと、をさらに含む、請求項4に記載のPUFユニット。 - 登録動作中、前記選択ゲート線は高動作電圧よりも低い低動作電圧にあり、前記登録ビット線は基前記準電圧にあり、前記登録ワード線は前記基準電圧よりも高く、前記登録電圧よりも低い前記高動作電圧にあり、前記読み出しワード線は低動作電圧にある、請求項9に記載のPUFユニット。
- 前記差動検知回路は、
前記第1の読み出しビット線に結合された入力端子と、前記第2の読み出しビット線に結合された出力端子と、を有する第1のインバータと、
前記第1のインバータの出力端子に結合された入力端子と、前記第1のインバータの入力端子に結合された出力端子と、を有する第2のインバータと、を含む、請求項9に記載のPUFユニット。 - 前記読み出し動作中、
前記選択ゲート線を低動作電圧から高動作電圧に変更し、
前記登録ビット線は前記基準電圧にあり、
前記登録ワード線を前記高動作電圧から前記低動作電圧に変更し、
前記読み出しワード線を前記高動作電圧から前記低動作電圧に変更する、請求項11に記載のPUFユニット。 - 読み出し動作中、前記登録ワード線を前記高動作電圧から前記低動作電圧に変更した後、前記選択ゲート線を前記低動作電圧から前記高動作電圧に変更し、前記登録ワード線を前記高動作電圧から前記低動作電圧に変更した後、前記読み出しワード線を前記高動作電圧から前記低動作電圧に変更する、請求項12に記載のPUFユニット。
- PUFユニットを動作させる方法であって、該PUFユニットは、アンチヒューズトランジスタと、該アンチヒューズトランジスタに結合された制御回路とを含み、当該方法は、
登録動作中、
前記制御回路が、前記アンチヒューズトランジスタのゲート端子に登録電圧を印加し、
前記制御回路が、前記アンチヒューズトランジスタの第1の端子及び第2の端子に基準電圧を印加し、
前記登録電圧は前記基準電圧よりも高く、前記登録電圧は前記第1の端子又は前記第2の端子への前記ゲート端子上にラプチャ経路を生成するのに十分に高い、方法。 - 読み出し動作中、
前記制御回路が、前記アンチヒューズトランジスタのゲート端子に読み出し電圧を印加し、
前記制御回路が、前記アンチヒューズトランジスタの前記第1の端子及び前記第2の端子に基準電圧を印加し、
前記登録電圧は前記読み出し電圧よりも高く、前記読み出し電圧は前記基準電圧よりも高い、請求項14に記載の方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201762557170P | 2017-09-12 | 2017-09-12 | |
US62/557,170 | 2017-09-12 | ||
US16/038,143 US10177924B1 (en) | 2017-09-12 | 2018-07-17 | Physically unclonable function unit with one single anti-fuse transistor |
US16/038,143 | 2018-07-17 |
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Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10911229B2 (en) | 2016-08-04 | 2021-02-02 | Macronix International Co., Ltd. | Unchangeable physical unclonable function in non-volatile memory |
US11258599B2 (en) | 2016-08-04 | 2022-02-22 | Macronix International Co., Ltd. | Stable physically unclonable function |
CN111201533B (zh) * | 2018-08-10 | 2023-06-23 | 深圳市为通博科技有限责任公司 | 物理不可克隆函数puf装置 |
US11263331B2 (en) * | 2018-09-27 | 2022-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electronic device for checking randomness of identification key device, random key checker circuit, and method of checking randomness of electronic device |
EP3640945B1 (en) * | 2018-10-15 | 2021-03-17 | Nxp B.V. | Non-volatile memory with physical unclonable function |
CN111723408B (zh) * | 2019-03-21 | 2023-06-02 | 中芯国际集成电路制造(上海)有限公司 | 用于生成puf特征码的装置 |
US11121884B2 (en) * | 2019-06-10 | 2021-09-14 | PUFsecurity Corporation | Electronic system capable of self-certification |
CN110309574B (zh) * | 2019-06-25 | 2023-01-06 | 北京智涵芯宇科技有限公司 | 可感知芯片电路物理完整性的puf电路及芯片 |
EP3770751B1 (en) | 2019-07-25 | 2023-10-18 | PUFsecurity Corporation | High speed encryption key generating engine |
US20210051010A1 (en) * | 2019-08-16 | 2021-02-18 | PUFsecurity Corporation | Memory Device Providing Data Security |
CN110491434B (zh) * | 2019-08-23 | 2021-04-02 | 上海华虹宏力半导体制造有限公司 | 一种闪存存储器装置及其编程方法 |
US11456867B2 (en) * | 2019-10-25 | 2022-09-27 | International Business Machines Corporation | Trust-anchoring of cryptographic objects |
US11296096B2 (en) * | 2019-11-08 | 2022-04-05 | Zhuhai Chuangfeixin Technology Co., Ltd. | Antifuse OTP structure with hybrid junctions |
US11217595B2 (en) * | 2020-01-15 | 2022-01-04 | Zhuhai Chuangfeixin Technology Co., Ltd. | Antifuse OTP structure with hybrid device and hybrid junction for select transistor |
US11158641B2 (en) * | 2020-02-12 | 2021-10-26 | Zhuhai Chuangfeixin Technology Co., Ltd. | Antifuse OTP structures with hybrid devices and hybrid junctions |
US11018143B1 (en) * | 2020-03-12 | 2021-05-25 | Zhuhai Chuangfeixin Technology Co., Ltd. | Antifuse OTP structures with hybrid low-voltage devices |
CN113496988B (zh) * | 2020-04-08 | 2023-12-12 | 长鑫存储技术有限公司 | 反熔丝单元及反熔丝阵列 |
US11233663B1 (en) * | 2020-07-22 | 2022-01-25 | Nxp Usa, Inc. | Physically unclonable function having source bias transistors |
US11380379B2 (en) | 2020-11-02 | 2022-07-05 | Macronix International Co., Ltd. | PUF applications in memories |
CN113009817B (zh) * | 2021-02-08 | 2022-07-05 | 浙江大学 | 一种基于控制器输出状态安全熵的工控系统入侵检测方法 |
US20230139712A1 (en) * | 2021-11-04 | 2023-05-04 | National Yang Ming Chiao Tung University | Circuit apparatus and methods for puf source and generating random digital sequence |
CN116092623B (zh) * | 2023-04-12 | 2023-07-28 | 四川执象网络有限公司 | 一种基于基层医学质控的健康数据管理方法 |
Family Cites Families (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5541996A (en) * | 1994-12-12 | 1996-07-30 | Itt Corporation | Apparatus and method for a pseudo-random number generator for high precision numbers |
US6292394B1 (en) | 2000-06-29 | 2001-09-18 | Saifun Semiconductors Ltd. | Method for programming of a semiconductor memory cell |
EP1359550A1 (fr) | 2001-11-30 | 2003-11-05 | STMicroelectronics S.A. | Régéneration d'une quantité secrète à partir d'un identifiant d'un circuit intégré |
US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
US7177199B2 (en) | 2003-10-20 | 2007-02-13 | Sandisk Corporation | Behavior based programming of non-volatile memory |
US7149114B2 (en) * | 2004-03-17 | 2006-12-12 | Cypress Semiconductor Corp. | Latch circuit and method for writing and reading volatile and non-volatile data to and from the latch |
US6970394B2 (en) | 2004-04-22 | 2005-11-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Programming method for electrical fuse cell and circuit thereof |
US7133316B2 (en) | 2004-06-02 | 2006-11-07 | Macronix International Co., Ltd. | Program/erase method for P-channel charge trapping memory device |
US7253496B2 (en) * | 2005-06-28 | 2007-08-07 | Cypress Semiconductor Corporation | Antifuse circuit with current regulator for controlling programming current |
US20070061595A1 (en) * | 2005-09-14 | 2007-03-15 | Huang-Chung Chen | Apparatus and method for protecting data |
KR100763353B1 (ko) * | 2006-04-26 | 2007-10-04 | 삼성전자주식회사 | 인접하는 메모리셀과의 커플링 노이즈를 저감시키는불휘발성 반도체 메모리 장치 |
JP2008047702A (ja) * | 2006-08-16 | 2008-02-28 | Nec Electronics Corp | 半導体記憶装置 |
KR101193348B1 (ko) * | 2006-12-22 | 2012-10-19 | 싸이던스 코포레이션 | 마스크 프로그램 가능한 안티-퓨즈 아키텍처 |
TWI430275B (zh) * | 2008-04-16 | 2014-03-11 | Magnachip Semiconductor Ltd | 用於程式化非揮發性記憶體裝置之方法 |
WO2010096915A1 (en) * | 2009-02-27 | 2010-09-02 | Sidense Corp. | Low power antifuse sensing scheme with improved reliability |
US8304835B2 (en) * | 2009-03-27 | 2012-11-06 | National Semiconductor Corporation | Configuration and fabrication of semiconductor structure using empty and filled wells |
CN102783028B (zh) * | 2010-01-15 | 2016-02-03 | 三菱电机株式会社 | 比特列生成装置以及比特列生成方法 |
KR101614950B1 (ko) * | 2010-04-12 | 2016-04-25 | 삼성전자주식회사 | 저장 장치에 물리적 식별자를 생성하는 방법 및 기계로 읽을 수 있는 저장 매체 |
US20120314474A1 (en) * | 2011-06-09 | 2012-12-13 | Hsin-Ming Chen | Non-volatile memory cell structure and method for programming and reading the same |
CN102393890B (zh) * | 2011-10-09 | 2014-07-16 | 广州大学 | 一种抗物理入侵和旁路攻击的密码芯片系统及其实现方法 |
JP5831203B2 (ja) * | 2011-12-20 | 2015-12-09 | 富士通株式会社 | 個体別情報生成装置、暗号化装置、認証システム、及び個体別情報生成方法 |
WO2013101085A1 (en) * | 2011-12-29 | 2013-07-04 | Intel Corporation | Secure key storage using physically unclonable functions |
DE102012102254B4 (de) * | 2012-03-16 | 2020-09-24 | Infineon Technologies Ag | Vorrichtung und Verfahren zur Rekonstruktion einer Bitfolge unter Vorkorrektur |
US9304944B2 (en) * | 2012-03-29 | 2016-04-05 | Broadcom Corporation | Secure memory access controller |
CA2816237C (en) * | 2012-05-18 | 2014-09-30 | Sidense Corp. | Circuit and method for reducing write disturb in a non-volatile memory device |
US8928347B2 (en) * | 2012-09-28 | 2015-01-06 | Intel Corporation | Integrated circuits having accessible and inaccessible physically unclonable functions |
JP6267207B2 (ja) * | 2012-10-04 | 2018-01-24 | イントリンシツク・イー・デー・ベー・ベー | 物理的クローン不能関数として使用されるメモリから暗号化キーを生成するためのシステム |
CN103020549B (zh) * | 2012-11-26 | 2016-05-11 | 北京华大信安科技有限公司 | 存储器的保护装置以及存储装置 |
US8938792B2 (en) | 2012-12-28 | 2015-01-20 | Intel Corporation | Device authentication using a physically unclonable functions based key generation system |
US9390291B2 (en) * | 2012-12-29 | 2016-07-12 | Intel Corporation | Secure key derivation and cryptography logic for integrated circuits |
US9281074B2 (en) * | 2013-05-16 | 2016-03-08 | Ememory Technology Inc. | One time programmable memory cell capable of reducing leakage current and preventing slow bit response |
TWI640863B (zh) | 2013-07-26 | 2018-11-11 | Ict韓國有限公司 | 測試隨機性的儀器以及方法 |
US9992031B2 (en) * | 2013-09-27 | 2018-06-05 | Intel Corporation | Dark bits to reduce physically unclonable function error rates |
JP6354172B2 (ja) * | 2014-01-20 | 2018-07-11 | 富士通株式会社 | 半導体集積回路及び認証システム |
WO2015148659A1 (en) * | 2014-03-25 | 2015-10-01 | Mai Kenneth Wei-An | Methods for generating reliable responses in physical unclonable functions (pufs) and methods for designing strong pufs |
US10216484B2 (en) * | 2014-06-10 | 2019-02-26 | Texas Instruments Incorporated | Random number generation with ferroelectric random access memory |
KR102169197B1 (ko) * | 2014-09-16 | 2020-10-22 | 에스케이하이닉스 주식회사 | 향상된 프로그램 효율을 갖는 안티퓨즈 오티피 메모리 셀 및 셀 어레이 |
US10129036B2 (en) | 2014-09-18 | 2018-11-13 | Intel Corporation | Post-processing mechanism for physically unclonable functions |
US9460797B2 (en) * | 2014-10-13 | 2016-10-04 | Ememory Technology Inc. | Non-volatile memory cell structure and non-volatile memory apparatus using the same |
EP3207539B1 (en) | 2014-10-13 | 2021-03-17 | Intrinsic ID B.V. | Cryptographic device comprising a physical unclonable function |
US10353638B2 (en) * | 2014-11-18 | 2019-07-16 | Microsemi SoC Corporation | Security method and apparatus to prevent replay of external memory data to integrated circuits having only one-time programmable non-volatile memory |
CN105632543B (zh) * | 2014-11-21 | 2018-03-30 | 松下知识产权经营株式会社 | 具有防篡改性的非易失性存储装置及集成电路卡 |
WO2016102164A1 (en) * | 2014-12-24 | 2016-06-30 | Intrinsic Id B.V. | Cryptographic key production from a physical unclonable function |
US11115022B2 (en) * | 2015-05-07 | 2021-09-07 | Northwestern University | System and method for integrated circuit usage tracking circuit with fast tracking time for hardware security and re-configurability |
CN104836669B (zh) * | 2015-05-08 | 2018-04-06 | 东南大学 | 一种基于sram puf的安全认证方法及一种终端、认证系统 |
JP6587188B2 (ja) * | 2015-06-18 | 2019-10-09 | パナソニックIpマネジメント株式会社 | 乱数処理装置、集積回路カード、および乱数処理方法 |
JP6617924B2 (ja) * | 2015-06-18 | 2019-12-11 | パナソニックIpマネジメント株式会社 | 耐タンパ性を有する不揮発性メモリ装置および集積回路カード、不揮発性メモリ装置の認証方法、個体識別情報生成方法 |
EP3113409A1 (en) * | 2015-07-01 | 2017-01-04 | Secure-IC SAS | Embedded test circuit for physically unclonable function |
KR102656990B1 (ko) * | 2015-08-06 | 2024-04-12 | 인트린직 아이디 비브이 | 물리적 복제 방지 기능을 갖는 암호화 디바이스 |
WO2017025597A1 (en) | 2015-08-11 | 2017-02-16 | Koninklijke Philips N.V. | Key sharing device and method |
US9971566B2 (en) * | 2015-08-13 | 2018-05-15 | Arizona Board Of Regents Acting For And On Behalf Of Northern Arizona University | Random number generating systems and related methods |
CN105007285B (zh) * | 2015-08-19 | 2018-07-24 | 南京万道电子技术有限公司 | 一种基于物理不可克隆函数的密钥保护方法和安全芯片 |
US10142103B2 (en) * | 2015-12-07 | 2018-11-27 | The Boeing Company | Hardware assisted fast pseudorandom number generation |
WO2017117663A1 (en) * | 2016-01-08 | 2017-07-13 | Sidense Corp. | Puf value generation using an anti-fuse memory array |
US9613714B1 (en) * | 2016-01-19 | 2017-04-04 | Ememory Technology Inc. | One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method |
CN105743645B (zh) * | 2016-01-25 | 2019-06-18 | 清华大学 | 基于puf的流秘钥生成装置、方法及数据加密、解密方法 |
CN106020771B (zh) | 2016-05-31 | 2018-07-20 | 东南大学 | 一种基于puf的伪随机序列发生器 |
US10438025B2 (en) * | 2016-10-04 | 2019-10-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-destruct SRAM-based authentication circuit |
US10122538B2 (en) * | 2016-10-12 | 2018-11-06 | Ememory Technology Inc. | Antifuse physically unclonable function unit and associated control method |
US9779832B1 (en) | 2016-12-07 | 2017-10-03 | Sandisk Technologies Llc | Pulsed control line biasing in memory |
JP2018113415A (ja) * | 2017-01-13 | 2018-07-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US11522724B2 (en) * | 2017-12-11 | 2022-12-06 | International Business Machines Corporation | SRAM as random number generator |
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