CN108428643B - Semiconductor manufacturing apparatus and method for manufacturing semiconductor device - Google Patents
Semiconductor manufacturing apparatus and method for manufacturing semiconductor device Download PDFInfo
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- CN108428643B CN108428643B CN201810110516.XA CN201810110516A CN108428643B CN 108428643 B CN108428643 B CN 108428643B CN 201810110516 A CN201810110516 A CN 201810110516A CN 108428643 B CN108428643 B CN 108428643B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67294—Apparatus for monitoring, sorting or marking using identification means, e.g. labels on substrates or labels on containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
- H01L21/67712—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrate being handled substantially vertically
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- Microelectronics & Electronic Packaging (AREA)
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- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Die Bonding (AREA)
- Supply And Installment Of Electrical Components (AREA)
Abstract
The invention provides a semiconductor manufacturing apparatus and a semiconductor device manufacturing method, which can place a semiconductor chip (bare chip) on a substrate such as an adhesive sheet to be finally peeled off with high precision. The semiconductor manufacturing apparatus includes: a bare chip supply section; a pick-up head for picking up the bare chip from the bare chip supply part and turning the bare chip upside down; a mounting head that picks up the bare chip from the pickup head, and mounts the bare chip on an upper surface of a transparent substrate with a circuit formation surface of the bare chip facing down; a fiducial mark for identifying a position of the bare chip when the bare chip is mounted on the substrate; a camera which photographs the bare chip and the reference mark from below the substrate; and an illumination device that irradiates light to the bare chip and the reference mark from obliquely below.
Description
Technical Field
The present invention relates to a semiconductor manufacturing apparatus and a semiconductor device manufacturing method, and can be applied to, for example, a die place (die place) for fan-out wafer level packaging.
Background
A Fan-Out Wafer Level Package (FOWLP) is a Package in which a rewiring layer is formed in a large area exceeding the chip area. As a method for manufacturing FOWLP, the following methods are known: a sealing body including a plurality of semiconductor chips and a sealing resin covering the plurality of semiconductor chips is formed by collectively sealing the plurality of semiconductor chips arranged on the adhesive sheet with the sealing resin, and then the adhesive sheet is peeled off from the sealing body, and then a rewiring layer is formed on a surface of the sealing body to which the adhesive sheet is bonded (for example, japanese patent application laid-open No. 2014-210909 (patent document 1)). In patent document 1, the adhesive sheet includes a support and an adhesive layer laminated on the support, and the semiconductor chip is disposed on the adhesive sheet using a flip chip mounter or a chip mounter.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 2014-210909
Disclosure of Invention
The invention provides a semiconductor manufacturing apparatus and a semiconductor device manufacturing method for accurately placing a semiconductor chip (bare chip) on a substrate such as an adhesive sheet to be finally peeled.
A brief summary of a representative embodiment of the present invention will be described below.
That is, the semiconductor manufacturing apparatus includes: a bare chip supply section; a pick-up head for picking up the bare chip from the bare chip supply part and turning the bare chip upside down; a mounting head that picks up the bare chip from the pickup head, and mounts the bare chip on an upper surface of a transparent substrate with a circuit formation surface of the bare chip facing down; a fiducial mark for identifying a position of the bare chip when the bare chip is mounted on the substrate; a camera which photographs the bare chip and the reference mark from below the substrate; and an illumination device that irradiates light to the bare chip and the reference mark from obliquely below.
Effects of the invention
According to the semiconductor manufacturing apparatus, the accuracy of placing the bare chip can be improved.
Drawings
Fig. 1 is a schematic plan view of a flip chip mounter according to embodiment 1.
Fig. 2 is a diagram illustrating the actions of the pickup head and the mounting head when viewed from the direction of arrow a in fig. 1.
Fig. 3 is a schematic cross-sectional view showing a main portion of the bare chip supply portion of fig. 1.
Fig. 4 is a schematic plan view showing the layout of the flip chip mounter of fig. 1.
Fig. 5 is a cross-sectional view for explaining the structure of the workpiece and die placement of fig. 1.
Fig. 6 is a flowchart for explaining a bare chip placing method of the flip chip mounter of fig. 1.
Fig. 7 is a schematic plan view showing the layout of the flip chip mounter according to modification 1.
Fig. 8 is a schematic plan view showing the layout of the flip chip mounter according to modification 2.
Fig. 9 is a cross-sectional view for explaining the structure of the work and the placement of the bare chip in the flip chip mounter according to modification 3.
Fig. 10 is a cross-sectional view for explaining the structure of the work and the placement of the bare chip in the flip chip mounter according to modification 4.
Fig. 11 is a schematic plan view of the chip mounter according to embodiment 2.
Fig. 12 is a view for explaining the operation of the pick-up head and the mounting head when viewed from the direction of arrow a in fig. 11.
Fig. 13 is a flowchart for explaining a bare chip placing method of the chip mounter of fig. 11.
Description of the reference numerals
1: bare chip supply unit
2: pickup part
21: pick-up head
22: cartridge clip part
3: turnover mechanism part
4: mounting part
41: mounting head
42: cartridge clip part
44: substrate identification camera
45: oblique light lighting device
7: control device
10: flip chip mounter
10E: chip mounter
11: wafer with a plurality of chips
13: jacking unit
D: bare chip
W: workpiece
101: glass substrate
102: adhesive agent
103: belt
104: glass substrate
PM: position identification mark
BS: pasting table
Detailed Description
Hereinafter, embodiments and modifications will be described with reference to the drawings. In the following description, the same components are denoted by the same reference numerals, and redundant description thereof may be omitted. In order to make the description more clear, the drawings schematically show the width, thickness, shape, and the like of each part as compared with the actual form, but the drawings are merely examples in principle and do not limit the explanation of the present invention.
[ example 1 ]
Fig. 1 is a schematic plan view of a flip chip mounter according to embodiment 1. Fig. 2 is a diagram illustrating the actions of the pickup head and the mounting head when viewed from the direction of arrow a in fig. 1.
The flip chip mounter 10 as a semiconductor manufacturing apparatus is roughly divided into a bare chip supply unit 1, a pickup unit 2, a turnover mechanism unit 3, a mounting unit 4, a conveying unit 5, a substrate supply unit 6K, a substrate carry-out unit 6H, and a control unit 7 that monitors and controls the operations of the respective units.
First, the bare chip supply unit 1 supplies the bare chip D mounted on the workpiece W such as a substrate. The bare chip supply unit 1 includes a wafer holding table 12 for holding the wafer 11, a lift unit 13 indicated by a broken line for lifting the bare chip D from the wafer 11, and a wafer ring supply unit (not shown). The bare chip supply unit 1 moves in the XY direction by a drive mechanism not shown, and moves the bare chip D to be picked up to the position of the lift unit 13. The wafer ring supply unit has a wafer cassette in which a wafer ring is stored, and sequentially supplies the wafer ring to the die supply unit 1, and replaces the wafer ring with a new wafer ring. The die supply 1 moves the wafer ring to a pick-up point to enable a desired die to be picked up from the wafer ring. The wafer ring is a jig for fixing the wafer and capable of being mounted on the bare chip supply unit 1.
The pickup section 2 includes: a collet section 22 for sucking the bare chip D from the bare chip supply section 1; a pickup head 21 having a collet part 22 at a tip end thereof and picking up a bare chip D; and a Y drive section 23 that moves the pickup head 21 in the Y direction. The pickup head 21 includes driving units, not shown, for moving the collet 22 up and down, rotating, and moving in the X direction. With such a configuration, the pickup head 21 picks up the bare chip, moves to the reversing mechanism portion 3, and is attracted to the reversing mechanism portion 3.
As shown by a broken line in fig. 2, the reversing mechanism portion 3 reverses the surface (pattern forming surface) of the bare chip D to face downward by rotating the pickup head 21 by 180 degrees, and takes a posture of delivering the bare chip D to the mounting head 41. As another method of the turnover mechanism portion, there are a method of providing the turnover mechanism portion to the pickup head 21 and moving the turnover mechanism portion together with the pickup head as shown in the drawing of fig. 2, a method of providing a stage unit capable of rotating the front and back of the bare chip and temporarily mounting the picked-up bare chip D on the stage unit, and the like.
The mounting section 4 receives the flipped bare chip D from the pickup head 21, and mounts the flipped bare chip D on the conveyed workpiece W. The mounting portion 4 has: a mounting head 41 including a collet 42 for holding the bare chip D by suction at the tip end thereof, similarly to the pickup head 21; a Y drive unit 43 that moves the mounting head 41 in the Y direction; a substrate recognition camera 44 that takes an image of a position recognition mark (reference mark) PM (see fig. 4) of the workpiece W and recognizes the mounting position; and an oblique light illumination device 45 (refer to fig. 4) discussed later. Further, a substrate recognition camera for inspecting the workpiece W may be provided. With this configuration, the mounting head 41 receives the flipped bare chip D from the pickup head 21, corrects the pickup position and the attitude based on the imaging data of the bare chip recognition camera 33, and mounts the bare chip D on the workpiece W based on the imaging data of the substrate recognition camera 44.
The conveying unit 5 includes conveying rails 51 and 52 for moving the workpiece W in the X direction. The conveying rails 51, 52 are arranged in parallel. With such a configuration, the workpiece W is carried out from the substrate supply unit 6K, moved to the mounting position along the conveying rails 51 and 52, moved to the substrate carry-out unit 6H after mounting, and delivered to the substrate carry-out unit 6H. In the process of mounting the bare chip D on the workpiece W, the substrate supply unit 6K carries out a new workpiece W and stands by on the conveying rails 51 and 52.
Fig. 3 is a schematic cross-sectional view showing a main part of a bare chip supply section. As shown in fig. 3, the bare chip supply unit 1 includes: an extension ring 15 that holds the wafer ring 14; a support ring 17 for horizontally positioning the dicing tape 16, which is held by the wafer ring 14 and to which the plurality of bare chips D are bonded; and a jacking unit 13 for jacking the bare chip D upward. In order to pick up the predetermined die D, the jack-up unit 13 is moved in the vertical direction by a driving mechanism not shown, and the die supplying unit 1 is moved in the horizontal direction.
The bare chip supply unit 1 lowers the extension ring 15 holding the wafer ring 14 when the bare chip D is pushed up. As a result, the dicing tape 16 held by the wafer ring 14 is pulled, and the interval between the bare chips D is expanded. In this state, the bare chip D is lifted up from below the bare chip by the lifting unit 13, whereby the bare chip supplying section 1 improves the pick-up property of the bare chip D.
Fig. 4 is a schematic plan view showing the layout of the flip chip mounter of fig. 1. The flip chip mounter 10 is arranged as a device in which the workpiece W is conveyed in the X direction and the bare chip D is conveyed in the Y direction.
A wafer ring supply unit 18 is provided on the X-axis negative direction side (left side in the drawing) of the bare chip supply unit 1, and a mounting position BP is provided on the Y-axis positive direction side (upper side in the drawing). The conveying rails 51 and 52 extend in the X-axis direction, and the workpiece W is moved in the X-axis positive direction (from left to right in the drawing) and sent to the mounting position BP. The wafer ring 14 is conveyed in the positive X-axis direction (from left to right in the drawing) from the wafer ring supply unit 18, and is sent to the die supply unit 1. The position DP is a position at which the pickup head 21 picks up the bare chip D from the bare chip supply section 1. The position PP is a position where the mounting head 41 picks up the bare chip D from the pickup head 21. The mounting position BP is a position at which the mounting head 41 mounts the bare chip D on the workpiece W, and the position WP is a position at which the next workpiece W stands by. Although not shown in fig. 4, the substrate supply unit 6K is disposed on the X-axis negative direction side (left side in the drawing) of the conveyance rails 51 and 52, and the substrate carry-out unit 6H is disposed on the X-axis positive direction side (right side in the drawing).
Fig. 5 is a cross-sectional view for explaining the structure of the workpiece and the placement of the bare chip in fig. 1, and is a view showing the arrangement of the workpiece, the bare chip, the camera, and the illumination at the mounting position. The work W is composed of a glass substrate 101 as a carrier having the position recognition mark PM and an adhesive 102 provided on the glass substrate 101, and can mount a plurality of bare chips. A position recognition mark PM corresponding to the package size is formed on the lower surface side of the glass substrate 101. The workpiece W is finally peeled off from the bare chip D, and the glass substrate 101 is reused by forming the position recognition mark PM and the like again. The bare chip D is attached to the collet 42 so that the patterned surface faces downward (face down). The substrate recognition camera 44 is disposed directly below the bare chip D, and recognizes the position of the bare chip D through the glass substrate 101 and the adhesive 102. Thus, the glass substrate 101 and the adhesive 102 are transparent. The plurality of oblique illumination devices 45 irradiate the position recognition marks PM and the bare chips D with light from obliquely below, respectively. The oblique illumination device 45 can observe the surface of the position recognition mark PM and the surface of the bare chip D without causing regular reflection of the glass substrate.
The control device 7 includes: a memory for storing a program (software) for monitoring and controlling the operation of each part of the flip chip mounter 10; and a Central Processing Unit (CPU) that executes a program stored in the memory. For example, the control device 7 takes in various information such as image information from the bare chip recognition camera 33 and the board recognition camera 44 and the position of the mounting head 41, and controls the operations of the components such as the mounting operation of the mounting head 41.
Next, a bare chip placement method (a method of manufacturing a semiconductor device) of the flip chip mounter of embodiment 1 will be described with reference to fig. 6. Fig. 6 is a flowchart for explaining a bare chip placing method of the flip chip mounter of fig. 1.
Step S1: the control device 7 picks up the bare chip D from the bare chip supply section 1 by the pick-up head 21.
Step S2: the control device 7 turns over the pickup head 21 so that the surface (back surface) of the bare chip D opposite to the circuit forming surface faces upward.
Step S3: the control device 7 delivers the bare chip D to the mounting head 41. That is, the mounting head 41 picks up the bare chip D from the pickup head 21.
Step S4: the control device 7 recognizes the position recognition mark PM of the glass substrate 101 by the substrate recognition camera 44.
Step S5: the control device 7 recognizes the pattern of the circuit forming surface (surface) of the bare chip D by the substrate recognition camera 44. Oblique illumination was irradiated through the glass from below to identify the edge of the bare chip D until just before placement. At this time, simultaneous 1-field recognition is desired.
Step S6: the control device 7 calculates the recognition result. The position recognition mark PM is recognized to calculate the placement position, and the bare chip D is recognized to calculate the bare chip position.
Step S7: the control device 7 moves the mounting head 41 based on the calculation result to correct the position of the bare chip D.
Step S8: the controller 7 places (places) the bare chip D on the workpiece W.
Before step S1, the wafer ring 14 holding the dicing tape 16 to which the bare chips D separated from the wafer 11 are bonded is stored in the wafer ring supply unit 18 and is carried into the flip chip mounter 10. The control device 7 supplies the wafer ring 14 to the die supply portion 1 from the wafer ring supply portion 18 filled with the wafer ring 14. Further, the work W is prepared and carried into the flip chip mounter 10. The controller 7 places the workpiece W on the conveying rails 51 and 52 by the substrate supply unit 6K.
After step S8, the controller 7 takes out the workpiece W with the bare chip D mounted thereon from the conveying rails 51 and 52 by the substrate carry-out section 6H. The work W is carried out from the flip chip mounter 10. Then, a plurality of bare chips (semiconductor chips) arranged on the adhesive 102 of the work W are collectively sealed with a sealing resin to form a sealed body including the plurality of semiconductor chips and the sealing resin covering the plurality of semiconductor chips, and then the work W is peeled off from the sealed body, and then a rewiring layer is formed on a surface of the sealed body to which the work W is bonded, thereby manufacturing a FOWLP.
< modification example >
Hereinafter, some representative modifications will be described. In the following description of the modified examples, the same reference numerals as those of the above-described embodiments can be used for the portions having the same configurations and functions as those of the portions described in the above-described embodiments. In the description of the above-mentioned embodiments, the description can be appropriately applied to the extent that the technical contradiction is not present. In addition, a part of the above-described embodiments and all or a part of the plurality of modifications can be appropriately combined and applied within a range where there is no technical contradiction.
(modification 1)
Fig. 7 is a schematic plan view showing the layout of the flip chip mounter according to modification 1. In example 1 (fig. 1), the workpiece W is conveyed in the X direction and the bare chip D is conveyed in the Y direction, but in the flip chip mounter 10A of modification 1, both the workpiece W and the bare chip D are conveyed in the X direction.
A wafer ring supply unit 18 is provided on the Y-axis negative direction side (lower side in the drawing) of the die supply unit 1, and a mounting position BP is provided on the X-axis positive direction side (right side in the drawing). The conveying rails 51 and 52 are provided above the bare chip supply unit 1, and the workpiece W is moved in the X-axis positive direction (from the left to the right in the drawing) and sent to the substrate stage 46. Thereafter, the substrate stage 46 moves in the positive Y-axis direction (upward from the bottom of the drawing) to transport the workpiece W to the mounting position BP. The wafer ring 14 is conveyed in the positive Y-axis direction (downward and upward in the drawing) from the wafer ring supply unit 18, and is sent to the die supply unit 1. The position DP is a position at which the pickup head 21 picks up the bare chip D from the bare chip supply section 1. The position PP is a position where the mounting head 41 picks up the bare chip D from the pickup head 21. The position BP is a position at which the mounting head 41 mounts the bare chip D on the workpiece W, and the position WP is a position at which the next workpiece W stands by. Although not shown in fig. 7, the substrate supply unit 6K is disposed on the X-axis negative direction side (left side in the drawing) of the conveyance rails 51 and 52, and the substrate carry-out unit 6H is disposed on the X-axis positive direction side (right side in the drawing).
(modification 2)
Fig. 8 is a schematic plan view showing the layout of the flip chip mounter according to modification 2. In the embodiment (fig. 1), the workpiece W is conveyed in the X direction and the bare chip D is conveyed in the Y direction, but in the flip chip mounter 10B of modification 2, the workpiece W is conveyed in the Y direction and the bare chip D is conveyed in the X direction.
A wafer ring supply unit 18 is provided on the Y-axis negative direction side (lower side in the drawing) of the die supply unit 1, and a mounting position BP is provided on the X-axis positive direction side (right side in the drawing). The workpiece W is moved from the workpiece supply and discharge unit 61 in the Y-axis positive direction (downward and upward in the drawing) and sent to the substrate stage 46. Thereafter, the substrate stage 46 conveys the workpiece W to the mounting position BP. After mounting, the substrate stage 46 conveys the workpiece W in the Y-axis negative direction (downward from the top of the drawing), and the workpiece W is sent to the workpiece supply and discharge section 61. The wafer ring 14 is conveyed in the positive Y-axis direction (downward and upward in the drawing) from the wafer ring supply unit 18, and is sent to the die supply unit 1. The position DP is a position at which the pickup head 21 picks up the bare chip D from the bare chip supply section 1. The position PP is a position where the mounting head 41 picks up the bare chip D from the pickup head 21. The position BP is a position at which the mounting head 41 mounts the bare chip D on the workpiece W, and the position WP is a position at which the next workpiece W stands by. In modification 2, the work supply and discharge unit 61 is disposed adjacent to the right side of the wafer ring supply unit 18 instead of the substrate supply unit 6K and the substrate carry-out unit 6H, and therefore the planar area of the die mounter can be reduced as compared with embodiment 1 and modification 1.
(modification 3)
Fig. 9 is a cross-sectional view for explaining the structure of the workpiece and the placement of the bare chip in the flip chip mounter according to modification 3, and is a view showing the arrangement of the workpiece, the bare chip, the mounting table, the camera, and the illumination at the mounting position. In example 1, the work W is made of a glass substrate, but the work W of the flip chip mounter 10C of modification 3 is made of a tape.
The workpiece W of modification 3 is composed of a tape 103 as a carrier and an adhesive 102 provided on the tape 103, and can mount a plurality of bare chips. The mounting table BS is made of a transparent substrate (glass substrate), and a position recognition mark PM is formed on the lower surface side of the glass substrate of the mounting table BS. The bare chip D is attached to the collet 42 so that the pattern surface faces downward (face down). The substrate recognition camera 44 is disposed directly below the bare chip D, and recognizes the position of the bare chip D through the mounting table BS, the tape 103, and the adhesive 102. Thus, the tape 103 and the adhesive 102 are transparent. The plurality of oblique illumination devices 45 irradiate the position recognition marks PM and the bare chips D with light from obliquely below, respectively. The oblique illumination device 45 allows the surface of the position recognition mark PM and the surface of the bare chip D to be observed without causing regular reflection of the glass substrate of the mounting table BS.
(modification 4)
Fig. 10 is a cross-sectional view for explaining the structure of the workpiece and the placement of the bare chip in the flip chip mounter according to modification 4, and is a view showing the arrangement of the workpiece, the bare chip, the mounting table, the camera, and the illumination at the mounting position. The work W of the flip chip mounter 10D of modification 4 is formed of a glass substrate 104 as in embodiment 1, but a mounting table BS formed of a transparent substrate (glass substrate) is further provided below the glass substrate 104 of the work W, and a position recognition mark PM is formed on the lower surface side of the glass substrate of the mounting table BS, as in modification 3. This eliminates the need to form the position recognition mark PM on the glass substrate on which the bare chip is placed, and facilitates recycling.
[ example 2 ]
Fig. 11 is a schematic plan view of the chip mounter according to embodiment 2. Fig. 12 is a view for explaining the operation of the pick-up head and the mounting head when viewed from the direction of arrow a in fig. 11.
The die mounter 10E as a semiconductor manufacturing apparatus is roughly divided into a bare chip supply unit 1, a pickup unit 2E, an intermediate stage unit 3E, a mounting unit 4E, a conveying unit 5, a substrate supply unit 6K, a substrate carry-out unit 6H, and a control device 7 that monitors and controls operations of the respective units.
The pickup section 2E has: a pickup head 21 that picks up the bare chip D; a Y drive section 23 of the pickup head which moves the pickup head 21 in the Y direction; and driving portions, not shown, for moving the collet portion 22 up and down, rotating, and moving in the X direction. The pickup head 21 has a collet part 22 (see fig. 12) for sucking and holding the lifted bare chip D at the tip end thereof, and picks up the bare chip D from the bare chip supply part 1 and mounts the bare chip D on the intermediate stage 31. The pickup head 21 includes driving units, not shown, for moving the collet 22 up and down, rotating, and moving in the X direction. Unlike embodiment 1, the pickup unit 2 of embodiment 2 does not have a function of rotating the pickup head 21 by 180 degrees to turn the front and back of the bare chip.
The intermediate stage portion 3E includes: an intermediate stage 31 on which a bare chip D is temporarily placed; and a stage recognition camera 32 for recognizing the bare chip D on the intermediate stage 31.
The mounting portion 4E picks up the bare chip D from the intermediate stage 31, and mounts the bare chip D on the conveyed workpiece W. The mounting portion 4E has: a mounting head 41 including a collet 42 (see fig. 12) for holding the bare chip D by suction at the tip end thereof, similarly to the pickup head 21; a Y drive unit 43 that moves the mounting head 41 in the Y direction; a board recognition camera 44 that images a position recognition mark PM (see fig. 5) of the workpiece W to recognize a mounting position; and an oblique illumination device 45 (see fig. 5). Further, a substrate recognition camera for inspecting the workpiece W may be provided. The structure of the workpiece W may be any of the structures of the embodiment (fig. 5), the modification 3 (fig. 9), and the modification 4 (fig. 10). With such a configuration, the mounting head 41 corrects the pickup position and the attitude based on the imaging data of the stage recognition camera 32, picks up the bare chip D from the intermediate stage 31, and mounts the bare chip D on the workpiece W based on the imaging data of the substrate recognition camera 44.
Next, a method of placing a bare chip (a method of manufacturing a semiconductor device) in the die mounter according to example 2 will be described with reference to fig. 13. Fig. 13 is a flowchart for explaining a bare chip placing method of the chip mounter of fig. 11.
Step S1: the control device 7 picks up the bare chip D from the supply section 1 by the pickup head 21.
Step S2D: the control device 7 mounts the bare chip D on the intermediate stage 31 by the pickup head 21.
Step S3D: the control device 7 delivers the bare chip D to the mounting head 41. That is, the mounting head 41 picks up the bare chip D from the intermediate stage 31.
Step S4: the control device 7 recognizes the position recognition mark PM of the glass substrate 101 by the substrate recognition camera 44.
Step S5: the control device 7 recognizes the edge of the bare chip D using the substrate recognition camera 44. The edge of the bare chip D is recognized until just before the bare chip D is placed by irradiating oblique illumination through the glass from the lower part. At this time, simultaneous 1-field recognition is desired.
Step S6: the control device 7 calculates the recognition result. The position recognition mark PM is recognized to calculate the placement position, and the bare chip D is recognized to calculate the bare chip position.
Step S7: the control device 7 moves the mounting head 41 based on the calculation result to correct the position of the bare chip D.
Step S8: the controller 7 places (places) the bare chip D on the workpiece W.
The operation before step S1 is the same as that of embodiment 1. The operation of taking out and carrying out the mounted workpiece W is the same as in example 1. FOWLP was produced in the same manner as in example 1.
In the embodiment and the modification, when the workpiece is a glass substrate, the mark (position recognition mark) of the package size determined is marked on the workpiece or the stage where transparency is secured, and when the workpiece is a tape, the mark of the package size is marked on the stage where transparency is secured. Thus, the workpiece can be recognized and mounted, and the position of the bare chip can be recognized and corrected immediately before the bare chip is placed. Therefore, the bare chip can be accurately placed on the glass or tape to be finally peeled. When the workpiece is glass, the position recognition mark can be accurately produced and can be reused.
In the case of Face Down (Face Down), the pattern on the surface of the bare chip can be recognized through the glass, and alignment can be performed. This can ensure higher accuracy of the placed reference. By making the placing accuracy good, the rewiring layer of the FOWLP can be easily performed.
The invention made by the present inventors has been specifically described above based on the embodiments and modifications, but the present invention is not limited to the embodiments and modifications described above, and it goes without saying that various modifications are possible.
For example, in the embodiment, the position recognition is performed by forming the position recognition mark PM on the lower surface side of the glass substrate, but the position recognition of the bare chip D may be performed by temporarily forming the position recognition mark PM by laser light irradiation or the like. Accordingly, it is not necessary to form the position recognition mark PM on the glass substrate on which the bare chip is placed, the regeneration is easy, and the change of the die size and the bare chip placement position by the change of the type, etc. can be performed by the change of the data of the laser irradiation position, etc., and the work can be simplified.
The position recognition mark PM on the lower surface side of the glass substrate may be formed not on the substrate on which the bare chip is placed or on the device stage made of transparent glass of the work constituted by the tape, but on a substrate made of transparent glass on which the position recognition mark PM is formed for each type of product. Thus, when the product is replaced, the position recognition substrate can be replaced easily by replacing the position recognition substrate, and automatic replacement and the like are also facilitated.
In addition, the position recognition substrate may also use the glass substrate for bare chip placement of the embodiment.
Claims (18)
1. A semiconductor manufacturing apparatus is characterized by comprising:
a bare chip supply section;
a pick-up head for picking up the bare chip from the bare chip supply part and turning the bare chip upside down;
a mounting head that picks up the bare chip from the pickup head, and mounts the bare chip on an upper surface of a transparent substrate with a circuit formation surface of the bare chip facing down;
a fiducial mark for identifying a position of the bare chip when the bare chip is mounted on the substrate;
a camera which photographs the bare chip and the reference mark from below the substrate; and
an illumination device that irradiates the bare chip and the reference mark with light from obliquely below,
the reference mark is provided on the lower surface side of the substrate,
the camera shoots the bare chip through the substrate, and the camera shoots the reference mark.
2. The semiconductor manufacturing apparatus according to claim 1,
the substrate includes a glass substrate and an adhesive provided on an upper surface of the glass substrate.
3. The semiconductor manufacturing apparatus according to claim 1,
the semiconductor manufacturing apparatus further includes a transparent stage positioned above the camera head,
the substrate has a tape and an adhesive provided on an upper surface of the tape,
the reference mark is arranged on the lower surface of the carrier.
4. The semiconductor manufacturing apparatus according to claim 1,
the semiconductor manufacturing apparatus further includes a wafer ring supply unit for receiving a wafer ring, a substrate supply unit, and a substrate carry-out unit,
the wafer ring is transported from the wafer ring supply portion in a first direction and sent to the die supply portion,
the substrate is conveyed from the substrate supply unit in the first direction and is carried to a mounting position,
the bare chip is transported in a second direction different from the first direction and is carried to a mounting position,
the substrate on which the bare chip is mounted is transported from the mounting position in the first direction and sent to the substrate carry-out section.
5. The semiconductor manufacturing apparatus according to claim 1,
the semiconductor manufacturing apparatus further includes a wafer ring supply unit for receiving a wafer ring, a substrate supply unit, and a substrate carry-out unit,
the substrate is conveyed from the substrate supply part to a first direction and is sent to a mounting position,
the bare chip is transported in the first direction to be carried to a mounting position,
the substrate on which the bare chip is mounted is transported from the mounting position in the first direction and is sent to the substrate carry-out section,
the wafer ring is conveyed from the wafer ring supply unit in a second direction different from the first direction and is sent to the die supply unit.
6. The semiconductor manufacturing apparatus according to claim 1,
the semiconductor manufacturing apparatus further includes a wafer ring supply unit for receiving a wafer ring, and a substrate supply/discharge unit,
the bare chip is transported in a first direction to be carried to a mounting position,
the wafer ring is conveyed from the wafer ring supply portion in a second direction different from the first direction and is sent to the die supply portion,
the substrate is conveyed from the substrate supply and discharge unit in a second direction and is sent to a mounting position,
the substrate on which the bare chip is mounted is transported from the mounting position in a direction opposite to the second direction and sent to the substrate supply and discharge unit.
7. A semiconductor manufacturing apparatus is characterized by comprising:
a bare chip supply section;
a pick-up head which picks up a bare chip from the bare chip supply section;
an intermediate stage on which a bare chip picked up by the pickup head is placed;
a mounting head that picks up a bare chip mounted on the intermediate stage, mounts the bare chip on an upper surface of a transparent substrate with a circuit formation surface of the bare chip facing upward;
a fiducial mark for identifying a position of the bare chip when the bare chip is mounted on the substrate;
a camera which photographs the bare chip and the reference mark from below the substrate; and
an illumination device that irradiates the bare chip and the reference mark with light from obliquely below,
the reference mark is provided on the lower surface side of the substrate,
the camera shoots the bare chip through the substrate, and the camera shoots the reference mark.
8. The semiconductor manufacturing apparatus according to claim 7,
the substrate includes a glass substrate and an adhesive provided on an upper surface of the glass substrate.
9. The semiconductor manufacturing apparatus according to claim 7,
the semiconductor manufacturing apparatus further includes a transparent stage positioned above the camera head,
the substrate has a tape and an adhesive provided on an upper surface of the tape,
the reference mark is arranged on the lower surface of the carrier.
10. The semiconductor manufacturing apparatus according to claim 7,
the substrate comprises a glass substrate and an adhesive provided on the upper surface of the glass substrate,
the semiconductor manufacturing apparatus includes a transparent stage positioned above the camera head,
the reference mark is arranged on the lower surface of the carrier.
11. A method for manufacturing a semiconductor device, comprising the steps of:
(a) preparing a semiconductor manufacturing apparatus including a camera for imaging a bare chip and a reference mark, and an illumination device for irradiating the bare chip and the reference mark with light from obliquely below;
(b) a step of preparing a wafer ring for holding a dicing tape having bare chips;
(c) preparing a substrate including a glass substrate and an adhesive provided on an upper surface of the glass substrate, the reference mark being provided on a lower surface side of the glass substrate;
(d) a step of picking up the bare chip from the wafer ring; and
(e) a step of mounting the picked bare chip on the substrate,
in the step (e), the picked-up bare chip is placed on the upper surface of the substrate while the picked-up bare chip is photographed by the camera from below the substrate through the substrate and the reference mark is photographed by the camera from below the substrate.
12. The method for manufacturing a semiconductor device according to claim 11,
the step (d) further includes a step of turning the picked bare chip upside down,
in the step (e), the bare chip is picked up after being turned upside down, and the bare chip is mounted on the substrate with the circuit formation surface of the bare chip facing downward.
13. The method for manufacturing a semiconductor device according to claim 11,
the step (d) further includes a step of placing the picked bare chip on an intermediate stage,
in the step (e), the bare chip mounted on the intermediate stage is picked up, and the bare chip is mounted on the substrate with the circuit formation surface of the bare chip facing upward.
14. The method for manufacturing a semiconductor device according to claim 12 or 13,
in the step (e), the position of the picked-up bare chip is corrected based on the recognition result of the camera, and then the bare chip is mounted on the substrate.
15. A method for manufacturing a semiconductor device, comprising the steps of:
(a) preparing a semiconductor manufacturing apparatus including a camera for imaging a bare chip and a reference mark provided on a lower surface side of a mounting table, and an illumination device for irradiating the bare chip and the reference mark with light from obliquely below;
(b) a step of preparing a wafer ring for holding a dicing tape having bare chips;
(c) a step of preparing a substrate having a tape and an adhesive provided on an upper surface of the tape;
(d) a step of picking up the bare chip from the wafer ring; and
(e) a step of mounting the picked bare chip on the substrate,
in the step (e), the picked-up bare chip is placed on the upper surface of the substrate while the picked-up bare chip is imaged by the camera from below the mounting table through the mounting table and the substrate and the reference mark is imaged by the camera from below the mounting table.
16. The method for manufacturing a semiconductor device according to claim 15,
the step (d) further includes a step of turning the picked bare chip upside down,
in the step (e), the bare chip is picked up after being turned upside down.
17. The method for manufacturing a semiconductor device according to claim 15,
the step (d) further includes a step of placing the picked bare chip on an intermediate stage,
in the step (e), the bare chip mounted on the intermediate stage is picked up.
18. The method for manufacturing a semiconductor device according to claim 16 or 17,
in the step (e), the position of the picked-up bare chip is corrected based on the recognition result of the camera, and then the bare chip is mounted on the substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| JP2017-023850 | 2017-02-13 | ||
| JP2017023850A JP6849468B2 (en) | 2017-02-13 | 2017-02-13 | Semiconductor manufacturing equipment and manufacturing method of semiconductor equipment |
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| CN108428643A CN108428643A (en) | 2018-08-21 |
| CN108428643B true CN108428643B (en) | 2022-03-29 |
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| JP (1) | JP6849468B2 (en) |
| KR (1) | KR102062121B1 (en) |
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| JP7285162B2 (en) * | 2019-08-05 | 2023-06-01 | ファスフォードテクノロジ株式会社 | Die bonding apparatus and semiconductor device manufacturing method |
| JP7436251B2 (en) | 2020-03-16 | 2024-02-21 | ファスフォードテクノロジ株式会社 | Die bonding equipment and semiconductor device manufacturing method |
| JP2022145332A (en) | 2021-03-19 | 2022-10-04 | ファスフォードテクノロジ株式会社 | Die bonding device and method for manufacturing semiconductor device |
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| JP3190575B2 (en) * | 1996-08-28 | 2001-07-23 | シャープ株式会社 | Chip arrangement device |
| JP2003218137A (en) * | 2002-01-23 | 2003-07-31 | Hitachi Ltd | Semiconductor chip mounting method and device |
| JP2004039736A (en) * | 2002-07-01 | 2004-02-05 | Shinko Electric Ind Co Ltd | Device and method for mounting semiconductor chip |
| WO2005008726A2 (en) * | 2003-07-09 | 2005-01-27 | Newport Corporation | Flip chip device assembly machine |
| TW201011849A (en) * | 2008-09-03 | 2010-03-16 | King Yuan Electronics Co Ltd | Bare die dual-face detector |
| TWI381200B (en) * | 2008-11-11 | 2013-01-01 | Au Optronics Suzhou Corp | Alignment inspection method and apparatus |
| WO2012042653A1 (en) * | 2010-09-30 | 2012-04-05 | 富士電機株式会社 | Method of manufacturing semiconductor device |
| WO2012133760A1 (en) * | 2011-03-30 | 2012-10-04 | ボンドテック株式会社 | Electronic component mounting method, electronic component mounting system, and substrate |
| JP5989313B2 (en) * | 2011-09-15 | 2016-09-07 | ファスフォードテクノロジ株式会社 | Die bonder and bonding method |
| JP5813432B2 (en) * | 2011-09-19 | 2015-11-17 | ファスフォードテクノロジ株式会社 | Die bonder and bonding method |
| US8871605B2 (en) * | 2012-04-18 | 2014-10-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for fabricating and orienting semiconductor wafers |
| JP6093610B2 (en) * | 2013-03-15 | 2017-03-08 | ファスフォードテクノロジ株式会社 | Die bonder and bonding method |
| JP2014210909A (en) | 2013-04-02 | 2014-11-13 | 日東電工株式会社 | Manufacturing method of semiconductor device |
| JP6118620B2 (en) * | 2013-04-03 | 2017-04-19 | ヤマハ発動機株式会社 | Component mounting equipment |
| JP6211359B2 (en) * | 2013-09-18 | 2017-10-11 | ファスフォードテクノロジ株式会社 | Flip chip bonder and bonding method |
| JP6411823B2 (en) * | 2014-09-09 | 2018-10-24 | ボンドテック株式会社 | Chip alignment method and chip alignment apparatus |
| JP6124969B2 (en) * | 2015-09-24 | 2017-05-10 | ファスフォードテクノロジ株式会社 | Die bonder and bonding method |
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| TW201836048A (en) | 2018-10-01 |
| JP2018133353A (en) | 2018-08-23 |
| JP6849468B2 (en) | 2021-03-24 |
| TWI677047B (en) | 2019-11-11 |
| KR102062121B1 (en) | 2020-01-03 |
| CN108428643A (en) | 2018-08-21 |
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