CN108074974B - 半导体装置的形成方法 - Google Patents

半导体装置的形成方法 Download PDF

Info

Publication number
CN108074974B
CN108074974B CN201710076208.5A CN201710076208A CN108074974B CN 108074974 B CN108074974 B CN 108074974B CN 201710076208 A CN201710076208 A CN 201710076208A CN 108074974 B CN108074974 B CN 108074974B
Authority
CN
China
Prior art keywords
forming
semiconductor substrate
oxide layer
layer
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710076208.5A
Other languages
English (en)
Other versions
CN108074974A (zh
Inventor
温文莹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nuvoton Technology Corp
Original Assignee
Nuvoton Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nuvoton Technology Corp filed Critical Nuvoton Technology Corp
Publication of CN108074974A publication Critical patent/CN108074974A/zh
Application granted granted Critical
Publication of CN108074974B publication Critical patent/CN108074974B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

本发明涉及半导体装置的形成方法，半导体装置的形成方法包含形成第一氮化层于半导体基底上，形成第一氧化层于第一氮化层上，形成第一沟槽穿过第一氧化层、第一氮化层和一部份的半导体基底，形成第一间隙物于第一沟槽的侧壁上，以第一间隙物为遮罩，在半导体基底内形成第二沟槽，移除第一氧化层以形成第三沟槽，形成第二氧化层于第二沟槽内，第二氧化层侧向延伸至半导体基底内且位于第一间隙物的下方，形成第二间隙物于第三沟槽的侧壁上，以及以第二间隙物为遮罩，刻蚀移除部分的第一氮化层和部分的半导体基底，形成鳍状结构于第二氧化层上。

Description

半导体装置的形成方法
技术领域
本发明是关于半导体装置，特别是有关于使用绝缘层上覆硅(silicon oninsulator，SOI)基底的鳍式场效晶体管(fin field effect transistor，FinFET)的半导体装置的形成方法。
背景技术
在半导体装置的产业中，鳍式场效晶体管的导入是一大进展，其三维的配置超越了平面晶体管所展现的基本效能和功效特性。鳍式场效晶体管具有竖立的鳍状结构(finstructure)，自基底垂直向上延伸，鳍状结构内具有沟道(channel)，而鳍状结构上具有栅极结构环绕着沟道，使得栅极结构可自多端控制沟道。鳍式场效晶体管具有降低阈值电压、减少漏电流以及提高效能的好处。
另一方面，近年来，绝缘层上覆硅的技术被广泛地用于积体电路的设计上，相较于传统的块材(bulk)半导体基底，绝缘层上覆硅基底由于具有埋植氧化层，不会产生闭锁效应(latch-up effect)，且具有较低的寄生电容、速度较快、较强的抗辐射能力，减少发生软式错误(soft error)的机会，以及受短沟道效应(short channel effect)的影响较小等优点。
虽然目前存在的半导体装置及其形成方法在鳍式场效晶体管的发展以及绝缘层上覆硅基底的应用上已足够应付它们原先预定的用途，但它们仍未在各个方面皆彻底的符合要求，因此半导体装置目前仍有需努力的方向。
发明内容
本发明的实施例利用第一间隙物的设置，是为制造绝缘层上覆硅(SOI)的架构，利用区域氧化隔离技术(Local Oxidation of Silicon,LOCOS)在半导体基底侧壁形成氧化层，避免基底全面被氧化。再者，本发明的实施例通过第二间隙物的设置，刻蚀半导体基底的一部分以在第二氧化层上形成尺寸精细的鳍状结构，使得鳍式场效晶体管在栅极施加电压时容易达到完全空乏的状态。此外，依据本发明的实施例，鳍状结构由半导体基底的一部分形成，其材料可为单晶硅，相较于以往通过沉积和退火形成的多晶硅鳍状结构具有开关电流比(Current on/off ratio，Ion/Ioff)较高的优势。
根据一些实施例，提供半导体装置的形成方法。此半导体装置的形成方法包含形成第一氮化层于半导体基底上，形成第一氧化层于第一氮化层上，形成第一沟槽穿过第一氧化层、第一氮化层和一部份的半导体基底。此半导体装置的形成方法还包含形成第一间隙物于第一沟槽的侧壁上，以第一间隙物为遮罩，在半导体基底内形成第二沟槽，移除第一氧化层以形成第三沟槽。此半导体装置的形成方法更包含形成第二氧化层于第二沟槽内，第二氧化层侧向延伸至半导体基底内且位于第一间隙物的下方，形成第二间隙物于第三沟槽的侧壁上，以及以第二间隙物为遮罩，刻蚀移除部分的第一氮化层和部分的半导体基底，形成鳍状结构于第二氧化层上。
根据一些实施例，提供采用上述半导体装置的形成方法形成的半导体装置。此半导体装置包含设置于半导体基底内且邻近半导体基底的表面的第二氧化层，设置于第二氧化层上的鳍状结构。此半导体装置更包含设置于鳍状结构、半导体基底和第二氧化层上的栅极介电层，以及设置于栅极介电层上的栅极电极层。
附图说明
通过以下的详述配合所附图式，我们能更加理解本发明的观点。值得注意的是，根据工业上的标准惯例，一些特征部件(feature)可能没有按照比例绘制。事实上，为了能清楚地讨论，不同特征部件的尺寸可能被增加或减少。
图1A-图1L是根据本发明的一些实施例，显示形成半导体装置的方法的不同阶段的剖面示意图；
图2是根据本发明的一些实施例，显示半导体装置的部份俯视图，其中图1L是显示沿图2线A-A’的剖面示意图。
附图标号
100a 半导体装置；
101 半导体基底；
102 第一沟槽；
103 第一氮化层；
104 第二沟槽；
105 第一氧化层；
106 第三沟槽；
107 图案化光阻层；
109 第二氮化层；
109a 第一间隙物；
111a、111b、111c、111d 第二氧化层；
113 第三氧化层；
113a、113b 第二间隙物；
117 栅极介电层；
119 栅极电极层；
C 连接部；
D 漏极区；
F 鳍状结构；
h 半导体基底图案的高度；
H 鳍状结构的高度；
P 半导体基底图案；
S 源极区；
W 鳍状结构的宽度。
具体实施方式
以下揭示提供了很多不同的实施例或范例，用于实施所提供的半导体装置的不同元件。各元件和其配置的具体范例描述如下，以简化本发明的说明。当然，这些仅仅是范例，并非用以限定本发明。举例而言，叙述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接触的实施例，也可能包含额外的元件形成在第一和第二元件之间，使得它们不直接接触的实施例。此外，本发明可能在不同的范例中重复参考数字及/或字母。如此重复是为了简明和清楚，而非用以表示所讨论的不同实施例及/或形态之间的关系。
以下描述实施例的一些变化。在不同图式和说明的实施例中，相似的参考数字被用来标明相似的元件。可以理解的是，在方法的前、中、后可以提供额外的操作，且一些叙述的操作可为了该方法的其他实施例被取代或删除。
本发明的实施例利用第一间隙物的设置，在半导体基底内形成第二氧化层，并通过第二间隙物的设置，刻蚀半导体基底的一部分以在第二氧化层上形成深度和宽度皆在约20nm至约250nm之间的鳍状结构，此鳍状结构由半导体基底形成，其材料可为单晶硅。本发明的实施例的半导体装置的形成方法具备了绝缘层上覆硅基底的优势，且能产生微细尺寸的鳍状结构，进而产生容易达到完全空乏状态的鳍式场效晶体管。此外，通过本发明的实施例，能制成单晶硅的鳍状结构，进而提高半导体装置的开关电流比。
图1A-图1L是根据本发明的一些实施例，显示形成图1L的半导体装置100a的方法的不同阶段的剖面示意图。
根据一些实施例，如图1A所示，提供半导体基底101。一些实施例中，半导体基底101可由单晶硅、多晶硅或其他半导体材料制成，或者，半导体基底101可包含其他元素半导体材料，例如锗(Ge)。一些实施例中，半导体基底101由化合物半导体制成，例如碳化硅、氮化镓、砷化镓、砷化铟或磷化铟。一些实施例中，半导体基底101由合金半导体制成，例如硅锗、碳化硅锗、磷化砷镓或磷化铟镓。一些实施例中，半导体基底101包含外延层。举例而言，半导体基底101有覆盖在块材半导体之上的外延层。一些实施例中，半导体基底101可为轻掺杂的P型或N型基底。一些实施例中，可在半导体基底101上形成垫氧化层(pad oxidelayer)，并于适当的区域离子注入N型或P型的掺质。
接着，参见图1A，在半导体基底101上形成第一氮化层103，在第一氮化层103上形成第一氧化层105，并在第一氧化层105上形成图案化光阻层107。一些实施例中，第一氮化层103的材料为氮化硅，第一氧化层105的材料为二氧化硅。一些实施例中，第一氮化层103和第一氧化层105是通过化学气相沉积(chemical vapordeposition，CVD)、原子层沉积(atomic layer deposition，ALD)、旋转涂布(spin coating)或前述的组合所形成。
根据一些实施例，如图1B所示，利用图案化光阻层107为遮罩，将第一氧化层105、第一氮化层103和一部分的半导体基底101图案化，以形成第一沟槽102和半导体基底图案P。一些实施例中，第一沟槽102穿过第一氧化层105、第一氮化层103和一部分的半导体基底101。一些实施例中，半导体基底图案P的高度h在约20nm至约250nm的范围内。一些实施例中，半导体基底图案P的高度h在约100nm至约200nm的范围内。半导体基底图案P的高度h即为后续制造工艺中形成的鳍状结构F(如图1J所示)的高度。
根据一些实施例，如图1C所示，在第一沟槽102的侧壁和底面上，以及第一氧化层105上毯覆性地形成第二氮化层109。换言之，第二氮化层109形成于半导体基底101的表面上、半导体基底图案P的侧壁上、第一氮化层103的侧壁上以及第一氧化层105的侧壁和顶面上。一些实施例中，第二氮化层109的材料为氮化硅。一些实施例中，第二氮化层109是通过化学气相沉积(CVD)、低压化学气相沉积(low-pressure CVD，LPCVD)、等离子体增强化学气相沉积(plasma enhanced CVD，PECVD)、原子层沉积(ALD)、旋转涂布、溅镀(sputter)或前述的组合所形成。
根据一些实施例，如图1D所示，通过异向性刻蚀(例如干式刻蚀)移除位于第一沟槽102的底部和第一氧化层105上的第二氮化层109，以形成第一间隙物109a。换言之，通过异向性刻蚀移除位于半导体基底101的表面上和第一氧化层105的顶面上的第二氮化层109，以在第一沟槽102的侧壁上形成第一间隙物109a。如图1D所示，第一间隙物109a位于半导体基底图案P的侧壁上、第一氮化层103的侧壁上和第一氧化层105的侧壁上，且接触部分的半导体基底101。值得注意的是，设置第一间隙物109a的目的为在后续制造工艺中定义出第二氧化层111a、111b、111c和111d(如图1G所示)的位置，此第二氧化层111a、111b、111c和111d相当于绝缘层上覆硅(SOI)基底中的埋置氧化层(buried oxide layer)。
根据一些实施例，如图1E所示，以第一间隙物109a为遮罩，实施刻蚀制造工艺，在半导体基底101内形成第二沟槽104。第二沟槽104形成于第一沟槽102的下方，且第二沟槽104的宽度和深度均较第一沟槽102小。一些实施例中，第二沟槽104由异向性刻蚀(例如干性刻蚀)形成。如图1E所示，在形成第二沟槽104之后，由于第二沟槽104的宽度小于第一沟槽102的宽度，半导体基底101具有阶梯状的剖面。
接续前述，如图1F所示，移除第一氧化层105以形成第三沟槽106。一些实施例中，通过图案化光阻层(未绘示)遮蔽鳍状结构以外的区域，实施刻蚀制造工艺以移除位于鳍状结构区域未被图案化光阻层遮蔽的第一氧化层105。由于图1F为沿着鳍状结构区域的剖面示意图，图中所显示的第一氧化层105皆被移除，并形成第三沟槽106。换言之，第三沟槽106的位置即为原本第一氧化层105的位置，因此，第三沟槽106的底面为第一氮化层103的顶面，且第三沟槽106的两侧为第一间隙物109a。
根据一些实施例，如图1G所示，形成多个第二氧化层111a、111b、111c和111d，各自位于每一个第二沟槽104内，并且这些第二氧化层111a、111b、111c和111d还侧向延伸至半导体基底101内，位于第一间隙物109a的下方和部分半导体基底图案P的下方。如图1G所示，这些第二氧化层111a、111b、111c和111d设置在半导体基底101内，且邻近半导体基底101的表面。一些实施例中，第二氧化层111a、111b、111c和111d是通过热氧化法(thermaloxidation)所形成。一些实施例中，第二氧化层111a、111b和111c彼此不相连，而第二氧化层111c和111d则通过连接部C相连。
值得注意的是，通过热氧化法形成的第二氧化层111a、111b、111c和111d的表面可能会不平整，且每一个单一第二氧化层111a、111b、111c和111d的形成速率和状态可能会不同，其中，连接部C为第二氧化层111c和111d在制造工艺过程中过度地侧向成长而连接在一起的部分。一些实施例中，可调控第二氧化层111a、111b、111c和111d的成长速率，使得第二氧化层111a、111b、111c和111d侧向成长超过第三沟槽104的距离约大于250nm。一些实施例中，第二氧化层111a、111b、111c和111d侧向成长超过第三沟槽104的距离约大于500nm，确保后续制造工艺中所产生的鳍状结构F(如图1J所示)能完全位于第二氧化层111a、111b、111c和111d的上方。
本发明的实施例的第二氧化层111a、111b、111c和111d的设置目的与绝缘层上覆硅(SOI)基底中的埋置绝缘层相同，差别在于第二氧化层111a、111b、111c和111d通过热氧化法形成，而以往埋置绝缘层通过氧离子注入形成，本发明的一些实施例可避免氧离子注入在绝缘层上覆硅基底的表面产生缺陷的问题。一些实施例中，通过热氧化法形成的第二氧化层111a、111b、111c和111d的表面不共平面。
根据一些实施例，如图1H所示，在第三沟槽106的底部和侧壁上、第一间隙物109a的顶部和侧壁上，以及第二氧化层111a、111b、111c和111d上毯覆性地形成第三氧化层113。换言之，第三氧化层113形成于第一氮化层103上、第一间隙物109a的顶部和侧壁上，以及第一沟槽102的部分底面上。一些实施例中，第三氧化层113的材料为氧化硅。
之后，根据一些实施例，如图1I所示，通过异向性刻蚀(例如干式刻蚀)移除位于第三沟槽106的底部、第一间隙物109a的顶部和第二氧化层111a、111b、111c和111d上的第三氧化层113，形成第二间隙物113a和113b。换言之，通过异向性刻蚀移除位于第一氮化层103上、第一间隙物109a的顶部和第一沟槽102的底面上的第三氧化层113，以在第三沟槽106的侧壁上形成第二间隙物113a，并且也在第一沟槽102内的第一间隙物109a的侧壁上形成第二间隙物113b。换言之，第二间隙物113a和113b分别位于第一间隙物109a的两侧，且分别位于第三沟槽106的侧壁上和第一沟槽102内的第一间隙物109a的侧壁上。一些实施例中，由于第二间隙物113a位在突出于半导体基底101表面的第一氮化层103和半导体基底图案P的上方，第二间隙物113a的高度小于第二间隙物113b的高度。
接续前述，如图1J所示，以第二间隙物113a为遮罩，刻蚀移除部分的第一氮化层103和部分的半导体基底图案P，以在第二氧化层111a、111b、111c和111d上形成多个鳍状结构F，其中每个第二氧化层111a、111b、111c和111d上有至少两个鳍状结构F。值得注意的是，这些鳍状结构F由异向性刻蚀(例如干式刻蚀)移除部分的半导体基底图案P直至暴露出第二氧化层111a、111b、111c和111d，以确保鳍状结构F彼此之间不相连。
根据一些实施例，如图1K所示，移除第一间隙物109a、第二间隙物113a和113b，以及第一氮化层103，以完整地露出鳍状结构F。如前所述，鳍状结构F的高度相当于图1B中半导体基底图案P的高度h。一些实施例中，鳍状结构F的高度H和宽度W皆在约20nm至约250nm的范围内。一些实施例中，鳍状结构F的高度H和宽度W皆在约100nm至约200nm的范围内。
一些实施例中，鳍状结构F由刻蚀半导体基底101的半导体基底图案P而形成，故鳍状结构F和半导体基底101为相同材料，且鳍状结构F的材料可为单晶硅，相较于以往通过沉积和退火形成的多晶硅鳍状结构，本发明的实施例所形成的单晶硅鳍状结构具有开关电流比较高的优势。另一方面，通过第二间隙物113a和113b的设置，刻蚀移除一部分的半导体基底图案P，以在第二氧化层111a、111b、111c和111d上形成尺寸精细的鳍状结构，可免除昂贵的制造工艺设备的使用，降低制造工艺成本。
根据一些实施例，如图1L所示，在鳍状结构F、半导体基底101和第二氧化层111a、111b、111c和111d上形成栅极介电层117，以及在栅极介电层117上形成栅极电极层119。一些实施例中，栅极介电层117使用热氧化制造工艺、化学气相沉积(CVD)制造工艺、流动式化学气相沉积(flowable CVD，FCVD)制造工艺、原子层沉积(ALD)制造工艺、低压化学气相沉积(low-pressure CVD，LPCVD)制造工艺、等离子体增强化学气相沉积(PECVD)制造工艺、其他合适的制造工艺或前述的组合形成，栅极电极层119使用化学气相沉积(CVD)制造工艺、原子层沉积(ALD)制造工艺、低压化学气相沉积(LPCVD)制造工艺、等离子体增强化学气相沉积(PECVD)制造工艺、其他合适的制造工艺或前述的组合形成。
一些实施例中，栅极介电层117可由氧化硅或高介电常数的介电材料制成，其中高介电常数的介电材料可由氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金(hafniumdioxide-alumina alloy)、铪硅氧化物、铪硅氮氧化物、铪钽氧化物、铪钛氧化物、铪锆氧化物、其他合适的高介电常数材料或前述的组合制成。一些实施例中，栅极电极层119包含金属或其他合适的导电材料，例如：钨、铜、镍、铝、硅化钨、多晶硅或前述的组合。一些实施例中，在栅极介电层117和栅极电极层119形成之后，在鳍状结构F的适当的区域形成N型或P型的掺杂区作为源/漏极(S/D)区，并形成源/漏极(S/D)区的金属接触(未绘示)，以完成半导体装置100a的鳍式场效晶体管。
图2是根据本发明的一些实施例，显示半导体装置100a的部份俯视图，其中图1L是显示沿图2线A-A’的剖面示意图。
根据一些实施例，如图2所示，鳍状结构F上具有栅极结构(包含栅极介电层117和栅极电极层119)环绕着鳍状结构F内的沟道区，使得栅极结构可自多端控制沟道区。此外，鳍状结构F在栅极结构的两端分别为源极区S和漏极区D。
上述实施例提供了半导体装置100a及其形成方法，半导体装置100a为使用绝缘层上覆硅基底的鳍式场效晶体管，为了使鳍式场效晶体管在栅极施加电压时能达到完全空乏(fully depletion)的状态，沟道的宽度或深度必须在约20nm至约250nm的范围内，但制造宽度或深度在250nm以下的鳍状结构的鳍式场效晶体管需要昂贵的制造工艺成本(例如使用价格较高的精密曝光设备)。另一方面，绝缘层上覆硅的基底虽然相较于块材基底具有许多优点，但由于绝缘层上覆硅的基底表面在形成埋置氧化层的氧离子注入制造工艺中，经过氧离子撞击容易产生缺陷，以及生成电荷累积的中性区，产生浮动基底效应(floatingbody effect)，使得鳍式场效晶体管的阈值电压(threshold voltage)容易变动，造成电路设计的困难。
为了解决上述问题，本发明的实施例利用第一间隙物的设置，在半导体基底内形成第二氧化层，以形成用于半导体装置的绝缘层上覆硅的基底，可避免因氧离子撞击而对半导体基底的表面造成损坏。再者，本发明的实施例通过第二间隙物的设置，刻蚀半导体基底的一部分以在第二氧化层上形成尺寸精细的鳍状结构，使得鳍式场效晶体管在栅极施加电压时容易达到完全空乏的状态。此外，由于鳍状结构的材料与半导体基底相同可为单晶硅，相较于以往通过沉积和退火形成的多晶硅鳍状结构，本发明的单晶硅鳍状结构具有开关电流比较高的优势。
以上概述数个实施例为特征，以便在本发明所属技术领域中具有通常知识者可以更理解本发明的观点。在发明所属技术领域中具有通常知识者应该理解他们能以本发明为基础，设计或修改其他制造工艺和结构以达到与在此介绍的实施例相同的目的及/或优势。在发明所属技术领域中具有通常知识者也应该理解到，此类等效的结构并无悖离本发明的精神与范围，且他们能在不违背本发明的精神和范围之下，做各式各样的改变、取代和替换。

Claims (8)

1.一种半导体装置的形成方法，其特征在于，所述形成方法包括：
形成一第一氮化层于一半导体基底上；
形成一第一氧化层于所述第一氮化层上；
形成一第一沟槽穿过所述第一氧化层、所述第一氮化层和一部份的所述半导体基底；
形成一第一间隙物于所述第一沟槽的侧壁上；
以所述第一间隙物为遮罩，在所述半导体基底内形成一第二沟槽；
移除所述第一氧化层以形成一第三沟槽；
形成一第二氧化层于所述第二沟槽内，所述第二氧化层侧向延伸至所述半导体基底内且位于所述第一间隙物的下方；
形成一第二间隙物于所述第三沟槽的侧壁上；以及
以所述第二间隙物为遮罩，刻蚀移除部分的所述第一氮化层和部分的所述半导体基底，形成一鳍状结构于所述第二氧化层上。
2.根据权利要求1所述的形成方法，其特征在于，所述形成方法更包括：
于刻蚀移除部分的所述第一氮化层和部分的所述半导体基底之后，移除所述第一间隙物、所述第二间隙物和所述第一氮化层，以暴露所述鳍状结构；
形成一栅极介电层于所述鳍状结构、所述半导体基底和所述第二氧化层上；以及
形成一栅极电极层于所述栅极介电层上。
3.根据权利要求1所述的形成方法，其特征在于，形成所述第一间隙物的步骤包括：
形成一第二氮化层于所述第一沟槽的底部和侧壁上，以及所述第一氧化层上；以及
通过异向性刻蚀移除位于所述第一沟槽的底部和所述第一氧化层上的所述第二氮化层。
4.根据权利要求1所述的形成方法，其特征在于，形成所述第二间隙物的步骤包括：
形成一第三氧化层于所述第三沟槽的底部和侧壁上、所述第一间隙物的顶部和侧壁上，以及所述第二氧化层上；以及
通过异向性刻蚀移除位于所述第三沟槽的底部、所述第一间隙物的顶部和所述第二氧化层上的所述第三氧化层。
5.根据权利要求4所述的形成方法，其特征在于，所述第二间隙物更形成在所述第一沟槽内的所述第一间隙物的侧壁上。
6.根据权利要求1所述的形成方法，其特征在于，所述第二氧化层由热氧化法形成，且所述第二氧化层与相邻的另一第二氧化层相连。
7.根据权利要求1所述的形成方法，其特征在于，刻蚀移除部分的所述半导体基底至暴露出所述第一氮化层下的所述第二氧化层。
8.根据权利要求1所述的形成方法，其特征在于，所述鳍状结构由刻蚀所述半导体基底形成，且所述鳍状结构的材料包括单晶硅。
CN201710076208.5A 2016-11-15 2017-02-13 半导体装置的形成方法 Active CN108074974B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW105137203 2016-11-15
TW105137203A TWI604569B (zh) 2016-11-15 2016-11-15 半導體裝置及其形成方法

Publications (2)

Publication Number Publication Date
CN108074974A CN108074974A (zh) 2018-05-25
CN108074974B true CN108074974B (zh) 2020-09-04

Family

ID=61023076

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710076208.5A Active CN108074974B (zh) 2016-11-15 2017-02-13 半导体装置的形成方法

Country Status (3)

Country Link
US (1) US9905480B1 (zh)
CN (1) CN108074974B (zh)
TW (1) TWI604569B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111200016B (zh) * 2018-11-16 2023-07-28 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
TWI707385B (zh) * 2019-10-15 2020-10-11 力晶積成電子製造股份有限公司 半導體結構的製造方法

Family Cites Families (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5235187A (en) * 1991-05-14 1993-08-10 Cornell Research Foundation Methods of fabricating integrated, aligned tunneling tip pairs
US7259425B2 (en) * 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US6770934B1 (en) * 2003-04-03 2004-08-03 Powerchip Semiconductor Corp. Flash memory device structure and manufacturing method thereof
KR100555518B1 (ko) * 2003-09-16 2006-03-03 삼성전자주식회사 이중 게이트 전계 효과 트랜지스터 및 그 제조방법
US6962843B2 (en) * 2003-11-05 2005-11-08 International Business Machines Corporation Method of fabricating a finfet
KR100513405B1 (ko) * 2003-12-16 2005-09-09 삼성전자주식회사 핀 트랜지스터의 형성 방법
KR100610496B1 (ko) * 2004-02-13 2006-08-09 삼성전자주식회사 채널용 핀 구조를 가지는 전계효과 트랜지스터 소자 및 그제조방법
KR100605104B1 (ko) * 2004-05-04 2006-07-26 삼성전자주식회사 핀-펫 소자 및 그 제조 방법
KR100618698B1 (ko) * 2004-06-21 2006-09-08 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
KR100645065B1 (ko) * 2005-06-23 2006-11-10 삼성전자주식회사 핀 전계 효과 트랜지스터와 이를 구비하는 비휘발성 메모리장치 및 그 형성 방법
US7928005B2 (en) * 2005-09-27 2011-04-19 Advanced Micro Devices, Inc. Method for forming narrow structures in a semiconductor device
US7638381B2 (en) * 2005-10-07 2009-12-29 International Business Machines Corporation Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby
KR100675290B1 (ko) * 2005-11-24 2007-01-29 삼성전자주식회사 다중채널 전계효과트랜지스터 및 핀 전계효과트랜지스터를갖는 반도체소자의 제조방법 및 관련된 소자
DE102006001680B3 (de) * 2006-01-12 2007-08-09 Infineon Technologies Ag Herstellungsverfahren für eine FinFET-Transistoranordnung und entsprechende FinFET-Transistoranordnung
US7612406B2 (en) * 2006-09-08 2009-11-03 Infineon Technologies Ag Transistor, memory cell array and method of manufacturing a transistor
US8236638B2 (en) * 2007-04-18 2012-08-07 Freescale Semiconductor, Inc. Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner
US8404592B2 (en) * 2009-07-27 2013-03-26 GlobalFoundries, Inc. Methods for fabricating FinFET semiconductor devices using L-shaped spacers
US8143121B2 (en) * 2009-10-01 2012-03-27 Nanya Technology Corp. DRAM cell with double-gate fin-FET, DRAM cell array and fabrication method thereof
US9117877B2 (en) * 2012-01-16 2015-08-25 Globalfoundries Inc. Methods of forming a dielectric cap layer on a metal gate structure
US8541286B2 (en) * 2012-02-17 2013-09-24 GlobalFoundries, Inc. Methods for fabricating integrated circuits
US8551843B1 (en) * 2012-05-07 2013-10-08 Globalfoundries Inc. Methods of forming CMOS semiconductor devices
KR20140008863A (ko) * 2012-07-12 2014-01-22 에스케이하이닉스 주식회사 더블 ｓｐｔ를 이용한 반도체 소자의 미세패턴 형성방법
CN103794499B (zh) * 2012-10-30 2017-08-25 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
US9082853B2 (en) * 2012-10-31 2015-07-14 International Business Machines Corporation Bulk finFET with punchthrough stopper region and method of fabrication
US8987823B2 (en) * 2012-11-07 2015-03-24 International Business Machines Corporation Method and structure for forming a localized SOI finFET
US8766363B2 (en) * 2012-11-07 2014-07-01 International Business Machines Corporation Method and structure for forming a localized SOI finFET
US8956942B2 (en) * 2012-12-21 2015-02-17 Stmicroelectronics, Inc. Method of forming a fully substrate-isolated FinFET transistor
US9318606B2 (en) * 2013-01-14 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of fabricating same
US8691640B1 (en) * 2013-01-21 2014-04-08 Globalfoundries Inc. Methods of forming dielectrically isolated fins for a FinFET semiconductor by performing an etching process wherein the etch rate is modified via inclusion of a dopant material
US8716156B1 (en) * 2013-02-01 2014-05-06 Globalfoundries Inc. Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process
US8877588B2 (en) * 2013-02-11 2014-11-04 Globalfoundries Inc. Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
US8835323B1 (en) * 2013-03-14 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US8975125B2 (en) * 2013-03-14 2015-03-10 International Business Machines Corporation Formation of bulk SiGe fin with dielectric isolation by anodization
US20140315371A1 (en) * 2013-04-17 2014-10-23 International Business Machines Corporation Methods of forming isolation regions for bulk finfet semiconductor devices
CN104167393B (zh) * 2013-05-17 2018-09-18 中国科学院微电子研究所 半导体器件制造方法
US9349730B2 (en) * 2013-07-18 2016-05-24 Globalfoundries Inc. Fin transformation process and isolation structures facilitating different Fin isolation schemes
US8987008B2 (en) * 2013-08-20 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layout and method with double patterning
US9093326B2 (en) * 2013-10-21 2015-07-28 International Business Machines Corporation Electrically isolated SiGe fin formation by local oxidation
US8975129B1 (en) * 2013-11-13 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US9117875B2 (en) * 2014-01-15 2015-08-25 Globalfoundries Inc. Methods of forming isolated germanium-containing fins for a FinFET semiconductor device
US9627245B2 (en) * 2014-03-05 2017-04-18 Globalfoundries Inc. Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device
US20150255555A1 (en) * 2014-03-05 2015-09-10 Globalfoundries Inc. Methods of forming a non-planar ultra-thin body device
US9147616B1 (en) * 2014-08-28 2015-09-29 Globalfoundries Inc. Methods of forming isolated fins for a FinFET semiconductor device with alternative channel materials
KR20160025866A (ko) * 2014-08-28 2016-03-09 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
US9337196B2 (en) * 2014-09-29 2016-05-10 International Business Machines Corporation III-V FinFET CMOS with III-V and germanium-containing channel closely spaced
US9293530B1 (en) * 2014-11-14 2016-03-22 International Business Machines Corporation High aspect ratio trapping semiconductor with uniform height and isolated from bulk substrate
US9595475B2 (en) * 2014-12-01 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stage fin formation methods and structures thereof
TWI629790B (zh) * 2015-01-26 2018-07-11 聯華電子股份有限公司 半導體元件及其製作方法
US9673083B2 (en) * 2015-01-29 2017-06-06 Globalfoundries Inc. Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material
US9349658B1 (en) * 2015-01-29 2016-05-24 Globalfoundries Inc. Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material
US9515089B1 (en) * 2015-05-14 2016-12-06 International Business Machines Corporation Bulk fin formation with vertical fin sidewall profile
US9590077B2 (en) * 2015-05-14 2017-03-07 International Business Machines Corporation Local SOI fins with multiple heights
CN106298921B (zh) * 2015-06-01 2019-07-02 中芯国际集成电路制造(上海)有限公司 半导体器件、鳍式场效应晶体管及其形成方法
US10269968B2 (en) * 2015-06-03 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9318392B1 (en) * 2015-06-18 2016-04-19 International Business Machines Corporation Method to form SOI fins on a bulk substrate with suspended anchoring
US9368569B1 (en) * 2015-09-21 2016-06-14 International Business Machines Corporation Punch through stopper for semiconductor device
US9397002B1 (en) * 2015-11-20 2016-07-19 International Business Machines Corporation Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide
US9466690B1 (en) * 2016-01-13 2016-10-11 International Business Machines Corporation Precisely controlling III-V height
US9601514B1 (en) * 2016-01-26 2017-03-21 International Business Machines Corporation Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
US9455314B1 (en) * 2016-02-05 2016-09-27 International Business Machines Corporation Y-FET with self-aligned punch-through-stop (PTS) doping
US9941302B2 (en) * 2016-04-20 2018-04-10 International Business Machines Corporation Structure and method to form defect free high-mobility semiconductor fins on insulator
US9793395B1 (en) * 2016-10-06 2017-10-17 International Business Machines Corporation Vertical vacuum channel transistor

Also Published As

Publication number Publication date
TWI604569B (zh) 2017-11-01
CN108074974A (zh) 2018-05-25
TW201820549A (zh) 2018-06-01
US9905480B1 (en) 2018-02-27

Similar Documents

Publication Publication Date Title
US11133387B2 (en) FinFETs having dielectric punch-through stoppers
US7381649B2 (en) Structure for a multiple-gate FET device and a method for its fabrication
JP4110085B2 (ja) 二重ゲート型電界効果トランジスタの製造方法
CN107958873B (zh) 鳍式场效应管及其形成方法
US10192746B1 (en) STI inner spacer to mitigate SDB loading
US9117907B2 (en) Semiconductor device
US9991343B2 (en) LDD-free semiconductor structure and manufacturing method of the same
CN112530943A (zh) 半导体器件及其制造方法
US10861951B2 (en) Transistor layout to reduce kink effect
JP5925740B2 (ja) トンネル電界効果トランジスタ
JP2009521126A (ja) フィールドプレートを具える半導体デバイス及びその製造方法
CN112825327A (zh) 半导体结构及其形成方法
CN103579004A (zh) FinFET及其制造方法
CN103390637B (zh) FinFET及其制造方法
CN107591436B (zh) 鳍式场效应管及其形成方法
CN108074974B (zh) 半导体装置的形成方法
CN104134698B (zh) FinFET及其制造方法
US20180294262A1 (en) Finfet device
JP2004207726A (ja) 二重ゲート型電界効果トランジスタおよびその製造方法
CN113838934A (zh) 半导体结构及其形成方法
KR20090046201A (ko) 수직형 트랜지스터 및 그의 형성방법
CN109273407B (zh) 半导体器件及其形成方法
CN116435367A (zh) 包含背栅结构的soi器件及其制备方法
KR100929630B1 (ko) 반도체 소자 및 그의 제조 방법
CN115714133A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant