CN107579121B - 肖特基势垒二极管及其制造方法 - Google Patents

肖特基势垒二极管及其制造方法 Download PDF

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CN107579121B
CN107579121B CN201611149881.9A CN201611149881A CN107579121B CN 107579121 B CN107579121 B CN 107579121B CN 201611149881 A CN201611149881 A CN 201611149881A CN 107579121 B CN107579121 B CN 107579121B
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CN107579121A (zh
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千大焕
郑永均
周洛龙
朴正熙
李钟锡
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Hyundai Motor Co
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Abstract

本公开提供了肖特基势垒二极管及其制造方法。根据本公开示范性实施方式的肖特基势垒二极管包括：设置在n+型碳化硅基底的第一表面上的n‑型层；设置在n‑型层上的p+型区域和p型区域，p+型区域和p型区域相互分离；设置在n‑型层、p+型区域和p型区域上的阳极；以及设置在n+型碳化硅基底的第二表面上的阴极，其中p型区域有多个，在平面上具有六角形形状，并且以矩阵形状设置，以及设置在p+型区域和p型区域之间的n‑型层在平面上具有六角形形状而且围绕p型区域。

Description

肖特基势垒二极管及其制造方法
相关申请交叉参考
本申请要求韩国专利申请第10-2016-0084839号优先权的权益，所述专利申请于2016年7月5日在韩国知识产权局提交，这里通过引用包含了其整个内容。
技术领域
本公开涉及一种包括碳化硅(SiC)的肖特基势垒二极管及其制造方法。
背景技术
肖特基势垒二极管使用肖特基结，其中不像普通的PN二极管那样使用PN结，而是金属和半导体结合在一起，肖特基势垒二极管显示了快速的开关特性，并且比PN二极管具有更低的开启电压。
在通常的肖特基势垒二极管中，为了改善泄露电流减小而应用结势垒肖特基(JBS)的结构，该结构中在肖特基结部分的下端形成了p+区域，从而通过当施加反向电压时扩散的PN二极管耗尽层的重叠获得阻塞泄露电流且提高击穿电压的效果。
形成具有不同离子掺杂浓度的p+型区域和p型区域以降低肖特基结区域的电场，使得当施加反向电压时可以减小泄露电流。
该背景技术部分公开的上述信息仅是用于加强对本发明背景技术的理解，因此，它可能包含未形成在该国家已被本领域的技术人员知晓的现有技术的信息。
发明内容
本公开增加了肖特基势垒二极管的电流密度。
根据本公开示范性实施例的肖特基势垒二极管包括设置在n+型碳化硅基底第一表面上的n-型层；设置在n-型层上且相互分离的p+型区域和p型区域；设置在n-型层、p+型区域和p型区域上的阳极；设置在n+型碳化硅基底第二表面上的阴极，其中p型区域有多个，在平面上具有六角形形状，并且布置为矩阵的形状，设置在p+型区域和p型区域之间的n-型层在平面上具有六角形形状并且围绕p型区域。
穿过p型区域中心点的水平线与平面的列方向上与其相互毗邻的p型区域的水平线不相遇。
p+型区域和p型区域可以分别接触n型层，并且其中p+型区域和n-型区域接触的区域可以比其中p型区域和n-型层接触的区域更宽。
p+型区域的离子掺杂浓度可以比p型区域的离子掺杂浓度更高。
阳极可以包括肖特基电极，阴极可以包括欧姆电极。
肖特基势垒二极管可以进一步包括位于阳极和n-型层之间的n型层，n型层的离子掺杂浓度可以比n-型层的离子掺杂浓度更高。
肖特基势垒二极管可以进一步包括设置在n型层上的且相互分离的第一沟槽(trench)和第二沟槽。
p+型区域可以设置在第一沟槽的下表面下方，p型区域可以设置在第二沟槽的底面下方。
阳极可以包括设置在第一沟槽和第二沟槽里面的第一阳极，和设置在第一阳极和n型层上的第二阳极。
根据本公开另一示范性实施例的肖特基势垒二极管的制造方法包括顺序地在n+型碳化硅基底第一表面处形成n-型层和n型层；在n型层处形成相互分离的第一沟槽和第二沟槽；将p型离子注入第一沟槽的下表面以形成p+型区域；将p型离子注入第二沟槽的下表面以形成p型区域；在n型层上、第一沟槽里面和第二沟槽里面形成阳极；以及在n+型碳化硅基底的第二表面上形成阴极，其中p型区域有多个，在平面上具有六角形形状，并且设置为矩阵的形状，设置在p+型区域和p型区域之间的n-型层在平面上具有六角形形状并且围绕p型区域。
如上所述，根据本公开的示范性实施例，通过形成比p型区域和n-型层的接触面更大的p+型区域和n-型层的接触面，当施加正向电压时可以增大肖特基势垒二极管的电流密度。
相应地，可以减小肖特恩势垒二极管的面积，从而提高每单位晶片上肖特基势垒二极管的数目以及其成品率。
附图说明
图1是示出根据本公开示范性实施方式的肖特基势垒二极管一个实例的布局。
图2是沿着图1的II-II线的剖视图。
图3是局部地示出根据本公开的示范性实施方式的肖特基势垒二极管的布局视图。
图4是局部地示出根据比较实例的肖特基势垒二极管的布局视图。
图5-图8是示出根据本公开的示范性实施方式的肖特基势垒二极管的制造方法的一个实例的视图。
具体实施方式
将参照附图对本公开的示范性实施方式进行详细描述。如本领域的技术人员将认识到的，可以通过多种不同的方式对所描述的实施方式进行修改，而不背离本公开的精神或范围。这里提供了所公开的示范性实施方式，从而所公开的内容可以变得更彻底和完整，并且本领域的普通技术人员可以充分地理解本公开的精神。
在附图中，为了清晰放大了层的厚度和区域。此外，当提到层出现在其它层或基底“上”时，可以直接在另一个层或基底上形成所述层，或者第三层可以插在它们之间。整个说明书中，相同的参考标号指定相同的构成元件。
图1是示出根据本公开的示范性实施方式的肖特基二极管的一个实例的布局。图2是沿着图1的II-II线的剖视图。
如图1和图2所示，根据示范性实施方式的肖特基势垒二极管包括n+型碳化硅基底100、n-型层200、n型层300、p+型区域400、p型区域500、阳极600、阴极700。
在图1的布局中，省略了n型层300和阳极600。参照图1，在平面上，p型区域500形成为具有六角形形状并且与p+型区域400相分离。n-型层200位于p型区域500和p+型区域400之间。位于p型区域500和p+型区域400之间的n-型层200形成为具有六角形形状。即，在平面上，六角形形状的n-型层200围绕具有六角形形状的p型区域500，p+型区域400设置在剩余的部分上。这里，位于p型区域500和p+型区域400之间的n-型层200和p型区域500可以在平面上具有正六边形形状。
p型区域500有多个且以矩阵形状设置。多个p型区域500在列方向上以Z字形形状放置，以便穿过p型区域500的中心点的水平线与穿过在平面的列方向上毗邻设置的p型区域500的中心点的水平线不相遇。
现在，将对根据本公开示范性实施方式的半导体设备的详细结构进行描述。
n-型层200和n型层300顺序地设置在n+型碳化硅基底100的第一表面上。n型层300的离子掺杂浓度可以高于n-型层200的离子掺杂浓度。
第一沟槽350和第二沟槽360形成于n型层300中，第一沟槽350和第二沟槽360相互毗邻且相互分离。第一沟槽350和第二沟槽360的深度可以相同。
p+型区域400设置在第一沟槽350的下表面下方，p型区域500设置在第二沟槽360的下表面下方。p+型区域400的离子掺杂浓度高于p型区域500的离子掺杂浓度。
P+型区域400围绕第一沟槽350下表面的拐角并且接触n-型层200。P型区域500围绕第二沟槽360下表面的拐角并且接触n-型层200。
阳极600设置在n型层300上、第一沟槽350里面和第二沟槽360里面。阳极600可以包括肖特基金属。阳极600包括位于第一沟槽350里面和第二沟槽360里面的第一阳极610以及位于第一阳极610和n型层300上的第二阳极620。第一阳极610接触p+型区域400和p型区域500。
阴极700设置在n+型碳化硅基底100的第二表面上。阴极700可以包括欧姆金属。这里，n+型碳化硅基底100的第二表面设置在与n+型碳化硅基底100的第一表面相对的一侧处。
由于p+型区域400的离子掺杂浓度高于p型区域500的离子掺杂浓度，当施加正向电压时，其中p+型区域400和n-型层200相连接的部分中的空穴电流密度高于其中p型区域500和n-型层200相连接的部分中的空穴电流密度。
如上所述，在平面上，具有六角形形状的n-型层200围绕具有六角形形状的p型区域500，p+型区域400设置在剩余的部分上，p+型区域400和p型区域500分别接触n-型层200。相应地，p+型区域400和n-型层200接触的区域宽于p型区域500和n-型层200接触的区域。
即，p+型区域400和n-型层200接触的区域被加宽以便增大肖特基势垒二极管的空穴电流密度，从而增大肖特基势垒二极管的整个电流密度。
由于肖特基势垒二极管电流密度的增大，可以减小肖特基势垒二极管的面积从而可以提高每单位晶片上肖特基势垒二极管的数目和成品率。
下面，将参照图3、图4和表1对根据本公开示范性实施方式的肖特基势垒二极管的特性进行描述。
如图3和图4所示，制备了根据本公开示范性实施方式的肖特基势垒二极管和根据比较例的肖特基势垒二极管。
图3是局部地示出根据本公开示范性实施方式的肖特基势垒二极管的布局视图。
图4是局部地示出根据比较例的肖特基势垒二极管的布局视图。
参照图3，如上所述，根据本公开示范性实施例的肖特基势垒二极管具有这样的结构，其中六角形形状的n-型层200围绕具有六角形形状的p型区域500，p+型区域400设置在平面上的剩余部分中。这里，可以形成三角形，所述三角形具有分别连接p型区域500的中心和具有六角形形状的p型区域500的两个相邻顶点的线以及连接两个相邻p型区域500的中心部分的作为一条边的线，该三角形被称为单胞(unit cell)。
参照图4，根据比较实例的肖特基势垒二极管具有这样的结构，其中p+型区域和p型区域形成为棒状，n-型层200设置在p+型区域和p型区域之间。在这种情况下，可以形成包括一个p型区域和一个p+型区域的四边形，该四边形被称为单胞。
在根据本公开示范性实施方式的肖特基势垒二极管的单胞中，可以确认的是p+型区域占据的面积广于p型区域占据的面积。在根据比较例的肖特基势垒二极管的单胞中，可以确认的是p+型区域占据的面积与p型区域占据的面积相同。
表1代表了当施加正向电压时，根据本公开示范性实施方式的肖特基势垒二极管和根据比较例的肖特基势垒二极管的仿真结果。
[表1]
Figure BDA0001178942930000081
参照表1，可以确认的是根据本示范性实施方式的肖特基势垒二极管的每单胞电子电流密度等于根据比较例的肖特基势垒二极管的每单胞电子电流密度，然而，与根据比较例的肖特基势垒二极管的每单胞空穴电流密度相比，根据本示范性实施方式的肖特基势垒二极管的每单胞空穴电流密度增大了大约25％。相应地，可以确认的是与根据比较例的肖特基势垒二极管的每单胞整体电流密度相比，根据本示范性实施方式的肖特基势垒二极管的每单胞整体电流密度增大了大约14％。
基于100A的相同电流量，可以确认的是与根据比较例的肖特基势垒二极管的面积相比，根据本示范性实施方式的肖特基势垒二极管的面积减小了大约13％。因此，与根据比较例的肖特基势垒二极管相比，每单位晶体上可以包括更大数目的根据本示范性实施方式的肖特基势垒二极管，从而降低了成本。
下面，将参照图5-图8对根据本公开示范性实施方式的半导体元件的制造方法进行描述。
图5-图8是示出根据本公开示范性实施方式的肖特基势垒二极管的制造方法的一个实例的视图。
参照图5，制备了n+型碳化硅基底100，n-型层200和n型层300顺序地形成在n+型碳化硅基底100的第一表面上。n型层300的离子掺杂浓度可以高于n-型层200的离子掺杂浓度。
这里，在n+型碳化硅基底100的第一表面处以外延生长形成了n-型层200，在n-型层200上以外延生长形成了n型层300。
在n+型碳化硅基底100的第一表面处以外延生长形成了n-型层200，在n-型层200的表面处通过注入n型离子可以形成n型层300。
参照图6，蚀刻n型层300以形成第一沟槽350和第二沟槽360。第一沟槽350与第二沟槽360毗邻且相互分离。第一沟槽350和第二沟槽360的深度可以相同。
参照图7，p+型离子被注入第一沟槽350的下表面以形成p+型区域400。p+型区域400形成在第一沟槽350下表面的下方，围绕第一沟槽350下表面的拐角，并且接触n-型层200。
参照图8，p型离子被注入第二沟槽360的下表面以形成p型区域500。p型区域500形成在第二沟槽360下表面的下方，围绕第二沟槽360下表面，并且接触n-型层200。这里，p型区域500的离子掺杂浓度低于p+型区域400的离子掺杂浓度。
接下来，如图1所示，在平面上，p型区域500具有六角形形状且与p+型区域400相分离，n-型层200位于p型区域500和p+型区域400之间。位于p型区域500和p+型区域400之间的n-型层200具有六角形形状。即，在平面上，六角形形状的n-型层200围绕六角形形状的p型区域500，p+型区域400位于剩余的部分上。
p型区域500为多个且以矩阵形状布置。多个p型区域500在列方向上以Z字形形状放置，以便穿过p型区域500的中心点的水平线与穿过在平面的列方向上相互毗邻设置的p型区域500的水平线不相遇。
参照图2，阳极600形成在n型层300上、第一沟槽350里面和第二沟槽360里面，阴极700形成在n+型碳化硅基底100的第二表面处。
这里，阳极600包括设置在第一沟槽350和第二沟槽360里面的第一阳极610和设置在第一阳极610和n型层300上的第二阳极620。第一阳极610接触p+型区域400和p型区域500。
阳极600可以包括肖特基金属，阴极700可以包括欧姆金属。
另一方面，在根据本示范性实施方式的半导体元件的制造方法中，在同时形成第一沟槽350和第二沟槽360之后形成p+型区域400和p型区域500，然而并不限于此，可以首先形成第一沟槽350，可以在第一沟槽350的下表面下方形成p+型区域400，然后可以形成第二沟槽360，并且可以在第二沟槽360的下表面下方形成p型区域500。
虽然联系当前认为的实际示范性实施方式对本发明进行了描述，但是应理解的是本发明不限于公开的实施方式，而是相反，意图涵盖包含在所附权利要求的精神和范围内的各种修改和等同设置方案。

Claims (16)

1.一种肖特基势垒二极管，包括：
n-型层，设置在n+型碳化硅基底的第一表面上；
p+型区域和p型区域，设置在所述n-型层上，所述p+型区域和所述p型区域相互分离；
阳极，设置在所述n-型层、所述p+型区域和所述p型区域上；以及
阴极，设置在所述n+型碳化硅基底的第二表面上，
其中，所述p型区域有多个，在平面上具有六角形形状，并且以矩阵形状布置，以及
所述n-型层，其设置在所述p+型区域和所述p型区域之间，在平面上具有六角形形状并且围绕所述p型区域。
2.根据权利要求1所述的肖特基势垒二极管，其中
水平线，其穿过所述p型区域的中心点，与平面上的列方向上与其毗邻的p型区域的水平线不相遇。
3.根据权利要求2所述的肖特基势垒二极管，其中
所述p+型区域和所述p型区域分别接触所述n-型层，以及
所述p+型区域与所述n-型层接触的区域宽于所述p型区域与所述n-型层接触的区域。
4.根据权利要求3所述的肖特基势垒二极管，其中
所述p+型区域的离子掺杂浓度高于所述p型区域的离子掺杂浓度。
5.根据权利要求4所述的肖特基势垒二极管，其中
所述阳极包括肖特基电极，以及
所述阴极包括欧姆电极。
6.根据权利要求5所述的肖特基势垒二极管，进一步包括
设置在所述阳极和所述n-型层之间的n型层，并且
所述n型层的离子掺杂浓度高于所述n-型层的离子掺杂浓度。
7.根据权利要求6所述的肖特基势垒二极管，进一步包括
设置在所述n型层上的第一沟槽和第二沟槽，所述第一沟槽和所述第二沟槽相互分离。
8.根据权利要求7所述的肖特基势垒二极管，其中
所述p+型区域设置在所述第一沟槽的底面下方，以及
所述p型区域设置在所述第二沟槽的底面下方。
9.根据权利要求8所述的肖特基势垒二极管，其中
所述阳极包括
第一阳极，设置在所述第一沟槽和所述第二沟槽里面，和
第二阳极，设置在所述第一阳极和所述n型层上。
10.一种制造肖特基势垒二极管的方法，包括：
在n+型碳化硅基底的第一表面处顺序地形成n-型层和n型层；
在所述n型层处形成相互分离的第一沟槽和第二沟槽；
将p+型离子注入所述第一沟槽的底面以形成p+型区域；
将p型离子注入所述第二沟槽的底面以形成p型区域；
在所述n型层上、所述第一沟槽里面和所述第二沟槽里面形成阳极；以及
在所述n+型碳化硅基底的第二表面处形成阴极，
其中所述p型区域有多个，在平面上具有六角形形状，并且以矩阵形状布置，并且
设置在所述p+型区域和所述p型区域之间的所述n-型层在平面上具有六角形形状，且围绕所述p型区域。
11.根据权利要求10所述的方法，其中
穿过所述p型区域中心点的水平线与平面上的列方向上与其毗邻的p型区域的水平线不相遇。
12.根据权利要求11所述的方法，其中
所述p+型区域和所述p型区域分别接触所述n-型层，以及
所述p+型区域与所述n-型层接触的区域宽于所述p型区域与所述n-型层接触的区域。
13.根据权利要求12所述的方法，其中
所述p+型区域的离子掺杂浓度高于所述p型区域的离子掺杂浓度。
14.根据权利要求13所述的方法，其中
所述n型层的离子掺杂浓度高于所述n-型层的离子掺杂浓度。
15.根据权利要求14所述的方法，其中
所述阳极包括肖特基电极，以及
所述阴极包括欧姆电极。
16.根据权利要求15所述的方法，其中所述阳极包括：
第一阳极，设置在所述第一沟槽和所述第二沟槽里面；以及
第二阳极，设置在所述第一阳极和所述n型层上。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227811B2 (en) * 2010-09-08 2012-07-24 Kabushiki Kaisha Toshiba Semiconductor rectifying device
CN103443907A (zh) * 2011-03-18 2013-12-11 克里公司 包括具有重叠掺杂区的肖特基二极管的半导体器件及其制造方法
CN103887346A (zh) * 2012-12-24 2014-06-25 比亚迪股份有限公司 一种肖特基二极管及其制造方法
CN104465793A (zh) * 2013-09-13 2015-03-25 现代自动车株式会社 肖特基势垒二极管和用于制造肖特基势垒二极管的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4764003B2 (ja) 2004-12-28 2011-08-31 日本インター株式会社 半導体装置
JP2008251925A (ja) 2007-03-30 2008-10-16 Sanyo Electric Co Ltd ダイオード
JP5377548B2 (ja) * 2011-03-03 2013-12-25 株式会社東芝 半導体整流装置
US8937319B2 (en) * 2011-03-07 2015-01-20 Shindengen Electric Manufacturing Co., Ltd. Schottky barrier diode
JP5926893B2 (ja) 2011-04-26 2016-05-25 株式会社 日立パワーデバイス 炭化珪素ダイオード
KR20130049916A (ko) 2011-11-07 2013-05-15 현대자동차주식회사 실리콘 카바이드 쇼트키 베리어 다이오드 및 이의 제조방법
KR101518905B1 (ko) 2013-12-30 2015-05-11 현대자동차 주식회사 쇼트키 배리어 다이오드 및 그 제조 방법
KR20150078454A (ko) 2013-12-30 2015-07-08 현대자동차주식회사 쇼트키 배리어 다이오드 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227811B2 (en) * 2010-09-08 2012-07-24 Kabushiki Kaisha Toshiba Semiconductor rectifying device
CN103443907A (zh) * 2011-03-18 2013-12-11 克里公司 包括具有重叠掺杂区的肖特基二极管的半导体器件及其制造方法
CN103887346A (zh) * 2012-12-24 2014-06-25 比亚迪股份有限公司 一种肖特基二极管及其制造方法
CN104465793A (zh) * 2013-09-13 2015-03-25 现代自动车株式会社 肖特基势垒二极管和用于制造肖特基势垒二极管的方法

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US20180013014A1 (en) 2018-01-11
KR101846879B1 (ko) 2018-04-09
US10930797B2 (en) 2021-02-23

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