CN112310228A - 肖特基势垒二极管 - Google Patents

肖特基势垒二极管 Download PDF

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CN112310228A
CN112310228A CN202010730192.7A CN202010730192A CN112310228A CN 112310228 A CN112310228 A CN 112310228A CN 202010730192 A CN202010730192 A CN 202010730192A CN 112310228 A CN112310228 A CN 112310228A
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barrier diode
semiconductor region
schottky barrier
semiconductor
metal layer
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崔基埈
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LX Semicon Co Ltd
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Silicon Works Co Ltd
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Abstract

公开了一种可以应用于诸如移动集成电路的需要低截止电流(Ioff)的应用的肖特基势垒二极管。肖特基势垒二极管能够通过改善由耗尽而夹断的接触表面的结构，从而在保持导通电流的优势的同时，改善对于反向电流的阻断特性。

Description

肖特基势垒二极管
技术领域
本公开涉及一种肖特基势垒二极管，并且更特别地，涉及一种可以应用于诸如移动集成电路的需要低截止电流(Ioff)的应用的肖特基势垒二极管。
背景技术
肖特基势垒二极管是使用由势垒金属与半导体之间的接触产生的势垒作为整流作用的器件。肖特基势垒二极管用于高速切换或高频转换、高频检测等。
当正向电流流入肖特基势垒二极管时，借助于外延半导体层的移动到势垒金属的多个载流子来导通肖特基势垒二极管。在这种情况下，电压-电流特性取决于肖特基特性。
此外，如果反向电流要流入肖特基势垒二极管，则通过势垒金属与半导体之间的势垒来断开肖特基势垒二极管。通过由P阱区域耗尽为N阱区域时形成的结势垒来断开肖特基势垒二极管。
为了将肖特基势垒二极管应用于需要快速断开和低截止电流(Ioff)的应用，肖特基势垒二极管需要一种结构，以能够在保持导通电流(Ion)不变的优势的同时改善截止电流(Ioff)。
发明内容
各种实施例旨在提供在保持导通电流(Ion)的优势的同时具有改善的截止电流特性的肖特基势垒二极管。
此外，各种实施例旨在通过形成其中由耗尽形成的结势垒的半导体区域而提供具有改善的截止电流特性的肖特基势垒二极管，使得在垂直彼此的第一方向和第二方向上的宽度具有相同的长度。
在实施例中，肖特基势垒二极管包括势垒金属层和配置为与势垒金属层形成肖特基接触的半导体衬底。半导体衬底包括：第一半导体区域，配置成形成与势垒金属层接触的第一接触表面；以及第二半导体区域，分别分布在第一接触表面内的多个位置处，并配置为形成与势垒金属层接触的各个第二接触表面。对于从半导体衬底到势垒金属层的反向电流流动，第一半导体区域具有绝缘特性。每个第二接触表面形成为具有在彼此垂直的第一方向和第二方向上具有相同长度的宽度。通过反向电流流动，第一半导体区域耗尽到第二半导体区域中，以阻断反向电流流动穿过第二半导体区域。
附图说明
图1是根据实施例的肖特基势垒二极管的平面图。
图2是沿图1中的线2-2截取的用于描述正向电流流动的局部截面图。
图3是沿图1中的线2-2截取的用于描述反向电流流动的局部截面图。
图4是根据另一实施例的肖特基势垒二极管的平面图。
具体实施方式
以下将参照附图详细描述示例性实施例。然而，本公开可以以不同的形式实施并且不应被构造为限于本文阐述的实施例。相反，提供这些实施例使得本公开将是透彻和完整的，并将向本领域技术人员充分地传达本公开的范围。在整个本公开中，贯穿本公开的各种附图和实施例，相同的附图标记指代相同的部分。
以下将参照图1至图3描述根据实施例的肖特基势垒二极管。
图1是根据实施例的肖特基势垒二极管的平面布局，并且示出了尚未形成势垒金属层BM和阳电极AN的状态。此外，图2和图3是沿图1中的线2-2截取的局部截面图。肖特基势垒二极管包括半导体衬底SM、势垒金属层BM和在半导体衬底SM一侧上的阳电极AN，以及在半导体衬底SM另一侧上的阴电极CA。
阳电极AN、阴电极CA和势垒金属层BM包括导电材料，并且可以形成为具有制造商设计的厚度。在这些元件中，势垒金属层BM可以形成为包括金属材料，诸如钛(Ti)或Ti合金、硅化物或硅化钴。
势垒金属层BM通过保护环10将与之接触的接触区域限定在半导体衬底SM中。接触区域可以理解为保护环10的内部区域。
例如，图1示出了保护环10形成为四边形。沿保护环10在保护环10内形成隔离区域20。保护环10和隔离区域20可以理解为形成在半导体衬底SM的一侧并填充有绝缘物质的沟槽。在元件当中，保护环10可以理解为形成为用于保护环10的内部区域和外部区域之间的电分离。隔离区域20可以理解为辅助地形成为用于隔离。
如图2和图3所示，势垒金属层BM形成在由保护环10限定的接触区域上方。阳电极AN形成在势垒金属层BM上方。
此外，参照图1，第一接触表面30和第二接触表面40形成在保护环10的接触区域内。
第一接触表面30形成在保护环10内的矩形中。第二接触表面40分布在第一接触表面30内的多个位置处。每个第二接触表面40的宽度在彼此垂直的第一方向(例如，图1中的X)和第二方向(例如，图1中的Y)上具有相同长度。例如，每个第二接触表面被示为圆形。
参照图2和图3，第一接触表面30可以理解为由保护环10的内部区域的第一半导体区域形成的上表面。第二接触表面40可以理解为由保护环10的内部区域的第二半导体区域形成的上表面。
第一半导体区域可以使用P型半导体形成。例如，第一半导体区域可以由P阱130形成。第二半导体区域可以使用N型半导体形成。例如，第二半导体区域可以由N阱140形成。在下文中，第一半导体区域被称为P阱130，以及第二半导体区域被称为N阱140。
P阱130形成为具有第一深度。N阱140形成为具有等于或大于第一深度的深度。图2和图3示出了N阱140形成为下部阱，以及P阱130形成为上部阱。
参照图2和图3描述半导体衬底SM的结构。
半导体衬底SM包括子层100和外延层110。例如，子层100可以使用N+型半导体形成。例如，外延层110可以使用N-型半导体形成。外延层110形成在子层100上。阴电极CA形成在子层100下，即，在半导体衬底SM的另一侧。
N阱140形成在外延层110中作为下部阱。P阱130形成在N阱140上作为上部阱。在这种情况下，N阱140可以形成为高压N阱。可以通过考虑外延层110和子层100来确定杂质的量。
由N阱140形成的第二接触表面40彼此间隔开，并且形成为在第一接触表面30内包括多个列。此外，第二接触表面40的相邻列设置为交错。因此，第二接触表面40可以均匀地分布在第一接触表面30中。
由于如上所述地实现了根据实施例的肖特基势垒二极管，所以如图2所示能够确保正向电流流动，并且如图3所示能够有效地阻断反向电流流动。
更具体地，对于从势垒金属层BM到半导体衬底SM的正向电流流动，形成第一接触表面30的P阱130和形成第二接触表面40的N阱140根据肖特基接触具有肖特基特性。结果是，如图2所示，确保了正向电流流动，即导通电流(Ion)的流动。
对于从半导体衬底SM到势垒金属层BM的反向电流流动，P阱130具有绝缘特性。
此外，P阱130通过反向电流流动形成延伸到N阱140的区域(即第二接触表面40)的耗尽区域DP。P阱130的耗尽区域DP通过反向电流而逐渐生长。结果是，由N阱140形成的第二接触表面40被耗尽区域DP夹断。耗尽区域DP形成结势垒。结果是，流过第二接触表面40的反向电流被阻断。即，截止电流(Ioff)即反向电流被阻断。
根据实施例的每个第二接触表面40形成为圆形。因此，通过P阱130的生长，耗尽区域DP能够在第二接触表面40的所有侧面上均匀地生长。通过耗尽区域DP的生长，第二接触表面40能够被有效地夹断。
因此，由于其中形成有耗尽区域的每个第二接触表面40形成的圆形在彼此垂直的第一方向和第二方向上具有相同长度的宽度，所以图1至图3的实施例能够改善形成夹断的特性。结果是，肖特基势垒二极管能够在保持导通电流的优势的同时改善对于反向电流流动的阻断特性，并且能够具有改善的截止电流特性。
根据如图4中的实施例，每个第二接触表面45可以形成为正方形。除了第二接触表面45的形状以外，图4的实施例以与图3的实施例相同的方式来配置，并因此省略冗余描述。
每个第二接触表面45形成为正方形，即附图中的一种，每个第二接触表面45在彼此垂直的第一方向和第二方向上具有相同长度的宽度。
因此，通过反向电流流动，P阱130的耗尽区域DP在四个表面中以均匀的速度生长。结果是，由N阱140形成的第二接触表面45能够由耗尽区域DP有效地夹断。流过第二接触表面45的反向电流能够被有效地阻断。
即，由于其中形成有耗尽区域的每个第二接触表面45形成的正方形在彼此垂直的第一方向和第二方向上具有相同长度的宽度(即附图中的一个示例)，所以图4的实施例能够改善形成夹断的特性。结果是，肖特基势垒二极管能够在保持导通电流的优势的同时改善对于反向电流流动的阻断特性，并且能够具有改善的截止电流特性。
除了图1所示的圆形和图4中所示的正方形之外，在常规多边形之中，每个第二接触表面45中可以配置为具有在彼此垂直的第一方向和第二方向上具有相同长度的宽度的正八边形。
即，根据实施例的肖特基势垒二极管能够应用于诸如移动集成电路的需要快速断开和低截止电流(Ioff)的应用。
本公开能够通过改进其中形成有耗尽区域的半导体区域，从而在保持导通电流的优势的同时改善对于反向电流流动的阻挡特性。
此外，本公开的优势在于，由于通过耗尽形成结势垒的每个半导体区域在彼此垂直的第一方向和第二方向上具有相同长度的宽度，所以具有改善的截止电流特性。
虽然以上已经描述了各种实施例，但是本领域技术人员将理解，所描述的实施例仅是示例性的。因此，不应基于所描述的实施例来限制本文所描述的公开。

Claims (8)

1.肖特基势垒二极管，包括：
势垒金属层；以及
半导体衬底，配置为与所述势垒金属层形成肖特基接触，
其中，所述半导体衬底包括：
第一半导体区域，配置为形成与所述势垒金属层接触的第一接触表面；以及
第二半导体区域，分别分布在所述第一接触表面内的多个位置处，并配置为形成与所述势垒金属层接触的各个第二接触表面，
对于从所述半导体衬底到所述势垒金属层的反向电流流动，所述第一半导体区域具有绝缘特性；
每个所述第二接触表面形成为具有在彼此垂直的第一方向和第二方向上具有相同长度的宽度；以及
通过所述反向电流流动，所述第一半导体区域耗尽到所述第二半导体区域中，以阻挡所述反向电流流动穿过所述第二半导体区域。
2.根据权利要求1所述的肖特基势垒二极管，其中：
阳电极形成在所述势垒金属层上，以及
所述第一半导体区域和所述第二半导体区域对于从所述势垒金属层到所述半导体衬底的正向电流流动具有肖特基特性。
3.根据权利要求1所述的肖特基势垒二极管，其中：
使用P型半导体形成所述第一半导体区域，以及
使用N型半导体形成所述第二半导体区域。
4.根据权利要求1所述的肖特基势垒二极管，其中：
所述第一半导体区域由具有第一深度的P阱形成，以及
所述第二半导体区域由深度等于或大于所述第一深度的N阱形成。
5.根据权利要求4所述的肖特基势垒二极管，其中，所述N阱形成为高压N阱。
6.根据权利要求1所述的肖特基势垒二极管，其中，每个所述第二接触表面形成为圆形。
7.根据权利要求1所述的肖特基势垒二极管，其中，每个所述第二接触表面形成为正方形。
8.根据权利要求1所述的肖特基势垒二极管，其中：
所述第二接触表面形成为在所述第一接触表面内具有多个列，以及
所述第二接触表面的相邻列设置为交错。
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