CN107230690A - 显示装置及显示装置的制造方法 - Google Patents
显示装置及显示装置的制造方法 Download PDFInfo
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- CN107230690A CN107230690A CN201710069669.XA CN201710069669A CN107230690A CN 107230690 A CN107230690 A CN 107230690A CN 201710069669 A CN201710069669 A CN 201710069669A CN 107230690 A CN107230690 A CN 107230690A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 65
- 239000010408 film Substances 0.000 claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 32
- 230000004888 barrier function Effects 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 101100489584 Solanum lycopersicum TFT1 gene Proteins 0.000 abstract description 24
- 101100214488 Solanum lycopersicum TFT2 gene Proteins 0.000 description 22
- 239000000758 substrate Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000003086 colorant Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000002096 quantum dot Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005424 photoluminescence Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
本发明提供一种显示装置及显示装置的制造方法,其目的在于减小薄膜晶体管的电流偏差,提高驱动能力。设于周边区域(PR)的多个薄膜晶体管为交错型的第一薄膜晶体管(TFT1),其具有由低温多晶硅构成的第一沟道层(CH1),且在第一源电极(SE1)及第一漏电极(DE1)各自与第一栅电极(GE1)之间不存在第一沟道层。设于显示区域(DR)的多个薄膜晶体管包括交错型的第二薄膜晶体管(TFT2),其具有由氧化物半导体构成的第二沟道层(CH2),且在第二源电极(SE2)及第二漏电极(DE2)各自与第二栅电极(GE2)之间不存在第二沟道层。第一薄膜晶体管与第二薄膜晶体管相比位于更下层的位置。
Description
技术领域
本发明涉及一种显示装置及显示装置的制造方法。
背景技术
显示装置通过与每个像素对应的亮度和色度的发光来显示图像。例如,向设在配置成矩阵状的多个像素电极与这些像素电极所共用的共用电极之间的有机发光层流通电流使其发光。另外,针对各个像素布局有组合了多个薄膜晶体管、电容器的像素电路。
现有技术文献
专利文献1:日本特开2012-160679号公报
因为由低温多晶硅构成的薄膜晶体管的驱动能力高,所以被大量使用。硅通过受激准分子激光退火而被多结晶化,但激光的照射偏差很大,从而无法减小各像素的电流偏差。因此,需要设置修正电路、或者多次反复照射激光,从而存在装置成本、激光的材料成本等的课题。
近年来,作为薄膜晶体管工艺,开发出使用了氧化物半导体的制造工艺(专利文献1)。然而,使用了氧化物半导体的现有薄膜晶体管无法满足窄框、低耗电量等的制约条件。于是,期待开发出用于混载基于氧化物半导体的薄膜晶体管和基于低温多晶硅的薄膜晶体管的工艺。
发明内容
本发明的目的在于,减小薄膜晶体管的电流偏差,提高驱动能力。
本发明的显示装置的特征在于,具有:多个像素电极,其设于用于显示图像的显示区域;共用电极,其配置在所述多个像素电极的上方;发光元件层,其夹设在所述多个像素电极与所述共用电极之间;以及由多个层构成的电路层,所述多个层从所述显示区域到达位于所述显示区域的外侧的周边区域,所述电路层在所述显示区域及所述周边区域分别具有多个薄膜晶体管,设于所述周边区域的所述多个薄膜晶体管为交错型的第一薄膜晶体管,该第一薄膜晶体管具有由低温多晶硅构成的第一沟道层,且在第一源电极与第一栅电极之间及第一漏电极与第一栅电极之间不存在所述第一沟道层,设于所述显示区域的所述多个薄膜晶体管包括交错型的第二薄膜晶体管,该第二薄膜晶体管具有由氧化物半导体构成的第二沟道层,且在第二源电极与第二栅电极之间及第二漏电极与第二栅电极之间不存在所述第二沟道层,所述第二薄膜晶体管与所述第一薄膜晶体管相比位于更上层的位置。
根据本发明,第一薄膜晶体管及第二薄膜晶体管为交错型,因此寄生电容变小,驱动能力很高。另外,由于第二薄膜晶体管的第二沟道层由氧化物半导体构成,所以能够减小电流偏差。而且,第一薄膜晶体管与第二薄膜晶体管相比位于更下层的位置。因此,由于第二薄膜晶体管在第一薄膜晶体管之后形成,所以不会受到在形成由低温多晶硅构成的第一沟道层时的热量。
本发明的显示装置的制造方法中,显示装置具有用于显示图像的显示区域及位于所述显示区域的外侧的周边区域,该显示装置的制造方法的的特征在于,包括:在所述周边区域形成交错型的第一薄膜晶体管的工序,所述第一薄膜晶体管具有由低温多晶硅构成的第一沟道层,且在第一源电极与第一栅电极之间及第一漏电极与第一栅电极之间不存在所述第一沟道层;在形成所述第一薄膜晶体管之后,在所述显示区域形成交错型的第二薄膜晶体管的工序,该第二薄膜晶体管具有由氧化物半导体构成的第二沟道层,且在第二源电极与第二栅电极之间及第二漏电极与第二栅电极之间不存在所述第二沟道层;在形成所述第二薄膜晶体管之后,在所述显示区域形成多个像素电极的工序;在所述多个像素电极的上方形成发光元件层的工序;以及在所述发光元件层的上方形成共用电极。
根据本发明,第一薄膜晶体管及第二薄膜晶体管为交错型,因此寄生电容变小,驱动能力很高。另外,由于第二薄膜晶体管的第二沟道层由氧化物半导体构成,所以能够减小电流偏差。而且,由于第二薄膜晶体管在第一薄膜晶体管之后形成,所以不会受到在形成由低温多晶硅构成的第一沟道层时的热量。
附图说明
图1是本发明的第一实施方式的显示装置的立体图。
图2是图1示出的显示装置的II-II线剖视图。
图3是本发明的第一实施方式的显示装置的电路图。
图4是示出第一实施方式的电路层的详细的概略图。
图5是示出第一实施方式的变形例的图。
图6是本发明的第二实施方式的显示装置的电路图。
图7是示出第二实施方式的电路层的详细的概略图。
附图标记说明
10 第一基板、12 集成电路芯片、14 柔性印刷基板、16 电路层、18 像素电极、20绝缘层、22 发光元件层、24 共用电极、26 封固层、28 填充层、30 第二基板、32 着色层、34黑矩阵、36屏蔽膜、116 电路层、140 金属层、142 贯穿孔、216 电路层、C 电容器、C1 第一电容器、C2 第二电容器、C3 第三电容器、CH1 第一沟道层、CH1 第一沟道层、CH2 第二沟道层、CL1 第一导电层、CL2 第二导电层、CP1 第一接触插塞、CP2 第二接触插塞、DE 显示元件、DE1 第一漏电极、DE2 第二漏电极、DR 显示区域、E1电极、E2 电极、E3 电极、GE1 第一栅电极、GE2 第二栅电极、PR 周边区域、PWL 电源线、SCL 扫描线、SE1 第一源电极、SE2第二源电极、SGL 信号线、SW1 第一开关元件、SW2 第二开关元件、SW3 第三开关元件、TFT1第一薄膜晶体管、TFT2 第二薄膜晶体管。
具体实施方式
以下,参照附图说明本发明的实施方式。
第一实施方式
图1是本发明的第一实施方式的显示装置的立体图。作为显示装置而举出有机电致发光显示装置为例子。显示装置对例如由红、绿及蓝构成的多个颜色的单位像素(子像素)进行组合,形成全彩的像素(pixel),显示全彩的图像。显示装置通过例如由树脂构成而包括具有柔性的第一基板10。在第一基板10上搭载有用于驱动用于显示图像的元件的集成电路芯片12,并连接有用于与外部电连接的柔性印刷基板14。
图2是图1示出的显示装置的II-II线剖视图。在第一基板10上层叠有电路层16。在后面具体说明电路层16。在电路层16之上设置有以与多个单位像素分别对应的方式构成的多个像素电极18(例如阳极)。在电路层16及像素电极18上形成有绝缘层20。绝缘层20以载置在像素电极18的周缘部并使像素电极18的一部分(例如中央部)开口的方式形成。通过绝缘层20形成了包围像素电极18的一部分的凸块(bank)。
在像素电极18上设有发光元件层22。发光元件层22连续地载置在多个像素电极18上,也载置在绝缘层20上。作为变形例,也可以针对每个像素电极18分别(分离地)设置发光元件层22。发光元件层22至少包括发光层,而且可以包括电子输送层、空穴输送层、电子注入层及空穴注入层中的至少一层。
在发光元件层22之上,以在多个像素电极18的上方与发光元件层22接触的方式设有共用电极24(例如阴极)。共用电极24以载置在成为凸块的绝缘层20的上方的方式形成。发光元件层22夹设在像素电极18及共用电极24之间,通过流过两者之间的电流被控制亮度从而发光。发光元件层22通过由层叠于共用电极24的封固层26覆盖而被封固,从而隔绝了水分。在封固膜26的上方隔着填充层28设有第二基板30。在第二基板30上设有由多个颜色(例如,蓝、红及绿)构成的着色层32,在相邻的不同颜色的着色层32之间由金属或树脂等形成有黑矩阵34,构成了彩色滤光片。第二基板30可以是触摸面板,也可以具有偏振片、相位差板。
图3是本发明的第一实施方式的显示装置的电路图。显示装置具有用于显示图像的显示区域DR。在显示区域DR针对每个像素设置有显示元件DE。显示元件DE由图2示出的像素电极18及共用电极24以及夹设在它们之间的发光元件层22构成。显示元件DE利用从电源线PWL供给的电流来发光。发光根据向电容器C写入的影像信号来调整亮度。影像信号从信号线SGL供给,由第一开关元件SW1写入。第一开关元件SW1的控制通过从扫描线SCL输入的扫描信号来实现。第二开关元件SW2按照向电容器C写入的影像信号来控制从显示元件DE流过的电流。在显示区域DR的周围具有周边区域PR。在周边区域PR设置有生成扫描信号、影像信号等的驱动电路。
图4是示出第一实施方式的电路层16的详细的概略图。电路层16从显示区域DR到达位于显示区域DR的外侧的周边区域PR。在第一基板10上形成有针对其自身所含有的杂质的屏蔽膜36。
电路层16在周边区域PR包括多个薄膜晶体管。设置于周边区域PR的多个薄膜晶体管为具有由低温多晶硅构成的第一沟道层CH1的第一薄膜晶体管TFT1。在图3示出的周边区域PR形成的驱动电路包括第一薄膜晶体管TFT1。第一薄膜晶体管TFT1为交错(stagger)型。因此,由于在第一源电极SE1与第一栅电极GE1之间及第一漏电极DE1与第一栅电极GE1之间不存在第一沟道层CH1,所以寄生电容变得很小,驱动能力很高。第一沟道层CH1具有从与第一栅电极GE1的重叠部分溢出的部分,该部分因离子的注入从而电阻值变低。设置有第一接触插塞CP1,第一接触插塞CP1将电路层16的第一薄膜晶体管TFT1上方的绝缘层(多个层)贯穿,且与第一沟道层CH1(从与第一栅电极GE1的重叠部分溢出的部分)连接。
在显示区域DR设置有多个像素电极18。参照图2,如上所述,在像素电极18载置有绝缘层20。在图4中,省略了设在像素电极18之上的其他构件。电路层16在显示区域DR包括多个薄膜晶体管。设于显示区域DR的多个薄膜晶体管包括具有由氧化物半导体构成的第二沟道层CH2的第二薄膜晶体管TFT2。第二薄膜晶体管TFT2的第二沟道层CH2由于由氧化物半导体构成,所以能够减小电流偏差。另外,第二薄膜晶体管TFT2为交错型。因此,由于第二源电极SE2与第二栅电极GE2之间及第二漏电极DE2与第二栅电极GE2之间不存在第二沟道层CH2,所以寄生电容变小,驱动能力很高。第二沟道层CH2具有从与第二栅电极GE2的重叠部分溢出的部分,该部分因离子的注入从而电阻值变低。
第二薄膜晶体管TFT2与第一薄膜晶体管TFT1相比位于更上层的位置。因此,由于第二薄膜晶体管TFT2在第一薄膜晶体管TFT1之后形成,所以不会受到在形成由低温多晶硅构成的第一沟道层CH1时的热量的影响。
图3示出的第一开关元件SW1及第二开关元件SW2分别为图4示出的第二薄膜晶体管TFT2。成为第二开关元件SW2的第二薄膜晶体管TFT2以能够控制向多个像素电极18的每一个供给的电流的供给量的方式被连接。设置有第二接触插塞CP2,该第二接触插塞CP2将电路层16的第二薄膜晶体管TFT2上方的绝缘层贯穿,且与第二沟道层CH2(从与第二栅电极GE2的重叠部分溢出的部分)连接。
构成电路层16的多个层中在显示区域DR包括向低温多晶硅的层注入离子而形成的第一导电层CL1。第一导电层CL1位于与第一薄膜晶体管TFT1的第一沟道层CH1同一层,且与第二薄膜晶体管TFT2相比位于更下方的层。通过将第一导电层CL1设有与第二薄膜晶体管TFT2的整体重叠的大小,能够保护第二薄膜晶体管TFT2不受热量或静电影响。此外,在图4的例子中,以使第二接触插塞CP2从第二沟道层CH2的端部露出,而且到达第一导电层CL1的方式设置该第二接触插塞CP2。
构成电路层16的多个层中在显示区域DR还包括第二导电层CL2,将第一导电层CL1作为电容器C的一个电极,该第二导电层CL2在与第一导电层CL1相对的位置成为电容器C的另一个电极。第二导电层CL2位于与第一薄膜晶体管TFT1的第一栅电极GE1同一层,且与第二薄膜晶体管TFT2相比位于更下方的层。电容器C被设为与第二薄膜晶体管TFT2重叠,因此不要求平面上的空间。
在本实施方式的显示装置的制造方法中,在周边区域PR形成上述的第一薄膜晶体管TFT1。在该工序中,同时在显示区域DR通过形成低温多晶硅的层并注入离子来形成第一导电层CL1。第一导电层CL1可以形成为具有与第二薄膜晶体管TFT2的整体重叠的大小。另外,在该工序中,与第一栅电极GE1的形成同时地,还形成成为用于与第一导电层CL1一起构成电容器C的电极的第二导电层CL2。在形成第一薄膜晶体管TFT1之后,在显示区域DR形成上述第二薄膜晶体管TFT2。由于第二薄膜晶体管TFT2在第一薄膜晶体管TFT1之后形成,所以不会受到在形成由低温多晶硅构成的第一沟道层CH1时的热量的影响。在形成第二薄膜晶体管TFT2之后,在显示区域DR形成多个像素电极18。然后,如图2所示,在多个像素电极18上形成发光元件层22,在发光元件层22上形成共用电极24。
变形例
图5是示出第一实施方式的变形例的图。在该变形例中,设于显示区域DR的多个薄膜晶体管在周边区域PR的第一薄膜晶体管TFT1同一层的位置包括第一薄膜晶体管TFT1。也就是说,图3示出的第一开关元件SW1为第一薄膜晶体管TFT1。设有第一接触插塞CP1,该第一接触插塞CP1将电路层116的第一薄膜晶体管TFT1之上的绝缘层贯穿,且与第一沟道层CH1连接。。
构成电路层116的多个层包括金属层140,该金属层140以与第一薄膜晶体管TFT1的第一沟道层CH1的至少端部重叠的方式,在与第二薄膜晶体管TFT2的第二栅电极GE2同一层的位置由与第二栅电极GE2相同的材料构成。金属层140以与第一接触插塞CP1成为一体的方式形成。
如上所述,第二沟道层CH2具有从与第二栅电极GE2重叠的部分溢出的部分。该部分通过以第二栅电极GE2作为掩膜注入离子来降低电阻值。通过设置金属层140,能够防止因离子注入的工艺导致第一薄膜晶体管TFT1的特性下降。
在本变形例的显示装置的制造方法中,在周边区域PR形成第一薄膜晶体管TFT1的工序中,在显示区域DR还形成第一薄膜晶体管TFT1,这一点与上述实施方式不同。
在显示区域DR形成第二薄膜晶体管TFT2。在形成第二栅电极GE2之前,在位于第二栅电极GE2下方的绝缘层形成有到达第一沟道层CH1的上表面的贯穿孔142。与第二栅电极GE2的形成同时地,在贯穿孔142内形成第一接触插塞CP1,并且形成金属层140。金属层140以与第一接触插塞CP1一体化且与第一薄膜晶体管TFT1的第一沟道层CH1的至少端部重叠的方式形成。
第二实施方式
图6是本发明的第二实施方式的显示装置的电路图。在本实施方式中,通过第一开关元件SW1将影像信号写入至电容器C,通过第二开关元件SW2来控制流过显示元件DE的电流,通过第三开关元件SW3来开启/关断电流供给。
图7是示出第二实施方式的电路层216的详细的概略图。在本实施方式中,图6示出的电容器C由串联连接的多个电容器(第一电容器C1、第二电容器C2及第三电容器C3)构成。
第一电容器C1包括向低温多晶硅的层注入离子而形成的一对电极E1。一对电极E1在与形成在周边区域PR的第一薄膜晶体管TFT1(图4参照)的第一沟道层CH1及第一栅电极GE1同一层以与第一栅电极GE1相同的材料构成。
第二电容器C2的一对电极E2由如下的电极构成:由作为第二开关元件SW2的第二薄膜晶体管TFT2的第二沟道层CH2的一部分(从与第二栅电极GE2的重叠部分溢出且被降低电阻的部分)构成的电极;以及在其上方形成的电极(在与第二栅电极GE2同一层由相同材料形成)。
第三电容器C3的一对电极E3由第二电容器C2的一个电极E2和在其上方形成的电极构成。第二电容器C2和第三电容器C3通过共用一个电极而串联连接。在第二电容器C2或第三电容器C3的未共用的另一个电极通过接触插塞CP而连接有第一电容器C1的一个电极E1。其他详细与在第一实施方式中说明的内容对应。在本实施方式的显示装置的制造方法中,在周边区域PR形成第一薄膜晶体管TFT1(参照图4)时,同时形成第三电容器C3的一对电极E3。另外,在形成第二薄膜晶体管TFT2时,形成第二电容器C2的一对电极E2(第三电容器C3的一个电极E3)。此后,形成第三电容器C3的另一个电极E3。
此外,显示装置不限于有机电致发光显示装置,也可以为在各像素具备量子点发光元件(QLED:Quantum‐Dot Light Emitting Diode)这种发光元件的显示装置,还可以为液晶显示装置。
本发明并非限定于上述实施方式,能够进行种种变形。例如,在实施方式中说明的结构能够利用实质上为同一结构、起到同一作用效果的结构或能够达到同一目的的结构替换。
Claims (13)
1.一种显示装置,其特征在于,具有:
多个像素电极,其设于用于显示图像的显示区域;
共用电极,其配置在所述多个像素电极的上方;
发光元件层,其夹设在所述多个像素电极与所述共用电极之间;以及
由多个层构成的电路层,所述多个层从所述显示区域到达位于所述显示区域的外侧的周边区域,
所述电路层在所述显示区域及所述周边区域分别具有多个薄膜晶体管,
设于所述周边区域的所述多个薄膜晶体管为交错型的第一薄膜晶体管,该第一薄膜晶体管具有由低温多晶硅构成的第一沟道层,且在第一源电极与第一栅电极之间及第一漏电极与第一栅电极之间不存在所述第一沟道层,
设于所述显示区域的所述多个薄膜晶体管包括交错型的第二薄膜晶体管,该第二薄膜晶体管具有由氧化物半导体构成的第二沟道层,且在第二源电极与第二栅电极之间及第二漏电极与第二栅电极之间不存在所述第二沟道层,
所述第二薄膜晶体管与所述第一薄膜晶体管相比位于更上层的位置。
2.如权利要求1所述的显示装置,其特征在于,
设于所述显示区域的所述第二薄膜晶体管以能够控制向所述多个像素电极的每一个供给的电流的供给量的方式被连接。
3.如权利要求1所述的显示装置,其特征在于,
构成所述电路层的所述多个层在所述显示区域包括向所述低温多晶硅的层注入离子而形成的导电层,
所述导电层位于与所述第一薄膜晶体管的所述第一沟道层同一层的位置,且与所述第二薄膜晶体管相比位于更下层的位置。
4.如权利要求3所述的显示装置,其特征在于,
所述导电层具有与所述第二薄膜晶体管的整体重叠的大小。
5.如权利要求3所述的显示装置,其特征在于,
构成所述电路层的所述多个层在所述显示区域还包括第二导电层,将所述导电层作为电容器的一个电极,所述第二导电层在与所述导电层相对的位置成为另一个电极,
所述第二导电层位于与所述第一薄膜晶体管的所述第一栅电极同一层的位置,且与所述第二薄膜晶体管相比位于更下层的位置。
6.如权利要求1~5中任一项所述的显示装置,其特征在于,
设于所述显示区域的所述多个薄膜晶体管在与所述周边区域的所述第一薄膜晶体管同一层的位置还包括所述第一薄膜晶体管。
7.如权利要求1~5中任一项所述的显示装置,其特征在于,
还具有接触插塞,该接触插塞将所述电路层的所述第一薄膜晶体管上方的层贯穿,且与所述第一沟道层连接,
构成所述电路层的所述多个层还包括金属层,该金属层以与所述第一薄膜晶体管的所述第一沟道层的至少端部重叠的方式,在与所述第二薄膜晶体管的所述第二栅电极同一层的位置由与所述第二栅电极相同的材料构成,
所述金属层以与所述接触插塞成为一体的方式形成。
8.一种显示装置的制造方法,所述显示装置具有用于显示图像的显示区域及位于所述显示区域的外侧的周边区域,所述显示装置的制造方法的特征在于,包括:
在所述周边区域形成交错型的第一薄膜晶体管的工序,所述第一薄膜晶体管具有由低温多晶硅构成的第一沟道层,且在第一源电极与第一栅电极之间及第一漏电极与第一栅电极之间不存在所述第一沟道层;
在形成所述第一薄膜晶体管之后,在所述显示区域形成交错型的第二薄膜晶体管的工序,该第二薄膜晶体管具有由氧化物半导体构成的第二沟道层,且在第二源电极与第二栅电极之间及第二漏电极与第二栅电极之间不存在所述第二沟道层;
在形成所述第二薄膜晶体管之后,在所述显示区域形成多个像素电极的工序;
在所述多个像素电极的上方形成发光元件层的工序;以及
在所述发光元件层的上方形成共用电极。
9.如权利要求8所述的显示装置的制造方法,其特征在于,
在所述周边区域形成所述第一薄膜晶体管的工序中,在所述显示区域通过形成所述低温多晶硅的层并注入离子而形成导电层。
10.如权利要求9所述的显示装置的制造方法,其特征在于,
所述导电层以具有与所述第二薄膜晶体管的整体重叠的大小的方式形成。
11.如权利要求9所述的显示装置的制造方法,其特征在于,
在所述周边区域形成所述第一薄膜晶体管的工序中,与所述第一栅电极的形成同时地,形成成为用于与所述导电层一起构成电容器的电极的第二导电层。
12.如权利要求8~11中任一项所述的显示装置的制造方法,其特征在于,
在所述周边区域形成所述第一薄膜晶体管的工序中,在所述显示区域也形成所述第一薄膜晶体管。
13.如权利要求8~11中任一项所述的显示装置的制造方法,其特征在于,
在所述显示区域形成所述第二薄膜晶体管的工序中,
在形成所述第二栅电极之前,在与所述第二栅电极相比位于下方的绝缘层形成到达所述第一沟道层的上表面的贯穿孔,
与所述第二栅电极的形成同时地,在所述贯穿孔内形成接触插塞,而且以与所述接触插塞成为一体且与所述第一薄膜晶体管的所述第一沟道层的至少端部重叠的方式形成金属层。
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US20170278916A1 (en) | 2017-09-28 |
US11404516B2 (en) | 2022-08-02 |
JP2017173505A (ja) | 2017-09-28 |
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US20230354647A1 (en) | 2023-11-02 |
US10236330B2 (en) | 2019-03-19 |
KR20170110503A (ko) | 2017-10-11 |
US20210083029A1 (en) | 2021-03-18 |
US11744111B2 (en) | 2023-08-29 |
KR102013488B1 (ko) | 2019-08-22 |
TWI649881B (zh) | 2019-02-01 |
US10886351B2 (en) | 2021-01-05 |
CN107230690B (zh) | 2020-09-22 |
TW201735373A (zh) | 2017-10-01 |
CN112038376A (zh) | 2020-12-04 |
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US20220310735A1 (en) | 2022-09-29 |
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