CN107204286A - 晶片的加工方法 - Google Patents

晶片的加工方法 Download PDF

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CN107204286A
CN107204286A CN201710156871.6A CN201710156871A CN107204286A CN 107204286 A CN107204286 A CN 107204286A CN 201710156871 A CN201710156871 A CN 201710156871A CN 107204286 A CN107204286 A CN 107204286A
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chip
resin
die bond
separating tank
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CN107204286B (zh
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小清水秀辉
荒谷侑里香
杉谷哲
杉谷哲一
灰本隆志
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Disco Corp
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Abstract

提供晶片的加工方法,对于采用先划片方式的情况下的半导体器件芯片的背面,不使生产性恶化而对各个器件芯片敷设固晶用树脂。该晶片在正面上由分割预定线划分而形成有多个器件芯片,该晶片的加工方法包含如下的工序:分离槽形成工序,沿着分割预定线形成深度相当于器件芯片的完工厚度的分离槽;分割工序,将保护部件配设在晶片的正面上,对晶片进行薄化而使分离槽在晶片的背面露出,将晶片分割成各个器件芯片;固晶用树脂敷设工序,向该晶片的背面涂布液状的固晶用树脂并使其固化,从而按照希望的厚度将固晶用树脂敷设在各个器件芯片的背面上;以及分离工序,将背面上敷设有该固晶用树脂的该器件芯片从晶片分离。

Description

晶片的加工方法
技术领域
本发明涉及晶片的加工方法,形成多个在背面上具有固晶(die bond)用树脂的器件芯片。
背景技术
在IC、LSI等中使用的半导体器件芯片的制造工艺中,将在正面上由分割预定线划分而形成有多个器件的晶片分割成各个器件芯片,从而形成半导体器件芯片。并且,通过对该半导体器件芯片进行封装而将其应用于移动电话、个人计算机等电子设备中。
分割得到的半导体器件芯片被粘合(粘结)在引线框架(金属制基板)等上,作为对该半导体器件芯片的背面敷设用于与引线框架粘结的粘合剂的方法,公知如下方法:在分割成各个器件芯片之前的晶片的背面上粘贴与该晶片大致相同大小的DAF(die-attachfilm:同时具有划片带和粘合剂的功能的膜),从晶片的正面侧通过划片将晶片分割成各个器件芯片,并且与各个器件芯片对应地将粘合剂切断,将分割得到的各个器件芯片从该晶片分离而取出,从而得到在背面上敷设有粘合剂的半导体器件芯片(例如,参照专利文献1)。
在采用上述那样的粘合剂敷设方法的情况下,以如下操作为前提:在从背面侧进行磨削(薄化)以使晶片达到希望的厚度并将该DAF粘贴在磨削后的背面上的基础上从正面侧进行划片,将晶片分割成各个器件芯片。
然而,在采用从正面侧利用切削刀具进行设置出深度相当于完工厚度的分离槽的切割然后对背面进行磨削从而分割成各个器件芯片的所谓的被称为先划片的技术的情况下,由于与完成背面磨削同时地将晶片分割成各个器件芯片,所以难以采用上述那样的方法。因此,当对采用了先划片方式的情况下的器件芯片的背面敷设作为粘合剂的例如固晶用树脂的情况下,尝试了如下方式:在分割成各个器件芯片之后,在将各个半导体器件芯片从晶片取出之前,将固晶用的树脂膜粘贴在晶片的整个背面上,并从晶片的正面的分离槽侧采取照射激光光线等方式而与该半导体器件芯片对应地对该膜进行分割(例如,参照专利文献2)。另外,作为沿着分割预定线形成深度相当于器件芯片的完工厚度的分离槽的方法,并不仅限于利用上述切削刀具,也能够通过蚀刻等来形成上述分离槽(例如,参照专利文献3)。
专利文献1:日本特开2000-182995号公报
专利文献2:日本特开2002-118081号公报
专利文献3:日本特开2006-294913号公报
在采用了上述的先划片方式的情况下的敷设固晶用树脂的方法中,产生了如下问题:需要区别于半导体器件的分割而对粘结在背面上的固晶用的树脂膜进行切断,变成比较复杂的工序。另外,关于结束了在划片之后执行的背面磨削而被分割成各个半导体器件芯片后的晶片的分割预定线,存在因背面磨削时的从磨削砂轮机施加的负荷而导致与分割前的分割预定线相比其宽度、位置发生变化而直线性受损等可能性,也存在很难通过物理的加工构件例如切削刀具沿着该分割预定线直线状地实施加工而进行分割的担心。特别是在器件较小的情况(例如,2mm见方以下的器件)下,被分割的器件的个数变多,更难沿着分割预定线实施物理性的加工,存在生产性恶化的问题。
发明内容
本发明是鉴于上述事实而完成的,其主要的技术性课题在于提供晶片的加工方法,对于采用先划片(Dicing Before Grinding)方式的情况下的从晶片分离出的器件芯片的背面,不使生产性恶化而对各个器件芯片敷设固晶用树脂。
为了解决上述主要的技术课题,根据本发明,提供晶片的加工方法,该晶片在正面上由交叉的多条分割预定线划分而形成有多个器件,其中,该晶片的加工方法包含如下的工序:分离槽形成工序,沿着分割预定线形成深度相当于器件芯片的完工厚度的分离槽;分割工序,在实施了该分离槽形成工序之后,将保护部件配设在晶片的正面上,对晶片进行薄化而使该分离槽在晶片的背面露出,将晶片分割成各个器件芯片;固晶用树脂敷设工序,在实施了该分割工序之后,向该晶片的背面涂布液状的固晶用树脂并使其固化,从而按照希望的厚度将固晶用树脂敷设在各个器件芯片的背面上;以及分离工序,将背面上敷设有该固晶用树脂的该器件芯片从晶片分离,该固晶用树脂敷设工序包含如下的工序:薄膜层形成工序,使液状的该固晶用树脂成为雾状而涂布在晶片的背面上从而形成薄膜层;以及外界刺激施加工序,通过对该薄膜层施加外界刺激而使该薄膜层固化,将该薄膜层形成工序和外界刺激施加工序交替并且反复进行至少两次以上而使该固晶用树脂形成为希望的厚度。
在该分离槽形成工序中,通过使切削刀具沿着分割预定线切入、或者湿蚀刻或干蚀刻、或者沿着分割预定线照射激光光线来形成具有相当于器件芯片的完工厚度的深度的分离槽。
优选在该分割工序中晶片的背面进行磨削而对晶片进行薄化,从而使该分离槽在晶片的背面露出。
优选在该固晶用树脂敷设工序之后实施如下的移换工序:在敷设有该固晶用树脂的晶片的背面上粘贴粘合带,并且利用具有对该晶片进行收纳的开口的框架而借助该粘合带对晶片进行支承,并将保护部件从该晶片的正面去除,在实施了该移换工序之后,实施该分离工序,从该粘合带拾取器件芯片。
优选该薄膜层形成工序包含如下的工序:保持工序,使该晶片的背面露出而将晶片保持在能够旋转的工作台上;以及涂敷工序,使该工作台旋转并使液状的该固晶用树脂成为雾状而涂布在该晶片的背面上。
优选通过该薄膜层形成工序而涂布的固晶用树脂是紫外线硬化型树脂,所施加的外界刺激是紫外线照射。或者该固晶用树脂可以是热硬化型树脂,所施加的外界刺激可以是加热。并且,优选该薄膜层的厚度为3μm~7μm,该固晶用树脂的希望的厚度为30μm~50μm。
根据本发明的晶片的加工方法,能够将固晶用的树脂以液状状态涂布在分割得到的各个器件芯片的背面上,与各个器件芯片对应地进行敷设。因此,即使是在通过先划片得到各个器件芯片的情况下,也不需要另外照射激光光线而将DAF与器件芯片对应地进行分割等工序,提高生产性。
附图说明
图1的(a)和(b)是示出用于执行分离槽形成工序的切削装置的一部分的立体图和晶片的A-A剖视图。
图2的(a)和(b)是示出安装保护部件的工序的立体图。
图3的(a)和(b)是示出对晶片的背面进行磨削而将晶片分割成器件芯片的分割工序的立体图。
图4的(a)和(b)是示出在树脂敷设工序中涂布液状的固晶用树脂的工序和对液状的固晶用树脂照射紫外线的工序的立体图。
图5是示出在移换工序中将保护部件剥离的工序的立体图。
图6是示出将器件芯片从晶片分离的分离工序的剖视图。
标号说明
10:主轴单元;11:主轴外壳;12:旋转主轴;13:切削刀具;21:器件芯片;22:分离槽;23:保护带(保护部件);30:卡盘工作台;33:磨削磨轮;50:涂布单元;51:涂布喷嘴;52:混合单元;53:摇动单元;54:高压空气容器;55:液体树脂容器;60:固晶用树脂层;70:分离装置;71:框架保持部件;72:夹具;73:扩张滚筒;720:支承构件。
具体实施方式
以下,参照附图对本发明的晶片的加工方法的优选的实施方式进行详细地说明。
在图1中示出了执行分离槽形成工序的状态,沿着形成在半导体晶片W的正面侧的分割预定线形成厚度相当于器件芯片的完工厚度的分离槽,该半导体晶片W是本实施方式中的被加工物。
如图1的(a)所示,通过具有主轴单元10的切削装置(省略了装置整体的图示)来执行上述分离槽形成工序。该主轴单元10具有对固定在主轴12的前端部的切削刀具13进行保持的主轴外壳11。以规定的厚度(例如为700μm)形成的加工前的该半导体晶片W的正面20a侧被分割预定线划分成多个区域,在该划分出的各区域内形成有器件21。使与主轴12一起高速旋转的切削刀具13相对于背面侧20b侧被吸引保持在切削装置的保持工作台(图示省略)上的半导体晶片W下降而使其切入,并使该保持工作台和切削刀具13在加工进给方向上相对移动,由此,如作为图1的(a)的A-A剖视图而示出的图1的(b)所示,形成沿着分割预定线的、深度相当于器件芯片的完工厚度(例如为50μm)而且具有规定的槽宽度(例如为30μm)的分离槽22。另外,图1的(b)为了方便说明而强调记载了分离槽22,并没有按照实际的尺寸。
该切削装置构成为:能够按照针对沿着切削刀具13的切削方向的加工进给方向、与该加工进给方向垂直的分度进给方向、以及使切削刀具13朝向半导体晶片W上下动作的切割方向中的任意方向预先存储的程序进行控制而在半导体晶片W上的全部的分割预定线上形成与上述同样的分离槽22,当该分离槽形成工序结束时,从切削装置的保持工作台取出半导体晶片W。另外,虽然上述分离槽22被设定为相当于器件芯片的完工厚度的深度,但并不需要与器件芯片的完工厚度严格地一致,只要是当通过后述的磨削装置进行磨削并磨削加工至希望的完工厚度时,作为结果能够分割成各个器件芯片的深度即可,也可以设定为比该希望的完工厚度稍微深些。
如图2的(a)所示,该分离槽形成工序结束后,在所取出的半导体晶片W的正面20a侧粘贴作为用于对器件21进行保护的保护部件的保护带23(保护部件粘贴步骤),并转移到将通过该保护部件粘贴步骤得到的该半导体晶片W(参照图2的(b))分割成各个器件芯片的分割工序。
根据图3对分割工序进行说明。如图3的(a)所示,关于粘贴有保护带23的半导体晶片W,将该保护带23侧定位并固定在磨削装置(省略了整体的说明)所具有的卡盘工作台30上。卡盘工作台30构成为能够通过未图示的电动机而旋转,其上表面部由具有微细的通气孔的多孔陶瓷形成,并与未图示的吸引构件连通。这样构成的卡盘工作台30通过使未图示的吸引构件工作而对载置在该卡盘工作台30的上表面即保持面上的半导体晶片W进行吸引保持。
在磨削装置的卡盘工作台30的上方具有由未图示的伺服电动机驱动的主轴31,在被设定在相对于卡盘工作台30的中心偏心的位置上的主轴31的下端形成有安装座32。通过螺栓将具有用于对吸引保持在卡盘工作台30上的半导体晶片W进行磨削的磨削磨具的磨削磨轮33牢固地固定在安装座32上。该磨削装置具有磨削进给构件,该磨削进给构件用于使由上述主轴31、安装座32、磨削磨轮33和未图示的伺服电动机构成的磨削单元在作为上下方向的磨削进给方向上移动。
通过上述磨削进给构件将磨削磨轮33的磨削磨具压接在吸引保持于卡盘工作台30上的半导体晶片W上。此时,卡盘工作台30以300rpm的旋转速度被驱动,磨削磨轮33以6000rpm的旋转速度被驱动并朝向下方以1μm/秒的速度进行磨削进给。当一边通过未图示的接触式或非接触式的厚度测量仪对半导体晶片W的厚度进行测量一边将半导体晶片W磨削至希望的完工厚度(50μm)时,如图3的(b)所示,上述的分离槽形成工序中所形成的分离槽22在背面侧露出,其结果是,半导体晶片W被分割成各个器件芯片。当这样分割出各个器件芯片时,成为在各个器件芯片的正面上配设有对该正面进行保护的作为保护部件的保护带23的状态,本发明的分割工序结束。
根据图4对按照本发明执行的固晶用树脂敷设工序进行说明。如图4的(a)所示,将上述的分割工序中被磨削的该半导体晶片W的背面侧作为上表面而使保护带23侧保持在固晶用树脂敷设装置(省略了装置整体的图示)的保持工作台40上。该保持工作台40也具有与上述卡盘工作台30同样的结构,构成为能够通过未图示的吸引构件进行吸引保持并且通过未图示的伺服电动机进行旋转。
在将半导体晶片W保持在保持工作台40上之后,通过设置在固晶用树脂敷设装置的保持工作台40附近的涂布单元50来执行薄膜层形成步骤。该涂布单元50包含:涂布喷嘴51,其延伸成其前端部51a位于保持工作台40所保持的半导体晶片W的上方;混合单元52,其对后述的液状的固晶用树脂和高压空气进行混合而提供给涂布喷嘴51侧;摇动单元53,其具有使该涂布单元50的涂布喷嘴51沿着半导体晶片W的上表面平行地摇动(参照图中的箭头)的未图示的空气电动机;高压空气容器54,其将高压空气提供给混合单元52;以及液状树脂容器55,其将液状的固晶用树脂提供给混合单元52。
在该高压空气容器54中具有未图示的空气泵和溢流阀,构成为在工作中进行控制以使该容器内总是处于恒定的压力(例如为0.3MPa),并能够根据需要朝向混合单元52提供高压空气。并且,构成为在液状树脂容器55内填充有固晶用的树脂,并能够通过内置的泵以恒定的压力朝向混合单元52提供固晶用的树脂,其中,该固晶用的树脂在稳定情况下维持液状状态并因施加外界刺激而固化,作为粘合剂而发挥功能。作为本实施方式的固晶用树脂,采用通过照射紫外线而固化的紫外线硬化型树脂,作为该紫外线硬化型树脂,例如能够采用Honghow Specialty Chemicals Inc.(鸿浩特用化学品股份有限公司)生产的商品名为“HP20VL”或“ST20VL”的固晶用树脂。另外,除此之外也可以使用通过作为外界刺激施加规定的热量(加热)而固化的填充有银的环氧树脂,例如,Ablestik Laboratories(爱博斯迪科)生产的商品名为“Ablebond8200c”的固晶用树脂等。
在混合单元52内设置有供上述高压空气通过的未图示的缩颈部,具有能够通过细管从相对于该缩颈部垂直的方向提供上述液状树脂的所谓的文丘里构造。构成为:在从涂布喷嘴51的前端部51a喷雾出该液状树脂的情况下,从高压空气容器54提供高压空气,并从该液状树脂容器55提供液状树脂,当高压空气通过混合单元52内的该缩颈部时,因文丘里效应液状树脂从细管被吸出并且被微粒化,能够从涂布喷嘴51的前端部51a朝向半导体晶片W的背面呈雾状地喷射。另外,该混合单元52的构造并不仅限于此。也可以直接应用作为一般熟知的涂装用具而使用的空气刷等结构。
对从上述涂布喷嘴51朝向半导体晶片W的背面喷雾出该液状树脂的薄膜层形成步骤进行进一步说明。当将半导体晶片W保持在保持工作台40上时,上述涂布单元50被设定为待机状态。此时,涂布喷嘴51的前端部51a被设置在不位于半导体晶片W的上方的附近位置。这是为了在喷雾开始时不使粒径较大的液状树脂滴落至半导体晶片W。在使液状的固晶用树脂从该涂布喷嘴51喷雾的情况下,首先保持工作台40以例如500rpm的速度开始旋转。接着开始从高压空气容器54提供高压空气,之后,开始从液状树脂容器55提供液状树脂。并且,当在涂布喷嘴51的前端部51a未处于半导体晶片W的上方的状态下使来自前端部51a的喷雾开始之后,开始对摇动单元53的驱动。也就是说,一边使半导体晶片W以上述速度旋转,一边使由该摇动单元53驱动的涂布喷嘴51的前端部51a在半导体晶片W的上方往复移动。然后,在涂布喷嘴51借助摇动单元53仅进行设定的次数(例如5个往复)的往复移动之后,恢复到涂布喷嘴51的前端部51a不处于半导体晶片W之上的待机状态,并停止液状树脂的提供和高压空气的提供,也停止保持工作台40的旋转,完成薄膜层形成步骤。另外,不是一次性地进行大量地喷雾,而是如上述那样将一次的涂布处理限定为5个往复,由此,按照3μm~7μm形成液状的固晶用树脂的薄膜层。
在完成了该薄膜层形成步骤之后,如图4的(b)所示,通过作为施加外界刺激的构件的紫外线照射构件100对涂布了液状的该固晶用树脂的面照射紫外线(外界刺激施加步骤),从而能够得到固化在该半导体晶片W的各个器件芯片的背面上的固晶用树脂层60。
在本发明中,接着上述的薄膜层形成步骤执行外界刺激施加步骤,并重复进行该步骤至少两次以上。即,在呈雾状地涂布液状的固晶用树脂而形成了3μm~7μm的薄膜层之后,暂且照射紫外线而使所涂布的固晶用树脂固化。之后,再次执行该薄膜层形成步骤和外界刺激施加步骤。这样,通过重复执行两次以上的薄膜层形成步骤和外界刺激施加步骤,得到预先设定的希望的厚度(例如为30μm~50μm)的固晶用树脂层。至此,固晶用树脂敷设工序结束。另外,在采用了热硬化型树脂来作为液状的固晶用树脂的情况下,作为外界刺激施加步骤,代替上述紫外线的照射而执行由电加热器等进行的加热从而对该液状的固晶用树脂进行固化,在各个器件芯片的背面得到该固晶用树脂层60。
如上述那样,通过采用将固晶用的树脂以液状而且雾状的方式涂布在半导体晶片W的背面上并使其固化的工序重复执行两次以上从而得到希望的厚度的固晶用树脂层的方式,能够不使液状的固晶用树脂流入存在于各个器件芯片之间的、在分离槽形成工序中形成的宽度为30μm的分离槽范围内,而是使固晶用树脂仅留在器件芯片的背面上,即在由先划片实现的分割成各个器件芯片的加工之后能够在不需要进行使固晶用树脂与各个器件芯片对应而分割的工序的状态下敷设该固晶用的树脂层。
在上述的固晶用树脂敷设工序结束之后实施移换工序。如上述那样,结束了该固晶用树脂敷设工序的半导体晶片W处于分离槽22内没有侵入固晶用树脂、各个器件芯片仅通过保护带23而连结的状态。这里,将该半导体晶片W从上述树脂敷设装置的保持工作台40取下,如图5所示,将半导体器件芯片W的背面、即形成有上述固晶用树脂层60的面粘贴在伸缩性优越的粘合带T的正面上,该粘合带T的外周部被安装成覆盖环状的框架F的内侧开口部,并将为了保护正面侧而粘贴的保护带23剥离,移换工序结束。
当上述移换工序结束时,实施将背面上敷设有该树脂的该器件芯片从晶片分离的分离工序。该分离工序是利用在图6中示出了其一部分的分离装置70而实施的,该分离装置70具有:框架保持部件71;夹具72,将环状框架F载置到框架保持部件71的上表面部而由该夹具72对上述环状的框架F进行保持;以及扩张滚筒73,其由至少上方开口的圆筒形状构成,用于对由该夹具72保持的环状的框架F上所安装的半导体晶片W进行扩张。框架保持部件71被支承构件723支承为能够升降,该支承构件723包含有以围绕扩张滚筒73的方式设置的多个气缸723a和从气缸723a延伸的活塞杆723b。
该扩张滚筒73被设定为直径比环状的框架F的内径小并且比半导体晶片W的外径大,其中,该半导体晶片W粘贴在粘合带T上,该粘合带T安装在环状的框架F上。这里,如图6所示,分离装置70能够成为框架保持部件71与扩张滚筒73的上表面部为大致相同的高度的位置(如虚线所示)和通过支承构件723的作用使框架保持部件71下降而使扩张滚筒73的上端部比框架保持部件71的上端部高的位置(如实线所示)。
当使上述框架保持部件71下降而使扩张滚筒73的上端从虚线所示的位置相对地变化为实线所示的比框架保持部件71高的位置时,安装在环状的框架F上的粘合带T被推抵于扩张滚筒73的上端缘而被扩张。其结果是,由于张力呈放射状地作用于粘贴在粘合带T上的半导体晶片W,所以预先沿着分离槽22被分割的各个器件芯片彼此的间隔被扩大。并且,在各个器件芯片彼此的间隔被扩大的状态下,使拾取夹头74工作而对已分割的器件芯片进行吸附,从粘合带T剥离而进行拾取,并搬送至未图示的托盘或芯片粘合工序,通过该芯片粘合工序将器件芯片粘结在引线框架上。通过以上动作,分离工序结束,本发明的晶片的加工方法完成。另外,在上述的薄膜层形成工序中呈雾状涂布的固晶用树脂有时会稍微侵入到先形成的分离槽中,但在上述的分离工序中能够通过对粘合带T进行扩张而分离成各个器件芯片,不需要另行准备切削构件等来进行分割。
在构成上述的保护部件配设工序的一部分的分离槽形成工序中,示出了为了形成分离槽而使设置在主轴的前端部的切削刀具旋转而压接于半导体晶片的正面而进行加工从而形成分离槽的例子,但形成分离槽的方法并不仅限于此,能够采用各种方法。例如,可以采用如专利文献3所示那样的通过等离子将气体离子化/自由基化而进行蚀刻的反应性离子蚀刻等干蚀刻,或者采用使用了根据晶片的材料而选择的各种液体的湿蚀刻。并且,作为其他方法,也可以采用激光加工来形成分离槽,该激光加工使用了对于晶片的正面具有吸收性的波长的激光光线。
如上述那样,当对由固晶用树脂敷设工序实施的固晶用树脂进行涂布时,对半导体晶片背面侧喷射液状的固晶用树脂,作为此时的高压空气的压力、来自液状树脂容器的提供量或者混合单元中的混合比例,优选所喷雾的液状树脂的粒径较小并且每单位时间的喷雾量较少。当粒径过大或者每单位时间的喷雾量过多时,存在所涂布的液状树脂从背面进入已露出的分离槽内并掩埋分离槽从而与上述的以往技术同样需要另外进行分割的工序的担心。因此,作为对每单位时间的液状树脂的提供量、喷雾的粒径等具有影响的高压空气的压力的条件,只要考虑该分离槽的槽宽度、液状树脂的粘度等而选择液状树脂不会进入该分离槽的程度的条件即可。

Claims (10)

1.一种晶片的加工方法,该晶片在正面上由交叉的多条分割预定线划分而形成有多个器件,其中,该晶片的加工方法包含如下的工序:
分离槽形成工序,沿着分割预定线形成深度相当于器件芯片的完工厚度的分离槽;
分割工序,在实施了该分离槽形成工序之后,将保护部件配设在晶片的正面上,对晶片进行薄化而使该分离槽在晶片的背面露出,将晶片分割成各个器件芯片;
固晶用树脂敷设工序,在实施了该分割工序之后,向该晶片的背面涂布液状的固晶用树脂并使其固化,从而按照希望的厚度将固晶用树脂敷设在各个器件芯片的背面上;以及
分离工序,将背面上敷设有该固晶用树脂的该器件芯片从晶片分离,
该固晶用树脂敷设工序包含如下的工序:
薄膜层形成工序,使液状的该固晶用树脂成为雾状而涂布在晶片的背面上从而形成薄膜层;以及
外界刺激施加工序,通过对该薄膜层施加外界刺激而使该薄膜层固化,
将该薄膜层形成工序和外界刺激施加工序交替并且反复进行至少两次以上而使该固晶用树脂形成为希望的厚度。
2.根据权利要求1所述的晶片的加工方法,其中,
在该分离槽形成工序中,使切削刀具沿着分割预定线切入而形成深度相当于该器件芯片的完工厚度的分离槽。
3.根据权利要求1所述的晶片的加工方法,其中,
在该分离槽形成工序中,通过湿蚀刻或干蚀刻而沿着分割预定线形成深度相当于该器件芯片的完工厚度的分离槽。
4.根据权利要求1所述的晶片的加工方法,其中,
在该分离槽形成工序中,沿着分割预定线照射激光光线而形成深度相当于该器件芯片的完工厚度的分离槽。
5.根据权利要求1所述的晶片的加工方法,其中,
在该分割工序中,对晶片的背面进行磨削而对该晶片进行薄化,从而使该分离槽在晶片的背面露出。
6.根据权利要求1所述的晶片的加工方法,其中,该晶片的加工方法还包含如下的工序:
移换工序,在该固晶用树脂敷设工序之后,在敷设有该固晶用树脂的晶片的背面上粘贴粘合带,并且利用具有对该晶片进行收纳的开口的环状框架而借助该粘合带对晶片进行支承,并将保护部件从该晶片的正面去除;以及
拾取工序,在实施了该移换工序之后,从该粘合带拾取器件芯片。
7.根据权利要求1所述的晶片的加工方法,其中,
该薄膜层形成工序包含如下的工序:
保持工序,使该晶片的背面露出而将晶片保持在能够旋转的工作台上;以及
涂敷工序,使该工作台旋转并使液状的该固晶用树脂成为雾状而涂布在该晶片的背面上。
8.根据权利要求1所述的晶片的加工方法,其中,
通过该薄膜层形成工序而涂布的该固晶用树脂是紫外线硬化型树脂,所施加的外界刺激是紫外线照射。
9.根据权利要求1所述的晶片的加工方法,其中,
通过该薄膜层形成工序而涂布的该固晶用树脂是热硬化型树脂,所施加的外界刺激是加热。
10.根据权利要求1所述的晶片的加工方法,其中,
通过该薄膜层形成工序而形成的该薄膜层的厚度为3μm~7μm,该固晶用树脂的希望的厚度为30μm~50μm。
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JP6352824B2 (ja) * 2015-01-23 2018-07-04 東芝メモリ株式会社 基板処理装置、制御プログラムおよび制御方法
KR102408524B1 (ko) 2017-09-19 2022-06-14 삼성디스플레이 주식회사 표시 장치의 제조 장치 및 표시 장치의 제조 방법
CN109909623A (zh) * 2017-12-12 2019-06-21 中芯国际集成电路制造(北京)有限公司 用于晶圆的切割方法
JP7045843B2 (ja) * 2017-12-12 2022-04-01 株式会社ディスコ 被加工物の分割方法
US10685863B2 (en) * 2018-04-27 2020-06-16 Semiconductor Components Industries, Llc Wafer thinning systems and related methods
KR20210141155A (ko) 2020-05-15 2021-11-23 삼성전자주식회사 기판 디본딩 장치
US11552040B2 (en) * 2020-07-21 2023-01-10 Western Digital Technologies, Inc. Package process, DAF replacement
TWI783395B (zh) * 2021-03-03 2022-11-11 華泰電子股份有限公司 晶圓薄化方法
CN114669452B (zh) * 2022-03-26 2023-06-06 宁波芯健半导体有限公司 一种超薄芯片背胶涂覆方法、涂覆装置及存储介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005050914A (ja) * 2003-07-30 2005-02-24 Sharp Corp 半導体装置の製造方法
US20110263097A1 (en) * 2010-04-27 2011-10-27 Atsushi Yoshimura Method for manufacturing semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000182995A (ja) 1998-12-14 2000-06-30 Mitsumi Electric Co Ltd 半導体装置の製造方法
JP4109823B2 (ja) 2000-10-10 2008-07-02 株式会社東芝 半導体装置の製造方法
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
JP2005129607A (ja) * 2003-10-22 2005-05-19 Disco Abrasive Syst Ltd ウエーハの分割方法
JP2006196701A (ja) * 2005-01-13 2006-07-27 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP2006294913A (ja) 2005-04-12 2006-10-26 Disco Abrasive Syst Ltd ウェーハの分割方法
JP4942313B2 (ja) * 2005-07-07 2012-05-30 株式会社ディスコ ウエーハのレーザー加工方法
JP2008235650A (ja) * 2007-03-22 2008-10-02 Disco Abrasive Syst Ltd デバイスの製造方法
JP2009194135A (ja) * 2008-02-14 2009-08-27 Disco Abrasive Syst Ltd ダイボンディング方法及びダイボンダ
JP5659033B2 (ja) 2011-02-04 2015-01-28 株式会社東芝 半導体装置の製造方法
JP6054234B2 (ja) * 2013-04-22 2016-12-27 株式会社ディスコ ウエーハの加工方法
JP2017041574A (ja) * 2015-08-21 2017-02-23 株式会社ディスコ ウエーハの加工方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005050914A (ja) * 2003-07-30 2005-02-24 Sharp Corp 半導体装置の製造方法
US20110263097A1 (en) * 2010-04-27 2011-10-27 Atsushi Yoshimura Method for manufacturing semiconductor device

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