TWI721106B - 晶圓之加工方法 - Google Patents

晶圓之加工方法 Download PDF

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TWI721106B
TWI721106B TW106105320A TW106105320A TWI721106B TW I721106 B TWI721106 B TW I721106B TW 106105320 A TW106105320 A TW 106105320A TW 106105320 A TW106105320 A TW 106105320A TW I721106 B TWI721106 B TW I721106B
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wafer
die bonding
resin
film layer
bonding resin
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小清水秀輝
荒谷侑里香
杉谷哲一
本志
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日商迪思科股份有限公司
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Abstract

提供對採用先切割之情況的半導體裝置晶片之背面，不會使生產性惡化，對各個裝置晶片鋪設晶粒接合用樹脂的晶圓之加工方法。

其係複數裝置晶片藉由分割預定線被區劃且被形成在表面的晶圓之加工方法，其特徵在於包含：分離溝形成工程，其係沿著分割預定線，形成相當於裝置晶片之完成厚度的分離溝；分割工程，其係在晶圓之表面配設保護構件，薄化晶圓而使該分離溝表露出至晶圓之背面，將晶圓分割成各個裝置晶片；晶粒接合用樹脂鋪設工程，其係於藉由對該晶圓之背面塗佈液狀之晶粒接合用樹脂並使其固化，將晶粒接合用樹脂以期望之厚度鋪設在各個裝置晶片之背面；及分離工程，其係從晶圓分離在背面被鋪設該晶粒接合用樹脂之該裝置晶片。

Description

晶圓之加工方法
本發明係關於形成在背面具備晶粒接合用樹脂之複數的裝置晶片的晶圓之加工方法。
在被使用於IC、LSI等之半導體裝置晶片之製造製程中，複數裝置藉由分割預定線被區劃而被形成在表面的晶圓，被分割成各個裝置晶片，依此形成半導體裝置晶片。而且，藉由該半導體裝置晶圓被封裝，被利用於行動電話、個人電腦等之電氣機器。
被分割之半導體裝置晶片，被接合(接著)在引線框架(金屬製基板)等，作為對該半導體裝置晶片之背面，鋪設用以接著於引線框架之接合劑的方法，所知的有在分割成各個裝置晶片之前的晶圓之背面，貼附與該晶圓略相同大小之DAF(晶粒黏接薄膜：帶有作為切割膠帶和接合劑之功能的薄膜)，從晶圓之表面側藉由切割將晶圓分割成各個裝置晶片，同時對應於各個裝置晶片而切斷接合劑，從該晶圓分離並取出分割的各個裝置晶圓，依此取得接合劑被鋪設在背面的半導體裝置晶片(例如，參 照專利文獻1)。
於採用上述般之晶粒接合劑之鋪設方法之情況下，以將晶圓從背面側進行研磨(薄化)使成為期望之厚度，且對研磨後之背面貼附該DAF後從表面側予以切割，分割成各個裝置晶片為前提。
但是，從表面側使用切削刀進行設置相當於完成厚度之深度的分離溝之切割，之後，藉由研磨背面，分割成各個裝置晶片的被稱為所謂的先切割之情況下，因與背面研磨完成之同時，晶圓被分割成了各個裝置晶片，故難以採用上述般之方法。於是，在採用先切割之情況的裝置晶片之背面，鋪設成為晶粒接合劑之例如晶粒接合用樹脂之情況下，嘗試在分割成各個裝置晶片之後，從晶圓取出各個半導體裝置晶片之前，以在晶圓之背面全體貼附晶粒接合用之樹脂薄膜，從晶圓之表面之分離溝側照射雷射光線等之方式，使該薄膜對應於該半導體裝置晶片而予以分割(例如，參照專利文獻2)。另外，作為沿著分割預定線，形成相當於裝置晶片之完成厚度之深度的分割溝之方法，並不限定於上述切削刀，亦能夠藉由蝕刻等形成(例如，參照專利文獻3)。
〔先前技術文獻〕 〔專利文獻〕
[專利文獻1] 日本特開2000-182995號公報
[專利文獻2] 日本特開2002-118081號公報
[專利文獻3] 日本特開2006-294913號公報
在採用上述先切割之情況的鋪設晶粒接合用樹脂之方法中，產生必須與半導體裝置之分割，另外切斷被貼附於背面之晶粒接合用之樹脂薄膜，有成為比較複雜之工程的問題。再者，有結束切割後被實行之背面研磨而被分割成各個半導體裝置晶片之後的晶圓之分割預定線，藉由從背面研磨時之研磨機施加的負載，使得其寬度或位置相對於分割前之分割預定線變化，而損及直線性等之可能性，也有難以沿著該分割預定線藉由物理性之加工手段，例如切削刀，直線狀地施予加工並予以分割之虞。尤其，在裝置小之情況下(例如，2mm見方以下之裝置)，被分割之裝置的數量變多，更難以沿著分割預定線施予物理性之加工，有生產性的惡化的問題。
本發明係鑒於上述事實，其主要之技術性課題，提供對採用先切割(Dicing Before Grinding)之情況下的從晶圓被分離之裝置晶片的背面，不會使生產性惡化，對各個裝置晶片鋪設晶粒接合用樹脂的晶圓之加工方法。
為了解決上述主要之技術課題，若藉由本發 明時，提供一種晶圓之加工方法，其係複數裝置藉由交叉之複數分割預定線被區劃而被形成在表面的晶圓之加工方法，其特徵在於包含：分離溝形成工程，其係沿著分割預定線，形成相當於裝置晶片之完成厚度的分離溝；分割工程，其係實施該分離溝形成工程之後，在晶圓之表面配設保護構件，薄化晶圓而使該分離溝表露出至晶圓之背面，將晶圓分割成各個裝置晶片；晶粒接合用樹脂鋪設工程，其係於實施該分割工程之後，藉由對該晶圓之背面塗佈液狀之晶粒接合用樹脂並使其固化，將晶粒接合用樹脂以期望之厚度鋪設在各個裝置晶片之背面；及分離工程，其係從晶圓分離在背面被鋪設該晶粒接合用樹脂之該裝置晶片，該晶粒接合用樹脂鋪設工程包含：薄膜層形成工程，其係使液狀之該晶粒接合用樹脂成為霧狀而塗佈在晶圓之背面而形成薄膜層；和外在刺激賦予工程，其係對該薄膜層賦予外在刺激而使該薄膜層固化，交互並且重複至少兩次以上該薄膜層形成工程和外在刺激賦予工程而將該晶粒用樹脂形成為期望的厚度。
在該分離溝形成工程中，藉由切削刀沿著分割預定線切入，藉由濕蝕刻或乾蝕刻，藉由沿著分割預定線照射雷射光線中之任一者，形成具備相當於裝置晶片之完成厚度之深度的分離溝。
理想上，該分割工程係研磨晶圓之背面使薄化，並使該分離溝表露出於晶圓之背面。
理想上，於該晶粒接合用樹脂鋪設工程之 後，實施在被鋪設該晶粒接合用樹脂之晶圓之背面的貼附黏貼膠帶，同時在具有收容該晶圓之開口的框架經該黏貼膠帶而支撐晶圓，從該晶圓之表面除去保護構件之移轉工程，於該移轉工程之實施後，從該黏貼膠帶拾取裝置晶片而實施該分離工程。
理想上，該薄膜層形成工程包含使該晶圓之背面表露出而將晶圓保持在能夠旋轉之工作台的保持工程，和使該工作台旋轉，並使液狀之該晶粒接合用樹脂成為霧狀而塗佈在該晶圓之背面的塗覆工程。
理想上，藉由該薄膜層形成工程被塗佈之晶粒接合用樹脂係紫外線硬化型樹脂，被賦予之外在刺激係紫外線的照射。或是，該晶粒接合用樹脂係熱硬化型樹脂，可以加熱被賦予的外在刺激。再者，以該薄膜之厚度為3~7μm，該晶粒接合用樹脂之期望的厚度為30~50μm較佳。
當藉由本發明之晶圓之加工方法時，晶粒接合用之樹脂能夠在液狀狀態下塗佈於被分割的各個裝置晶片之背面，對應於各個裝置晶片而被鋪設。依此，即使在藉由先切割取得各個裝置晶片之情況，也不需要另外照射雷射光線而對應於裝置晶片分割DAF等之工程，生產性提升。
10:主軸單元
11:主軸殼體
12:主軸
13:切削刀
21:裝置
22:分離溝
23:保護膠帶(保護構件)
30:挾盤載置台
33:研削輪
50:塗佈單元
51:塗佈噴嘴
52:混合單元
53:搖動單元
54:高壓氣體槽
55:液狀樹脂槽
60:晶粒接合用樹脂層
70:分離裝置
71:框架保持構件
72:挾具
73:擴張滾筒
723:支撐手段
圖1為表示用以實行分離溝形成工程之切削裝置之一部分的斜視圖，及晶圓之A-A剖面圖。
圖2為表示安裝保護構件之工程的斜視圖。
圖3為表示研磨晶圓之背面而將晶圓分割成裝置晶片之分割工程的斜視圖。
圖4為表示在樹脂鋪設工程中塗佈液狀之晶粒接合用樹脂之工程，及對液狀之晶粒接合用樹脂照射紫外線之工程的斜視圖。
圖5為在移轉工程中，剝離保護構件之工程的斜視圖。
圖6為表示從晶圓分離裝置晶片之分離工程的剖面圖。
以下，針對藉由本發明之晶圓加工方法之最佳的實施型態，參照附件圖面詳細說明。
在圖1中，表示在本實施型態中實行沿著被形成在成為被加工物之半導體晶圓W之表面側的分割預定線，形成相當於裝置晶片之完成厚度之分離溝的分離溝形成工程之狀態。
如圖1(a)所示般，上述分離溝形成工程藉由具備有主軸單元10之切削裝置(省略裝置全體之圖 示)被實行。該主軸單元10具備有保持被固定在主軸12之前端部之切削刀13的主軸殼體11。以特定之厚度(例如，700μm)所形成之加工前之該半導體晶圓W之表面20a側，藉由分割預定線被區劃成複數區域，在該被區劃的各區域形成裝置21。使與主軸12同時高速旋轉之切削刀13，相對於背面側20b側被吸引保持在切削裝置之保持工作台(省略圖示)之半導體晶圓W，下降而予以切入，使該保持工作台和切削刀13在加工進給方向相對移動，依此如作為圖1(a)之A-A剖面圖所示之圖1(b)所示般，以相當於沿著分割預定線之裝置晶片之完成厚度(例如，50μm)之深度，形成特定之溝寬(例如，30μm)之分離溝22。另外，圖1(b)係為了方便說明強調記載分離溝22者，並非依照實際的尺寸。
該切削裝置被構成即使對朝向沿著切削刀13之切削方向之加工進給方向、與該加工進給方向正交之分度進給方向，使切削刀13朝向半導體晶圓W上下移動之切出方向中之任一者，亦可以依照事先被記憶的程式而能夠控制，在半導體晶圓W上之分割預定線上的全部形成與上述相同的分離溝22，當該分離溝形成工程結束時，從切削裝置之保持工作台取出半導體晶圓W。另外，上述分離溝22係被設定成相當於裝置晶片之完成厚度之深度，但是不一定要與裝置晶片之完成厚度嚴格一致，於藉由後述之研磨裝置被研磨，且被研磨加工成期望之完成厚度之時，就結果而言，若被分割成各個裝置晶片之深度即 可，即使設定成較該期望之完成厚度稍微深亦可。
如圖2(a)所示般，當該分離溝形成工程結束時，移至對被取出之半導體晶圓W之表面20a側，貼附用以保護裝置21之保護構件之保護膠帶23(保護構件黏貼步驟)，且將藉由該保護構件黏貼步驟所取得之該半導體晶圓W(參照圖2(b))分割成各個裝置晶片之分割工程。
根據圖3，針對分割工程進行說明。如圖3(a)所示般，被貼附保護膠帶23之半導體晶圓W係該保護膠帶23側定位在研磨裝置(省略全體之說明)所具備之挾盤載置台30上而被固定。挾盤載置台30被構成能夠藉由無圖示之馬達而旋轉，藉由其上面部具有細微之通氣孔的多孔陶瓷而被形成，被連通於無圖示之吸引手段。被構成如此之挾盤載置台30藉由使無圖示之吸引手段作動，吸引保持被載置於作為該挾盤載置台30之上面的保持面之半導體晶圓W。
在研磨裝置之挾盤載置台30之上方，具備藉由無圖示之伺服馬達而被驅動之主軸31，在被設定在相對於挾盤載置台30之中心偏心的位置之主軸31之下端，形成有固定座32。在固定座32，具備有用以研磨被吸引保持挾盤載置台30上之半導體晶圓W之研磨砥石的研磨輪33藉由螺栓被牢固固定。該研磨裝置具備用以使藉由上述主軸31和固定座32和研磨輪33和無圖示之伺服馬達所構成之研磨單元在作為上下方向之研磨進給方向移動 之研磨進給手段。
藉由上述研磨進給手段，迫使研磨輪33之研磨砥石壓接於被吸引保持在挾盤載置台30上之半導體晶圓W。此時，挾盤載置台30以300rpm被驅動，研磨輪33以6000rpm之旋轉速度被驅動，朝下方以1μm/秒之速度被研磨進給。一面以無圖示之接觸式或非接觸式之厚度測量計測量半導體晶圓W之厚度，一面將半導體導體晶圓W研磨至期望之完成厚度(50μm)時，如圖3(b)所示般，在上述分離溝形成工程中形成的分離溝22表露出至背面側，其結果，半導體晶圓W被分割成各個裝置晶片。當如此被分割成各個裝置晶片時，成為在各個裝置晶片之表面配設作為保護該表面之保護構件的保護膠帶23之狀態，本發明之分割工程結束。
根據圖4，針對依照本發明實行之晶粒接合用樹脂鋪設工程進行說明。如圖4(a)所示般，將在上述分割工程中被研磨之該半導體晶圓W之背面側設為上面，使保護膠帶23側保持在晶粒接合用樹脂鋪設裝置(省略裝置全體之圖示)之保持工作台40。該保持工作台40也具有與上述挾盤載置台30相同之構成，藉由無圖示之吸引手段被吸引保持，同時被構成能夠藉由無圖示之伺服馬達而旋轉。
將半導體晶圓W保持在保持工作台40之後，藉由被設置在晶粒接合用樹脂鋪設裝置之保持工作台40附近之塗佈單元50，實行薄膜層形成步驟。該塗佈單元 50係藉由以其前端部51a被定位在被保持於保持工作台40上之半導體晶圓W的上方之方式延伸的塗佈噴嘴51、混合後述之液狀之晶粒接合用樹脂和高壓氣體而供給至塗佈噴嘴51側之混合單元52、具備沿著半導體晶圓W之上面使該塗佈單元50之塗佈噴嘴51平行搖動(參照圖中箭號)之無圖示之氣體馬達的搖動單元53、對混合單元52供給高壓氣體之高壓氣體槽54，和對混合單元52供給液狀之晶粒接合用樹脂之液狀樹脂槽55所構成。
在該高壓氣體槽54，具備無圖示之氣體泵和釋放閥，在作動中，該槽內總是被控制成為一定之壓力(例如，0.3MPa)，被構成因應所需能夠朝向混合單元52供給高壓氣體。再者，在液狀樹脂槽55，被填充在恆常維持液狀狀態，藉由賦予外在刺激使固化，且當作接合劑發揮功能之晶粒接合用之樹脂，被構成能夠藉由被內裝之泵，以一定壓力朝混合單元52供給。作為本實施型態中之晶粒接合用樹脂，採用藉由照射紫外線使固化之紫外線硬化型樹脂，作為該紫外線硬化型樹脂，例如可以採用Honghow Specialty Chemicals Inc.製造之產品名稱「HP20VL」或「ST20VL」。另外，其他作為外在刺激，亦能夠使用藉由施加特定之熱(加熱)以予以固化之銀填充環氧樹脂，例如Ablestik Laboratories製造之產品名稱「Ablebond 8200c」等。
在混合單元52內，設置上述高壓氣體通過之無圖示之縮頸部，具備上述液狀樹脂能夠從對該縮頸部呈 正交之方向藉由細管供給的所謂文氏管構造。被構成於從塗佈噴嘴51之前端部51a噴霧該液狀樹脂之情況下，從高壓氣體槽54供給高壓氣體，從該液狀樹脂槽55供給液狀樹脂，於高壓氣體通過混合單元52內之該縮頸部之時，藉由文氏管效果，液狀樹脂從細管被吸出，同時被微粒化，能夠從塗佈噴嘴51之前端部51a朝向半導體晶圓W之背面霧狀地噴射。另外，該混合單元52之構造並不限定於此。亦能夠在原有狀態下適用以一般所知的塗裝用具被使用之氣體刷具等的構成。
針對從上述塗佈噴嘴51朝向半導體晶圓W之背面噴霧該液狀樹脂之薄膜形成步驟，進一步予以說明。當半導體晶圓W被保持在保持工作台40上時，上述塗佈單元50被設定成待機狀態。此時，塗佈噴嘴51之前端部51a被設定在無位於半導體晶圓W之上方的附近。此係因為使成為於噴霧開始時，大的粒徑之液狀樹脂不滴下於半導體晶圓W上之故。當在從該塗佈噴嘴51噴霧液狀之晶粒接合用樹脂之情況下，首先保持工作台40以例如500rpm之速度開始旋轉。接著，開始從高壓氣體54供給高壓氣體，之後，從液狀樹脂槽55開始供給液狀樹脂。而且，在塗佈噴嘴51之前端部51a不在半導體晶圓W之上方之狀態下，開始從前端部51a的噴霧之後，開始搖動單元53之驅動。即是，一面使半導體晶圓W以上述速度旋轉，一面迫使藉由該搖動單元53被驅動之塗佈噴嘴51之前端部51a在其上方往返移動。而且，藉由搖動單元 53，若塗佈噴嘴51僅以設定次數(例如5往返)往返移動時，塗佈噴嘴51之前端部51a返回至不在半導體晶圓W上之待機狀態，液狀樹脂之供給、高壓氣體之供給被停止，保持工作台40之旋轉也停止，薄膜層形成步驟完成。另外，不一次大量噴霧，如上述般將一次之塗佈處理限定成5往返，依此使液狀之晶粒接合用樹脂之薄膜層以3~7μm被形成。
於該薄膜層形成步驟完成之後，如圖4(b)所示般，對被塗佈液狀之該晶粒接合用樹脂的表面，藉由作為賦予外在刺激之手段的紫外線照射手段100，照射紫外線(外在刺激賦予步驟)，可以在該半導體晶圓W之各個的裝置晶片之背面，取得被固化之晶粒接合用樹脂層60。
在本發明中，接續於上述薄膜層形成步驟，實行外在刺激賦予步驟，重覆至少兩次以上此步驟。即是，霧狀地塗佈液狀之晶粒接合用樹脂，形成3~7μm之薄膜層之後，暫時照射紫外線，使被塗佈之晶粒接合用樹脂固化。之後，再次實行該薄膜層形成步驟和外在刺激賦予步驟。如此一來，藉由重覆實行兩次以上薄膜層形成步驟和外在刺激賦予步驟，取得事先設定之期望的厚度(例如30~50μm)之晶粒接合用樹脂層。以上，晶粒接合用樹脂鋪設工程結束。另外，於採用熱硬化型樹脂當作液狀之晶粒接合用樹脂之情況，實行藉由電加熱器等之加熱取代上述紫外線之照射，以作為外在刺激賦予步驟，使該液狀 之晶粒接合用樹脂固化，在各個裝置晶片之背面，取得該晶粒接合用樹脂層60。
如上述般，採用在半導體晶圓W之背面上以液狀且霧狀塗佈晶粒接合用之樹脂，並予以藉由重覆實行兩次以上固化之工程，以取得期望之厚度的晶粒接合用樹脂層的構成，依此不會使液狀之晶粒接合用樹脂流入至在存在於各個裝置晶片間之分離溝形成工程中被形成之30μm寬度之分離溝寬內，僅貯留在裝置晶片之背面，即是，能夠在不需要藉由先切割分割成各個裝置晶片之後使晶粒接合用樹脂對應於各個裝置晶片而予以分割之工程的狀態下，鋪設該晶粒接合用之樹脂層。
於上述晶粒接合用樹脂鋪設工程之後，實施移轉工程。如上述般，該晶粒接合用樹脂鋪設工程結束之半導體晶圓W，係晶粒接合用樹脂不侵入分離溝22，各個裝置晶片僅藉由保護膠帶23被連結的狀態。在此，從上述樹脂舖設裝置之保持工作台40拆下該半導體晶圓W，如圖5所示般，以覆蓋環狀之框架F之內側開口部之方式，被安裝在外周部之伸縮性優良的黏貼膠帶T之表面，貼附半導體裝置晶片W之背面，即是形成上述晶片接合用樹脂層60之面，剝離應保護表面側而被貼附的保護膠帶23，移轉工程結束。
當上述移轉工程結束時，實施從晶圓分離在背面鋪設該樹脂之該裝置晶片的分離工程。該分離工程係在圖6表示其一部分的分離裝置70被實施，該分離裝置 70具備框架保持構件71；和在其上面部載置環狀框架F而保持上述環狀之框架F的挾具72；和由至少上方開口之圓筒形狀所構成的擴張滾筒73，其係用以擴張被安裝於藉由該挾具72被保持之環狀的框架F之半導體晶圓W。框架保持構件71藉由以被設置成包圍擴張滾筒73之複數的汽缸723a，和從汽缸723a延伸之活塞桿723b所構成之支撐手段723被支撐成能夠升降。
該擴張滾筒73被設定小於環狀之框架F之內徑，大於被貼附於安裝在環狀之框架F之黏貼膠帶T的半導體晶圓W之外徑。在此，如圖6所示般，分離裝置70可以設為框架保持構件71、擴張滾筒73之上面部成為略相同之高度的位置(以虛線表示)，和藉由支撐手段723之作用迫使框架保持構件71下降，擴張滾筒73之上端部高於框架保持構件71之上端部之位置(以實線表示)。
當使上述框架保持構件71下降，使擴張滾筒73之上端從以虛線表示之位置相對於性地變化成高於以實線表示之框架保持構件71之位置時，被安裝於環狀之框架F之黏貼膠帶T被推壓至擴張滾筒73之上端緣而迫使擴張。其結果，由於拉伸力放射狀地作用於被貼附於黏貼膠帶T之半導體晶圓W，故事先沿著分離溝22而被分割之各個裝置晶片彼此之間隔被擴寬。而且，搬運至在各個裝置晶片彼此之間隔被擴寬之狀態下，使拾取夾套74作動而吸附已被分割之裝置晶片，從黏貼膠帶T剝離而予以拾取，將裝置晶片接合於無圖示之托盤或引線框架的晶 粒接合工程。藉由上述，分離工程結束，完成藉由本發明之晶圓的加工方法。另外，雖然有在上述薄膜層形成工程中霧狀地塗佈之晶粒接合用樹脂，僅侵入先前被形成之分離溝之情形，但是藉由在上述分離工程中擴張黏貼膠帶T能夠分離成各個裝置晶片，用不著需要另外準備切削手段等而予以分割。
在構成上述保護構件配設工程之一部分的分離溝形成工程中，雖然表示為了形成分離溝，使被設置在主軸之前端部的切削刀旋轉且壓接於半導體晶圓之表面而予以加工之例，但是形成分離溝之方法並不限定於此，能夠取得各種方法。例如，能夠採用如專利文獻3所示般，藉由電漿使氣體離子化、自由基化而予以蝕刻之反應性離子蝕刻等之乾蝕刻，或是使用因應晶圓之材料而被選擇之各種液體的濕蝕刻。再者，作為其他之方法，亦可以採用使用相對於晶圓之表面具有吸收性之波長的雷射光線之雷射加工。
如上述般，於塗佈在晶粒接合用樹脂鋪設工程中被實施之晶粒接合用樹脂之時，雖然對半導體晶圓背面側射液狀之晶粒接合用樹脂，但是此時之高壓氣體之壓力、來自液狀樹脂槽之供給量，或是在混合單元之混合比例，以噴霧之液狀樹脂之粒徑細，每小時之噴霧量少為佳。當粒徑過大，或每小時之噴霧量過多時，被塗佈之液狀樹脂從背面進入且被埋入至表露出的分離溝內，有與上述先前技術相同需要另外分割的工程之虞。依此，若對每 小時之液狀樹脂之供給量或噴霧之粒徑等有影響之高壓氣體之壓力的條件，考慮該分離溝之溝寬、液狀樹脂之黏度等，而選擇液狀樹脂不進入該分離溝之程度的條件即可。
23:保護膠帶
40:保持工作台
50:塗佈單元
51:塗佈噴嘴
51a:前端部
52:混合單元
53:搖動單元
54:高壓氣體槽
55:液體樹脂槽
60:晶粒接合用樹脂層
100:紫外線照射手段
W:晶圓

Claims (10)

  1. 一種晶圓之加工方法，其係複數裝置藉由交叉之複數分割預定線被區劃而被形成在表面的晶圓之加工方法，其特徵在於包含：分離溝形成工程，其係沿著分割預定線，形成相當於裝置晶片之完成厚度的分離溝；分割工程，其係實施該分離溝形成工程之後，在晶圓之表面配設保護構件，薄化晶圓而使該分離溝表露出至晶圓之背面，將晶圓分割成各個裝置晶片；晶粒接合用樹脂鋪設工程，其係於實施該分割工程之後，藉由對該晶圓之背面塗佈液狀之晶粒接合用樹脂並使其固化，將晶粒接合用樹脂以期望之厚度鋪設在各個裝置晶片之背面；及分離工程，其係從晶圓分離在背面被鋪設該晶粒接合用樹脂之該裝置晶片，該晶粒接合用樹脂鋪設工程包含：薄膜層形成工程，其係利用高壓氣體使液狀之該晶粒接合用樹脂成為霧狀而塗佈在晶圓之背面而形成薄膜層；和外在刺激賦予工程，其係對該薄膜層賦予外在刺激而使該薄膜層固化，交互並且重複至少兩次以上該薄膜層形成工程和外在刺激賦予工程而將該晶粒用樹脂形成為期望的厚度，上述高壓氣體之壓力及在每單位時間內被塗佈之上述霧狀之晶粒接合用液狀樹脂的量，係考慮上述分離溝之溝 寬及液狀之上述晶粒接合用液狀樹脂之黏度，而被設定成防止該晶粒接合用液狀樹脂進入至上述分離溝中。
  2. 如請求項1所記載之晶圓之加工方法，其中該分離溝形成工程係切削刀沿著分割預定線切入，形成相當於該裝置晶片之完成厚度之深度的分離溝。
  3. 如請求項1所記載之晶圓之加工方法，其中該分離溝形成工程係藉由濕蝕刻或乾蝕刻而在分割預定線形成相當於該裝置晶片之完成厚度之深度的分離溝。
  4. 如請求項1所記載之晶圓之加工方法，其中該分離溝形成工程係沿著分割預定線照射雷射光線而形成相當於該裝置晶片之完成厚度之深度的分離溝。
  5. 如請求項1所記載之晶圓之加工方法，其中該分割工程係研磨晶圓之背面而使薄化且使該分離溝表露出至晶圓之背面。
  6. 如請求項1所記載之晶圓之加工方法，其中進一步包含移轉工程，其係在該晶粒接合用樹脂鋪設工程之後，在鋪設該晶粒接合用樹脂之晶圓的背面貼附黏貼膠帶，同時以具有收容該晶圓之開口的環狀框架，經由該黏貼膠帶支撐晶圓，從該晶圓之表面除去保護構件；和拾取工程，其係於該移轉工程之實施後，從該黏接膠帶拾取裝置膠帶。
  7. 如請求項1所記載之晶圓之加工方法，其中該薄膜層形成工程包含：使該晶圓之背面表露出而將晶圓保持在能夠旋轉之工 作台的保持工程，和使該工作台旋轉，並使液狀之該晶粒接合用樹脂成為霧狀而塗佈在該晶圓之背面的塗覆工程。
  8. 如請求項1所記載之晶圓之加工方法，其中藉由該薄膜層形成工程被塗佈之該晶粒接合用樹脂為紫外線硬化型樹脂，被賦予之外在刺激為紫外線之照射。
  9. 如請求項1所記載之晶圓之加工方法，其中藉由該薄膜層形成工程被塗佈之該晶粒接合用樹脂為熱硬化型樹脂，被賦予之外在刺激為加熱。
  10. 如請求項1所記載之晶圓之加工方法，其中在該薄膜層形成工程所形成之該薄膜層的厚度為3~7μm，該晶粒接合用樹脂之期望的厚度為30~50μm。
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Families Citing this family (9)

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JP6352824B2 (ja) * 2015-01-23 2018-07-04 東芝メモリ株式会社 基板処理装置、制御プログラムおよび制御方法
KR102408524B1 (ko) 2017-09-19 2022-06-14 삼성디스플레이 주식회사 표시 장치의 제조 장치 및 표시 장치의 제조 방법
CN109909623A (zh) * 2017-12-12 2019-06-21 中芯国际集成电路制造(北京)有限公司 用于晶圆的切割方法
JP7045843B2 (ja) * 2017-12-12 2022-04-01 株式会社ディスコ 被加工物の分割方法
US10685863B2 (en) * 2018-04-27 2020-06-16 Semiconductor Components Industries, Llc Wafer thinning systems and related methods
KR20210141155A (ko) 2020-05-15 2021-11-23 삼성전자주식회사 기판 디본딩 장치
US11552040B2 (en) * 2020-07-21 2023-01-10 Western Digital Technologies, Inc. Package process, DAF replacement
TWI783395B (zh) * 2021-03-03 2022-11-11 華泰電子股份有限公司 晶圓薄化方法
CN114669452B (zh) * 2022-03-26 2023-06-06 宁波芯健半导体有限公司 一种超薄芯片背胶涂覆方法、涂覆装置及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113283A1 (en) * 2002-03-06 2004-06-17 Farnworth Warren M. Method for fabricating encapsulated semiconductor components by etching
US20060154447A1 (en) * 2005-01-13 2006-07-13 Yoshimasa Kushima Method for manufacturing semiconductor device
US20080233712A1 (en) * 2007-03-22 2008-09-25 Disco Corporation Method of manufacturing device
US20110263097A1 (en) * 2010-04-27 2011-10-27 Atsushi Yoshimura Method for manufacturing semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000182995A (ja) 1998-12-14 2000-06-30 Mitsumi Electric Co Ltd 半導体装置の製造方法
JP4109823B2 (ja) 2000-10-10 2008-07-02 株式会社東芝 半導体装置の製造方法
JP4296052B2 (ja) * 2003-07-30 2009-07-15 シャープ株式会社 半導体装置の製造方法
JP2005129607A (ja) * 2003-10-22 2005-05-19 Disco Abrasive Syst Ltd ウエーハの分割方法
JP2006294913A (ja) 2005-04-12 2006-10-26 Disco Abrasive Syst Ltd ウェーハの分割方法
JP4942313B2 (ja) * 2005-07-07 2012-05-30 株式会社ディスコ ウエーハのレーザー加工方法
JP2009194135A (ja) * 2008-02-14 2009-08-27 Disco Abrasive Syst Ltd ダイボンディング方法及びダイボンダ
JP5659033B2 (ja) 2011-02-04 2015-01-28 株式会社東芝 半導体装置の製造方法
JP6054234B2 (ja) * 2013-04-22 2016-12-27 株式会社ディスコ ウエーハの加工方法
JP2017041574A (ja) * 2015-08-21 2017-02-23 株式会社ディスコ ウエーハの加工方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113283A1 (en) * 2002-03-06 2004-06-17 Farnworth Warren M. Method for fabricating encapsulated semiconductor components by etching
US20060154447A1 (en) * 2005-01-13 2006-07-13 Yoshimasa Kushima Method for manufacturing semiconductor device
US20080233712A1 (en) * 2007-03-22 2008-09-25 Disco Corporation Method of manufacturing device
US20110263097A1 (en) * 2010-04-27 2011-10-27 Atsushi Yoshimura Method for manufacturing semiconductor device

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