CN106876292B - 一种封装装配件及其形成方法、合并封装装配件的系统 - Google Patents
一种封装装配件及其形成方法、合并封装装配件的系统 Download PDFInfo
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- CN106876292B CN106876292B CN201710088191.5A CN201710088191A CN106876292B CN 106876292 B CN106876292 B CN 106876292B CN 201710088191 A CN201710088191 A CN 201710088191A CN 106876292 B CN106876292 B CN 106876292B
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- 238000005538 encapsulation Methods 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000003990 capacitor Substances 0.000 claims abstract description 32
- 230000011664 signaling Effects 0.000 claims abstract description 8
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000002035 prolonged effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 12
- 238000004891 communication Methods 0.000 description 14
- 230000000712 assembly Effects 0.000 description 12
- 238000000429 assembly Methods 0.000 description 12
- 239000010949 copper Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000008878 coupling Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005202 decontamination Methods 0.000 description 1
- 230000003588 decontaminative effect Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
本公开内容的实施方式涉及封装装配件以及用于形成封装装配件的方法和合并封装装配件的系统。封装装配件可以包括衬底,该衬底包括诸如BBUL等的多个构建层。在各种实施方式中,电气布线构件可以被放置在衬底的外表面上。在各种实施方式中,主逻辑管芯和第二管芯或电容器可以被嵌入在所述多个构建层中。在各种实施方式中,电气路径可以被定义在所述多个构建层中,以便在第二管芯或电容器和电气布线构件之间传送电能或接地信号,这旁路了主逻辑管芯。
Description
本申请是中国国家申请号为201310587344.2、申请日为2013年11月20日、题为“一种封装装配件及其形成方法、合并封装装配件的系统”的申请的分案申请。
技术领域
本公开内容的实施方式通常涉及集成电路的领域,且尤其涉及用于带有嵌入在多个构建层中的逻辑管芯和其他组件的封装装配件的技术和配置。
背景技术
新兴的封装装配件可以包括以各种堆叠式和/或嵌入式配置的多个管芯。封装装配件可以继续缩减为更小的尺度,以便为各种应用提供更小的形状尺寸,这些例如包括诸如电话或平板等的移动计算设备。随着管芯和封装装配件缩减到更小的尺度,通过用于多个管芯中的每一个的封装装配件的电信号传送对当前的封装装配件配置来说构成了挑战。例如,现有技术可以利用严格的设计规则,这些设计规则推动了诸如迹线宽度/间距等的互连结构的管脚间距的限制,或者可以利用可能危及多个管芯中的一个或多个的可靠性的传送技术。
附图说明
结合附图,借助于下列具体实施方式将容易理解各实施方式。为了促进这一描述,类似的参考数字指定类似的结构元素。附图的各图中,作为示例而非限制阐释了各实施方式。
图1阐释根据各种实施方式的包括嵌入在多个构建层中的主逻辑管芯和次级管芯的示例封装装配件的剖面侧视图。
图2阐释根据各种实施方式的包括嵌入在多个构建层中的主逻辑管芯和电容器的示例封装装配件的剖面侧视图。
图3阐释根据各种实施方式的包括并排嵌入在多个构建层中的主逻辑管芯和电容器的示例封装装配件的剖面侧视图。
图4示意性阐释根据一些实施方式用于制造封装装配件的方法的流程图。
图5-图15示意性阐释根据各种实施方式的封装装配件制造的各个阶段。
图16示意性阐释根据本发明的一种实现的计算设备。
具体实施方式
在下列描述中,将使用本领域中的技术人员通常用来向本领域中的其他技术人员传播他们的工作要点的术语来描述说明性实现的各方面。然而,本领域中的技术人员将明显看出,可以借助于所描述的各方面种的仅一些来实践本发明。出于解释的目的,陈述了特定的数字、材料和配置,以便提供对说明性实现的透彻理解。然而,本领域中的技术人员将明显看出,不需要特定细节就可以实践本发明。在其他实例中,忽略或简化了公知的特征,以便不模糊说明性实现。
在下列具体实施方式中,对附图进行引用,附图形成下列具体实施方式的部分,其中,类似的数字始终指定类似的部分,且其中作为阐释示出可以在其中实践的本公开内容的主题的实施方式。应理解,在不偏离本公开内容的范围的前提下,可以利用其他实施方式,且可以做出结构或逻辑改变。因此,不应以限制意义来理解下列具体实施方式,且各实施方式的范围由所附权利要求和它们的等效物界定。
出于本公开内容的目的,短语“A和/或B”意味着(A)、(B)或(A和B)。出于本公开内容的目的,短语“A、B和/或C”意味着(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)。
本描述可以使用基于透视的描述,例如顶部/底部、内部/外部、上面/下面等等。这样的描述仅仅用来促进讨论,且不预期把在此描述的实施方式的应用限定为任何具体的定向。
本描述可以使用短语“在一个实施方式中”或“在多个实施方式中”,两者均可以是指相同的或不同的实施方式中的一个或多个。此外,在相对于本公开内容的实施方式使用时,术语“包含”、“包括”、“具有”等等是同义的。
在此可以使用术语“与……耦合”以及其衍生物。“耦合”可以意指以下中的一个或多个。“耦合”可以意指两个或更多个元素处于直接物理接触或电接触。然而,“耦合”也可以意指两个或更多个元素相互间接地接触,但仍然相互协作或交互,且可以意指在被称为相互耦合的元素之间耦合或连接的一个或多个其他元素。术语“直接耦合”可以意指两个或元素处于直接接触。
在各种实施方式中,短语“被形成、被沉积或以另外方式被放置在第二特征上的第一特征”可以意指第一特征被形成、被沉积或被放置在第二特征上,且第一特征的至少一部分与第二特征的至少一部分直接接触(例如,直接物理接触和/或电接触)或非直接接触(例如,在第一特征和第二特征之间具有一个或多个其他特征)。
图1示意性地阐释包括嵌入在衬底106中的主逻辑管芯102和第二管芯104的示例封装装配件100的剖面侧视图。在各种实施方式中,衬底106可以包括其他组件被嵌入在其中的多个构建层108。在一些实施方式中,多个构建层可以包括多个“无焊点”构建层(“BBUL”)。在此所使用的“无焊点构建层”可以是指不需要使用焊料或可以被认为是“焊点”的其他附着装置的衬底的多层和嵌入在其中的组件。
在各种实施方式中,主逻辑管芯102可以是带有晶体管和其他组件的处理器核心,晶体管和其他组件可以一起形成封装装配件100被安装在其中的计算设备的“大脑”的全部或部分。在各种实施方式中,第二管芯104可以是被配置为补充主逻辑管芯的处理能力的次级逻辑管芯(例如,另一处理器核心)。在各种其他实施方式中,第二管芯104可以是任何类型的管芯,该管芯可以被包括在封装装配件100上,以便简化封装装配件100被安装在其中的系统/平台,例如存储器管芯或电源管理管芯。
电气布线构件110可以被放置在衬底106的表面上。在各种实施方式中,电气布线构件110可以包括可以把去往/来自主逻辑管芯102和/或第二管芯104的电信号传送到图1中未叙述的其他组件(例如封装装配件100被附加到其中的印刷电路板(“PCB”))的球栅阵列(“BGA”)或其他电组件。
主逻辑管芯102可以包括第一“有效”表面112和第二反面114。主逻辑管芯102也可以包括一个或多个通孔,诸如例如在第一表面112和第二表面114之间的穿硅通孔(“TSV”)116。尽管图1中示出了两个TSV 116,但这不意味着限制,且可以包括更多或更少的TSV116。尽管图中的通孔被示出为具有均匀的直边,但通孔也可以具有其他形状。例如,由激光器钻成的通孔可以倾向于具有锥形形状,例如,一个端部比相对的端部更大。
在各种实施方式中,可以在多个构建层108中形成从第二管芯104的有效表面120到主逻辑管芯102的TSV 116的电气路径118。在各种实施方式中,电气路径118可以在主逻辑管芯102和第二管芯104之间传送输入/输出(“I/O”)信号。诸如电能和/或接地信号等的去往或来自第二管芯104的其他电信号可以通过第二电气路径122被直接传送到电气布线构件110。在各种实施方式中,第二电气路径122可以包括一个或多个通孔124,这些通孔把被放置在多个构建层108的各层之间的一个或多个导电层126互连起来。
在各种实施方式中,第二电气路径122可以不穿过主逻辑管芯102,这可以允许减少主逻辑管芯102的设计限制。例如,主逻辑管芯102可以要求较少的TSV 116。这可以为其他技术构件节省主逻辑管芯102上的空间、增加主逻辑管芯102的可靠性和/或允许主逻辑管芯102更小。更小的主逻辑管芯102可以允许也把其他组件做成更小,从而减少了封装装配件100的总体尺寸。尺寸减小的封装装配件100又可以允许创建更小的计算设备,例如智能电话和平板计算机。
在各种实施方式中,在多个构建层108中可以把主逻辑管芯102嵌入在第二管芯104和电气布线构件110之间。在一些这样的实施方式中,第二电气路径122可以包括在所述多个构建层108中的两个之间的至少一个导电层126,以便把在第二管芯104和电气布线构件110之间经过的电能或接地信号传送离开主逻辑管芯102。在图1中把这样的示例示出为在主逻辑管芯102的左边和右边,其中以当第二电气路径122沿着页面向下移动时从主逻辑管芯102“输出(fan out)”的方式把通孔124和导电层126定义在多个构建层108中。在其他实施方式中,第二电气路径122可以不通过从第二管芯104到电气布线构件110的完整路径从主逻辑管芯102输出接地信号和电源扇。
在各种实施方式中,在多个构建层108中可以把第三电气路径128定义在主逻辑管芯102的第一表面112和电气布线构件110之间。在各种实施方式中,第三电气路径128可以在主逻辑管芯102和在图1中未叙述的诸如例如电路板(例如,图16的印刷电路板1602)的其他组件之间传送电信号(例如,I/O、接地、电源)。在各种实施方式中,第一电气路径118、第二电气路径122和/或第三电气路径128可以不包括焊料,这是由于可以凭借使用BBUL工艺的其他组件来制造它们。
在各种实施方式中,封装装配件100可以包括层叠封装(“POP”)焊盘130。在各种实施方式中,POP焊盘130可以被放置在封装装配件100的表面上,例如在上表面上,以便在封装装配件100和可以被堆叠在封装装配件100上的其他封装(未示出)之间传送电信号。然而,不要求这一点,且在此描述不带有POP焊盘的其他封装装配件的示例。
图2叙述带有与图1相同的组件中的多个的封装装配件200,这些组件以相似的方式编号。然而,在这一示例中,代替第二管芯104(例如,逻辑、存储器或电源管理管芯),把电容器230(或电容器的阵列)嵌入在多个构建层208中。在各种实施方式中,电容器230可以是被安放在主逻辑管芯202邻近以便减少噪声的去耦电容器。把诸如电容器230等的电容器嵌入在封装装配件200中可以允许把较少电容器放置在诸如主板等的PCB上,例如,这减少了其覆盖区。
图3叙述类似于图2的封装装配件200的封装装配件300的另一实施方式。类似地标记与图1和图2中的组件对应的组件。然而,在图3中,电容器330被嵌入为横向偏离主逻辑管芯302,且与主逻辑管芯302大致共面,这与图2中所叙述的被放置在主逻辑管芯302的不同于电气布线构件310的相对侧相反。另外,从嵌入的电容器330到电气布线元件310的电气路径可以包括比结合图1或图2所叙述的更多的导电层326,尽管这不意味着限制。在各种实施方式中,更多或更少的导电层(126、226、326)可以被包括在封装装配件中。在各种实施方式中,更多的导电层可以允许更好的电能传递。
图4图示地叙述示例制造工艺流400。图5-图15描绘对应于制造工艺流400中的各点的各种制造阶段的示例封装装配件500。因此,当描述工艺流400时,将对图5-图15中的相应阶段进行引用。
参考图4和图5,在框402,可以在空板542上形成(例如,图案化和镀)被称为“L0基准”540的结构。在各种实施方式中,基准540可以是出于对准目的而包括的镀铜构件。在许多情况中,在诸如去镶嵌(depaneling)等的各种制造步骤期间可以移除它们,以使得它们不成为最终的封装装配件500的部分。
在各种实施方式中,空板542可以是可剥离核心,且可以用诸如铜(Cu)等的各种材料来构建。在框404,在预备接收电介质膜例(如环氧树脂内建膜(Ajinomoto build-upfilm)或“ABF”叠层)时,可以把铜空板542的第一表面544和第二表面546粗糙化。在框406,第二管芯504可以结合到铜空板542的第一表面544和第二表面546。稍后将添加主逻辑管芯502。图5叙述在这一制造阶段将变成两个封装装配件500(铜空板542的每一侧上有一个)的部件。
在框408,在ABF层压中,可以在每一侧上形成(例如,添加和固化)第一构建层548并将其固化以便嵌入第二管芯504。图6中叙述在这一阶段的封装装配件500的示例。在各种实施方式中,第一构建层548和在此描述的其他构建层可以具有可以改变和/或优化以便得到可靠性、减少翘曲等等的材料性质。
在框410,可以在第一构建层548中形成通孔550,例如,在第二管芯504的I/O焊盘(未示出)和/或电源地焊盘(未示出)的顶部。在各种实施方式中,诸如例如紫外线辐射和/或二氧化碳激光的激光可以用来钻成通孔550。在框412,可以形成(例如,图案化和镀)在此可以被称为“SL1”的第一导电层552。在此描述的“导电层”可以不在底层构建层的整个表面上扩展。例如,使用定义“排除区域(keep out zone)”或“KOZ”的光刻掩膜以便确保I/O通孔中没有镀层,从而可以有选择地在第一构建层548的顶部上形成第一导电层552。图7中叙述这一阶段的封装装配件500的示例。也可以有选择地形成在此描述的其他导电层以便实现各种电气布线目标。
在框414,可以形成例如ABF层叠的第二构建层554。图8中叙述这一阶段的封装装配件500的示例。在框416,可以在第二构建层554的顶部上形成(例如,图案化或镀)第二导电层556,且通孔558在第二导电层556和第一导电层552之间通过。在各种实施方式中,该第二导电层556可以被称为“SL2”层。图9中叙述这一阶段的封装装配件500的示例。在框418,可以形成例如ABF层叠的第三构建层560。图10中叙述这一阶段的封装装配件500的示例。
在框420,可以形成用于接收主逻辑管芯502的腔562。在各种实施方式中,可以首先应用感光干膜抗蚀剂(photo-definable dry film resist)(“DFR”)材料以便定义腔562将位于何处。然后,可以使用湿喷工具来形成腔562。在曝光后不存在DFR的区域中,可以去除ABF层叠,例如,这是由于DFR与ABF的蚀刻率的差异。在各种实施方式中,可以用铜构建的第一导电层552可以充当蚀刻停止,因为一旦碰到铜就可以停止ABF蚀刻。这样的技术可以把第二构建层554的薄片保持在任一侧上的导电层552之间。图11中叙述这一阶段的封装装配件500的示例。在各种实施方式中,在形成了腔562之后,可以化学剥离剩余的DFR。
在框422,可以形成(例如,使用激光或其他相似的装置进行钻)通过第二构建层554的剩余部分的通孔564(在此称为逻辑-逻辑互连通孔,或“LLI通孔”)。在一些实施方式中,可以使用LLI通孔564来在第二管芯504和主逻辑管芯502之间传送I/O信号。在框424,为了消除残留物并用于粗糙化,可以对LLI通孔564进行去污。图12中叙述这一阶段的封装装配件500的示例。
在框426,主逻辑管芯502可以被放置到腔562中。在各种实施方式中,在放置主逻辑管芯502之前,可以把焊料放置在主逻辑管芯502的表面上,或者把焊料粘印(paste-print)在第二管芯504上。可以加热主逻辑管芯502,以使得焊料566熔融到LLI通孔564中,在第二管芯504和主逻辑管芯502之间形成LLI结合点和电连接。图13中叙述这一阶段的封装装配件500的示例。在其他实施方式中,可以不同地结合两个管芯。例如,可以使用在压力下创建电连接的各向异性导电粘合剂来结合两个管芯。
在框428,可以形成例如ABF层叠的第四构建层568。在一些实施方式中,例如图14中所示出的实施方式,可以完全地嵌入主逻辑管芯502。在其他实施方式中,可以仅部分地嵌入主逻辑管芯502。
在框430,可以形成离开第二导电层556通过各种构建层的通孔570。例如,且如图14中所示出的,通孔570被形成为通过第四构建层568和第三构建层560。在各种实施方式中,这些通孔570可以被称为“V0”逻辑互连。在图5-图15中所示出的实施方式中,当接地信号和电能向被放置在封装装配件500的表面上的电气布线构件(图5-图15中未示出,图1-图3中在110、210、310处示出的示例)行进时,通孔570被配置为在稍微更靠近(尽管不必接触)主逻辑管芯502处传送接地信号和电能。在各种其他实施方式中,例如图1和图2中所示出的那些,这样的通孔且更一般地在第二管芯(例如,104、504)或去耦电容器230和表面传送元件(110、210)之间的电气路径,可以逐渐传送离开主逻辑管芯(102、202、502)。
在各种实施方式中,用于传送诸如地信号和/或电能等的非I/O信号的通孔可以被形成为比传统的封装装配件更大,这是因为它们通过衬底而不是主逻辑管芯502。图7-图15中可以看出这一点,其中通孔550、558和570(可以对应于图1中的第一电气路径120)可以比诸如通孔564等的仅携带I/O信号的其他通孔更宽。常规封装装配件中的TSV直径可以是约~10-20μm。相反,通孔550、558、570可以更大,例如在一些实施方式中为100μm,这取决于通孔的高度和其他电气考虑。这样的更大通孔能够应对更多的电流和/或电能。
在框432,可以在第四构建层568的顶部上形成(例如,图案化和镀)可以被称为“L1”层的第三导电层572。图14中叙述这一阶段的封装装配件500的示例。
在框434,可以形成后续的构建层(例如,574)。在框436,铜空板542可以被去镶嵌并被蚀刻掉,以便创建完整的嵌入式管芯堆叠封装装配件500。图15中叙述这一阶段的封装装配件500的示例。底封装装配件500被示出为从空板542移除。可以形成带有缝隙578(有时称为“阻焊口”)的最外面的衬底层576(有时称为“阻焊层”),以使得可以把诸如阻焊球等的电气布线构件(例如,110、210、310)插入到其中。
在一些实施方式中,例如图1-图3中所示出的那些,主逻辑管芯(102、202、302)和第二管芯(204)两者或电容器(230、330)完全嵌入到多个构建层(108、208、308)中。然而,在其他实施方式中,例如图15中所示出的,主逻辑管芯502完全嵌入到构建层中,且第二管芯504被嵌入为使得第二管芯的非有效表面574与封装装配件500的顶面576齐平(如图15中所示出),或甚至稍稍高于封装装配件500的顶面576。
以最能帮助理解所要求保护的本主题的方式,依次把各种操作被描述为多个分离的操作。然而,描述次序不应被解释成暗示这些操作必定依赖于次序。使用任何合适的硬件和/或软件以便根据期望来配置,可以把本公开内容的实施方式实现为系统。
图16阐释根据各种实施方式的示例计算设备1600。在此描述的封装装配件100、200、300和500可以被安装在诸如计算设备1600等的计算设备上。例如,叙述了封装装配件1100,它可以包括图1的封装装配件100和图3的封装装配件300的组合。封装装配件1110可以包括完全嵌入的第二管芯1104、被嵌入在第二管芯1104下的主逻辑管芯1102和被嵌入且与两个管芯横向偏离的去耦合电容器1330。
在各种实施方式中,至少一个通信芯片1606可以物理耦合和电耦合到封装装配件1100。在进一步的实现中,通信芯片1606可以是封装装配件1100的部分,例如,作为被嵌入到封装装配件1100中的构建层中的附加管芯。在各种实施方式中,计算设备1600可以包括PCB 1602。对于这些实施方式,封装装配件1100和通信芯片1606可以被放置在PCB 1602上。在备选的实施方式中,可以不需要采用PCB 1602就耦合各种组件。
取决于其应用,计算设备1600可以包括可以物理耦合和电耦合到PCB1602或可以不物理耦合和电耦合到PCB 1602的其他组件。这些其他组件包括但不限于易失性存储器(例如,也称为“DRAM”的动态随机存取存储器1608)、非易失性存储器(例如,也称为“ROM”的只读存储器1610)、闪速存储器1612、输入/输出控制器1614、数字信号处理器(未示出)、加密处理器(未示出)、图形处理器1616、一个或多个天线1618、显示器(未示出)、触摸屏显示器1620、触摸屏控制器1622、电池1624、音频编解码器(未示出)、视频编解码器(未示出)、全球定位系统(“GPS”)设备1628、罗盘1630、加速度计(未示出)、陀螺仪(未示出)、扬声器1632、照相机1634和大容量存储设备(例如硬盘驱动器、固态驱动器、紧致盘(“CD”)、数字多用盘(“DVD”))(未示出)等等。在各种实施方式中,各种组件可以与其他组件集成以便形成片上系统(“SoC”)。在进一步的实施方式中,诸如DRAM 1608等的一些组件可以被嵌入在封装装配件1100中或嵌入在封装装配件1100内。
通信芯片1606可以允许用于传输去往和来自计算设备1600的数据有线通信和/或无线通信。术语“无线”及其衍生物可以用来描述可以通过使用通过非固态介质的经调制电磁辐射来传输数据的电路、设备、系统、方法、技术、通信信道等等。该术语不暗示关联的设备不包含任何线路,尽管在一些实施方式中它们可以不包含任何线路。通信芯片1606可以实现多种无线标准或协议中的任何标准或协议,包括但不限于IEEE 702.20、通用分组无线业务(“GPRS”)、演进数据优化(“Ev-DO”)、Evolved高的速度分组访问(“HSPA+”)、演进高速下行链路分组接入(“HSDPA+”)、演进高速上行链路分组接入(“HSUPA+”)、全球移动通信系统(“GSM”)、增强型数据速率GSM演进(“EDGE”)、码分多址(“CDMA”)、时分多址(“TDMA”)、数字增强无绳通信(“DECT”)、蓝牙、其衍生物、以及被称为3G、4G、5G和更高的任何其他无线协议。计算设备1600可以包括多个通信芯片1606。举例来说,第一通信芯片1606可以专用于诸如Wi-Fi和蓝牙等的短距离无线通信,且第二通信芯片1606可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO和其他等的较远距离的无线通信。
在各种实现中,计算设备1600可以是膝上型、上网本、笔记本、超极本、智能电话、计算平板、个人数字助理(“PDA”)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元(例如,游戏控制台)、数码相机、便携式音乐播放器或数字录像机。在进一步的实现中,计算设备1600可以是处理数据的任何其他电子设备。
在各种实施方式中,在此描述封装装配件以及用于形成封装装配件的方法和合并了封装装配件的系统。封装装配件可以包括衬底,该衬底包括诸如BBUL等的多个构建层。在各种实施方式中,电气布线构件可以被放置在衬底的外表面上。在各种实施方式中,主逻辑管芯和第二管芯或电容器可以被嵌入在所述多个构建层中。在各种实施方式中,电气路径可以被定义在所述多个构建层中以便在第二管芯或电容器和电气布线构件之间传送电能或接地信号,这旁路了主逻辑管芯。
在各种实施方式中,第二管芯或电容器可以是次级逻辑管芯或存储器管芯。在各种实施方式中,主逻辑管芯可以包括在主逻辑管芯的第一表面和主逻辑管芯的第二反面之间的一个或多个通孔。在各种实施方式中,电气路径是第一电气路径,封装装配件还可以包括在所述多个构建层中被定义为从次级逻辑管芯或存储器管芯的有效表面到一个或多个通孔的第二电气路径,以便在主逻辑管芯和次级逻辑管芯或存储器管芯之间传送I/O信号。在各种实施方式中,第二管芯或电容器可以是电源管理管芯。
在各种实施方式中。第一管芯和第二管芯或电容器可以完全地嵌入在所述多个构建层内。在各种实施方式中,衬底的外表面可以是第一外表面,该第一管芯可以完全地嵌入在所述多个构建层内,且第二管芯的表面可以与衬底与第一外表面反向的第二外表面齐平。在各种实施方式中,主逻辑管芯和第二管芯或电容器可以大致共面。在各种实施方式中,主逻辑管芯可以被嵌入所述多个构建层中、在第二管芯或电容器和电气布线构件之间。
在各种实施方式中,电气路径可以包括在所述多个构建层中的两个之间的导电层,以便把在第二管芯和电气布线构件之间经过的电能或接地信号传送离开主逻辑管芯。在各种实施方式中,导电层可以是第一导电层,且电气路径可以包括在所述多个构建层中的两个之间的第二导电层。在各种实施方式中,第二导电层可以平行于第一导电层且比第一导电层更接近电气布线构件。
上面对所阐释的本发明的实现的描述,包括摘要中所描述的内容,不预期是详尽的或把本发明限制在所公开的确切形式。尽管在此出于说明性目的描述了本发明的特定实现及其示例,但如相关领域中的技术人员将明白的,在本发明的范围内的各种等效的修改也是可能的。
根据上面的具体实施方式,可以对本发明做出这些修改。下列的权利要求中所使用的术语不应被解释为把本发明限制在说明书和权利要求所公开的特定实现。相反,本发明的范围应完全由下列权利要求确定,下列权利要求应根据所确立的权利要求解释原理来解释。
Claims (21)
1.一种产生封装装配件的方法,包括:
形成通过第二多个构建层从形成在第一构建层中的第一管芯或电容器至所述第二多个构建层的与所述第一构建层相对的表面的电气路径,其中所述第二多个构建层被耦合至所述第一构建层的一侧,并且其中形成所述电气路径包括:
在所述第一构建层内形成第一通孔,所述第一通孔从所述第一管芯或所述电容器的焊盘延伸至所述第一构建层的所述一侧以邻接所述第二多个构建层;
在所述第一构建层的所述一侧上形成第一导电层,所述第一导电层被耦合至所述通孔并且从所述通孔朝着所述封装装配件的与所述第二多个构建层的所述表面垂直的一侧延伸,其中所述第一导电层将位于所述第一构建层与所述第二多个构建层之间;
将第二管芯嵌入到所述第二多个构建层内,所嵌入的第二管芯位于所述第一构建层与所述第二多个构建层的表面之间,其中所述电气路径旁路所述第二管芯;以及
在所述第二多个构建层的所述表面上形成一个或多个电气构件,所述电气特征被电耦合至所述电气路径。
2.如权利要求1所述的方法,其特征在于,形成所述电气路径包括:
在所述第一构建层的所述一侧上形成所述第二多个构建层;以及
在所述第二多个构建层内形成一个或多个通孔以及一个或多个导电层,所述一个或多个通孔从所述第一导电层延伸至所述第二多个构建层的所述表面。
3.如权利要求2所述的方法,其特征在于,形成所述一个或多个通孔以及所述一个或多个导电层包括在所述第二多个构建层中的两个之间形成第二导电层,其中所述第二导电层平行于所述第一导电层,且比所述第一导电层更靠近所述电气构件。
4.如权利要求1所述的方法,其特征在于,所述电气路径是从所述第一管芯形成的,并且其中所述第一管芯包括次级逻辑管芯或存储器管芯。
5.如权利要求1所述的方法,其特征在于,将所述第二管芯嵌入到所述第二多个构建层内包括将所述第二管芯嵌入到所述第二多个构建层内,以便与所述第一管芯或所述电容器大致共面。
6.如权利要求1所述的方法,其特征在于,形成所述电气构件包括在所述第二多个构建层的所述表面上形成焊料互连结构。
7.如权利要求1所述的方法,其特征在于,所述第二管芯包括主逻辑管芯。
8.如权利要求1所述的方法,其特征在于,所述封装装配件是第一封装装配件,其中所述第一封装装配件经由背板被耦合至第二封装装配件,所述背板邻接所述第一构建层,并且其中所述方法还包括:
通过从所述第一封装装配件去镶嵌所述背板来将所述第一封装装配件与所述第二封装装配件分开。
9.如权利要求8所述的方法,其特征在于,所述第一构建层的所述一侧是所述第一构建层的第一侧,并且其中将所述第一封装装配件与所述第二封装装配件分开导致所述第一管芯或所述电容器的非有效表面与所述第一构建层的第二侧齐平或稍稍高于所述第一构建层的所述第二侧,所述第一构建层的所述第二侧与所述第一构建层的所述第一侧相对。
10.如权利要求8所述的方法,其特征在于,在所述第一封装装配件与所述第二封装装配件分开之后,所述第一管芯或电容器被完全地嵌入到所述第一构建层内。
11.如权利要求1所述的方法,其特征在于,所述电气路径是第一电气路径,并且其中所述方法还包括:
形成从所述第一管芯或所述电容器到所述第二管芯的第一侧的第一通孔;
形成通过所述第二管芯的穿硅通孔(TSV),所述TSV从所述第二管芯的所述第一侧延伸至所述第二管芯的第二侧,所述第二侧与所述第一侧相对,其中所述TSV被耦合至所述第一通孔;
形成从所述第二管芯的所述第二侧至所述第二多个构建层内的导电层的第二通孔,所述导电层位于所述第二管芯的与所述第一管芯或所述电容器的相对侧上,并且所述第二通孔被耦合至所述TSV;以及
形成通过所述第一通孔、所述TSV以及所述第二通孔的第二电气路径,其中所述第二电气路径将信号从所述第二管芯传送至所述导电层。
12.如权利要求11所述的方法,其特征在于,所述第一电气路径被布线通过的多个通孔的宽度比所述TSV的宽度更宽。
13.如权利要求11所述的方法,其特征在于,所述第一电气路径用于在所述第一管芯或所述电容器与所述一个或多个电气构件之间传送电能或接地信号。
14.如权利要求11所述的方法,其特征在于,所述第二电气路径用于在所述第二管芯与所述第一管芯或所述电容器之间传送输入/输出信号。
15.如权利要求1所述的方法,其特征在于,还包括:
形成从所述第一管芯或所述电容器至所述第二多个构建层的所述表面的多个通孔,所述多个通孔被形成为通过所述第二多个构建层,其中所述电气路径被布线在所述多个通孔内,并且其中所述多个通孔中形成于所述第二多个构建层中的第一个中的第一通孔偏离所述多个通孔中形成于所述第二多个构建层中的第二个中的第二通孔,所述第二多个构建层中的所述第二个毗邻所述第二多个构建层中的所述第一个。
16.如权利要求15所述的方法,其特征在于,形成所述电气路径包括在所述第二多个构建层中的所述第一个与所述第二多个构建层中的所述第二个之间形成导电层,其中所述导电层将所述电气路径中位于所述第一通孔内的第一部分耦合至所述电气路径中位于所述第二通孔内的第二部分。
17.如权利要求1所述的方法,其特征在于,嵌入所述第二管芯包括:
在所述第二多个构建层的至少一个构建层内形成腔;
将所述第二管芯放置在所述腔内;以及
在所述第二管芯上形成所述第二多个构建层的附加构建层,所述附加构建层用于填充所述腔以及将所述第二管芯嵌入到所述第二多个构建层内。
18.如权利要求17所述的方法,其特征在于,形成所述腔包括:
将感光干膜抗蚀剂施加到所述至少一个构建层的表面;以及
使用湿喷工具来移除所述至少一个构建层的第一部分,其中所述感光干膜抗蚀剂保护所述至少一个构建层的第二部分免于被所述湿喷工具移除。
19.如权利要求17所述的方法,其特征在于,在所述第一构建层的一侧上形成第一导电层,其中所述腔邻接所述第一导电层,并且其中所述第二管芯被放置并嵌入到第二管芯的与所述第一导电层接触的非有效表面。
20.如权利要求17所述的方法,其特征在于,所述电气路径是第一电气路径,并且所述一个或多个电气构件是第一组电气构件,并且其中所述方法还包括:
形成通过所述第二多个构建层从嵌入到所述第一构建层中的所述第一管芯或所述电容器到与所述第二多个构建层的所述第一构建层相对的所述表面的第二电气路径,其中所述第二管芯被嵌入在所述第一电气路径与第二电气路径之间,并且被所述第一电气路径和所述第二电气路径旁路;以及
在所述第二多个构建层的所述表面上形成第二组电气构件,所述第二组电气特征被电耦合至所述第二电气路径。
21.一种设备,包括用于执行如权利要求1至20中任一项所述的方法的装置。
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US20170125351A1 (en) | 2017-05-04 |
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