CN106663610A - 具有改进的非钳位感应开关抗扰性的晶体管结构 - Google Patents

具有改进的非钳位感应开关抗扰性的晶体管结构 Download PDF

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CN106663610A
CN106663610A CN201580044859.5A CN201580044859A CN106663610A CN 106663610 A CN106663610 A CN 106663610A CN 201580044859 A CN201580044859 A CN 201580044859A CN 106663610 A CN106663610 A CN 106663610A
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CN106663610B (zh
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文杰·张
马督儿·博德
陈去非
凯尔·特里尔
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Vishay Siliconix Inc
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Abstract

一种具有改进的非钳位感应开关抗扰性的横向扩散金属氧化物半导体(LDMOS)晶体管结构。该LDMOS包括第一导电类型的衬底和相邻的外延层。栅极结构在外延层之上。两者都为第二导电类型的漏区和源区位于外延层内。沟道形成于源区和漏区之间并且布置在栅极结构下方。第一导电类型的体结构至少部分地形成于栅极结构下方并且在源区下方横向延伸，其中外延层的掺杂少于体结构。导电沟槽状馈通元件穿过外延层并接触衬底和源区。LDMOS包括形成于源区下方、且横向靠近并接触所述体结构和所述沟槽状馈通元件的第一导电类型的槽区。

Description

具有改进的非钳位感应开关抗扰性的晶体管结构
背景技术
在DC-DC电源中，功率/控制MOSFET(metal oxide semiconductor field effecttransistor，金属氧化物半导体场效应晶体管)的优化需要最小化的传导损耗和开关损耗。例如，LDMOS(横向扩散MOSFET)器件在历史上已经用于在高频时要求非常低的开关损耗的RF(射频)应用中。
半导体工业将功率MOSFET的耐用性定义为当经受非钳位感应开关(unclampedinductive switching，UIS)时承受雪崩电流的能力。对于功率开关应用，在每个电路中都不能避免电感。也就是说，在UIS事件中，电路中通过功率MOSFET关断的电感将继续推动电流通过功率MOSFET。这会导致在晶体管两端存在高电压，这反过来又会导致功率MOSFET的失效，例如雪崩击穿和高温。因此，这种非钳位感应开关事件仍然是功率MOSFET耐用性的最关键的挑战之一。
电感的关键特性之一是在接通过程期间它会从电路吸收能量，并在关断过程期间将能量释放到电路中。例如，每当通过电感的电流被快速关断时，磁场感应反电磁力(counter electromagnetic force，EMF)，其可以在相应的开关两端建立惊人的高电位。当这种UIS事件发生时，由于没有钳位器件来接收存储在电感中的能量，这种巨大能量不得不由功率MOSFET器件消耗或失效。也就是说，当晶体管用作开关时，该感应电势的全部累积可能远远超过晶体管的额定击穿电压，或导致瞬时芯片温度达到临界值。在任一情况下，在不受控的UIS事件中的功率MOSFET将经历灾难性失效。
因此，功率MOSFET器件必须在UIS事件结束后再次幸存(survive)并像往常一样工作。对于更快的功率开关，例如在RF应用中，UIS抗扰性变得更具挑战性和重要性。
发明内容
在本发明的实施例中，描述了半导体晶体管结构。该结构包括衬底和与衬底相邻的外延层。衬底和外延层都具有第一导电类型。栅极结构位于外延层上方。两者都具有第二导电类型的漏区和源区位于外延层内，使得在外延层中的源区和漏区之间形成沟道。沟道至少部分地布置在栅极结构下方。第一导电类型的体结构位于外延层内，其中体结构至少部分地形成于栅极结构下方并且在源区下方横向延伸。外延层的掺杂少于体结构。导电沟槽状馈通元件穿过所述外延层并接触所述第一导电类型衬底，穿过并接触所述第二导电类型源区。第一导电类型的槽区形成于源区下方，并且横向靠近并接触体结构，还接触沟槽状馈通元件。
在本发明的其他实施例中，描述了一种半导体晶体管结构。该结构包括衬底和与衬底相邻的外延层。衬底和外延层都具有第一导电类型。栅极结构位于外延层上方。两者都具有第二导电类型的漏区和源区位于外延层内，使得在外延层中的源区和漏区之间形成沟道。沟道至少部分地布置在栅极结构下方。漏区包括可接近漏极接触并且与栅极结构分隔开的第一区域。漏区还包括第二区域，其至少部分地位于外延层内的第一区域下方。第二区域的掺杂少于第一区域。此外，第二区域至少部分地延伸到栅极结构下方。第二区域与栅极结构的边缘内粗略对准。第一导电类型的钳位区位于第一区域下方，使得第二区域夹在第一区域和钳位区之间。
在其他实施例中，描述了用于制造半导体结构的方法。该方法包括提供衬底，以及形成与衬底相邻的外延层。衬底和外延层都具有第一导电类型。该方法包括形成位于外延层上方的栅极结构。该方法包括在外延层内形成漏区和源区，使得沟道被布置在漏区和源区之间并且至少部分地在栅极结构下方。漏区和源区具有第二导电类型。该方法包括在外延层内形成具有第一导电类型的体结构，其中该体结构至少部分地形成于栅极结构下方并且在源区下方横向延伸。该方法包括在源区下方并且横向靠近并接触体结构形成槽区，其中槽区包括第一导电类型。
在阅读了在各个附图中示出的实施例的以下详细描述之后，本领域普通技术人员将认识到本公开的各个实施例的这些和其他目的和优点。
附图说明
并入本说明书中并且形成本说明书的一部分的附图示出了本公开的实施例，其中相同的附图标记描述相同的元件，并且与描述一起用于解释本公开的原理。
图1A是根据本公开的一个实施例的功率MOSFET的截面图，该功率MOSFET包括位于源区下方的、被配置为减小跨MOSFET的p型区的横向电阻的p型槽区。
图1B是根据本公开的一个实施例的功率MOSFET的截面图，该功率MOSFET包括位于源区下方的、被配置为减小跨MOSFET的p型区的横向电阻的p型第一和第二槽区。
图1C和1D是根据本公开的实施例的功率MOSFET的截面图，每个功率MOSFET包括位于漏区和LDD(轻掺杂漏极)区下方的、被配置为钳位漏源极结两端电压的p型钳位区。
图2是根据本公开的一个实施例的、示出图1A-D所描述的功率MOSFET的器件UIS抗扰性结果的图表。
图3是根据本公开的一个实施例的、示出用于制造功率MOSFET的方法的流程图，该功率MOSFET包括位于源区下方的p型槽区，该p型槽区被配置为减小跨MOSFET的p型区的横向电阻。
图4A-I是根据本公开的实施例的、示出功率MOSFET器件的元件的截面图，该元件被配置用于各个制造阶段的改进的UIS抗扰性。
具体实施方式
现在将详细参考本公开的多个实施例，其示例在附图中示出。虽然结合这些实施例进行描述，但是应当理解的是，它们并不意图将本公开限制为这些实施例。相反，本公开意图覆盖可以包括在由所附权利要求所限定的本公开的精神和范围内的替代、修改和等同物。此外，在本公开的以下详细描述中，阐述了许多具体细节以便提供对本公开的透彻理解。然而，应当理解的是，本公开可以在没有这些具体细节的情况下被实践。在其他情况下，没有详细描述公知的方法、过程、组件和电路，以免不必要地模糊本公开的方面。
在本发明的以下详细描述中，阐述了许多具体细节以便提供对本发明的透彻理解。然而，本领域技术人员将认识到的是，可以在没有这些具体细节或采用其等同物的情况下实践本发明。在其他情况下，没有详细描述公知的方法、过程、组件和电路，以免不必要地模糊本发明的发明点。
以下详细描述的一些部分按照用于制造半导体器件的操作的过程、逻辑块、工艺和其他符号表示来介绍。这些描述和表示是半导体器件制造领域的技术人员用来将其工作的实质最有效地传达给本领域其他技术人员的手段。在本申请中，过程、逻辑块、工艺等被认为是导致预期结果的步骤或指令的自相一致的序列。这些步骤是需要物理量的物理操纵的那些步骤。然而，应当记住的是，所有这些和类似的术语将与适当的物理量相关联，并且仅仅是应用于这些量的方便标记。应当理解的是，除非特别声明，否则在以下讨论中显而易见的是，贯穿本申请的讨论使用诸如“形成”、“执行”、“提供”、“延伸”、“沉积”、“蚀刻”或类似的术语，是指半导体器件制造的动作和工艺。
如本发明所使用的，字母“n”是指n型掺杂剂，字母“p”是指p型掺杂剂。一个或多个加号“+”或一个或多个减号“-”分别用于表示相对高或相对低的掺杂剂浓度。
术语“沟道”在本发明中以可接受的方式使用。也就是说，电流在源极连接到漏极连接之间的沟道中的场效应晶体管(FET)内移动。沟道可以由n型或p型半导体材料制成；因此，FET被指定为n沟道或p沟道器件。
尽管整个申请中在n沟道器件的上下文中进行了描述，但是根据本发明的实施例并不限于此。也就是说，本发明所描述的特征可以用在p沟道器件中。因此，通过用相应的p型掺杂剂和材料替代n型掺杂剂和材料，描述可以容易地映射到p沟道器件，反之亦然。
通常在UIS事件期间，功率MOSFET器件工作于雪崩模式，其中器件的漏极到源极的p-n结被击穿，并且电感中累积的功率将被雪崩电流耗散。这个雪崩电流将最终下降到零，使得器件将恢复到正常状态并像平常一样正常工作，除非寄生双极晶体管被触发。一旦寄生双极晶体管在UIS事件期间导通，雪崩电流将非常快速地上升，器件两端的电压将下降到雪崩击穿电压以下，并且功耗将加热器件至超过其熔点，使器件物理烧坏并失效。本发明的实施例被配置为通过促进通过器件的不同雪崩电流路径，同时防止寄生双极晶体管导通来幸存于(survive)UIS事件。
图1A-D是能够改进UIS抗扰性的变化配置的功率MOSFET 100A-D的截面图。也就是说，图1A-D中的每一个包括独特特征结合其他共同特征，所述其它共同特征在UIS事件期间促进一个或多个雪崩电流路径。下面描述功率MOSFET 100A-D中所示的共同特征。图1A-D中所示的相同特征通过类似的编号来标识，并且因此在每个MOSFET 100A-D中执行类似的功能。
图1A-D中所示的功率MOSFET 100A-D是横向扩散MOSFET(LDMOS)器件。具体地，LDMOS结构将源区连接到衬底并且还连接到栅极屏蔽。此外，金属馈通(例如，钨)接触栅极屏蔽、n+源区和p+衬底。图1A-D所示的钨馈通LDMOS器件适用于低功耗的RF应用，以及改进的UIS事件抗扰性。
具体地，外延层106在重掺杂衬底102上生长。外延层106和衬底102两者都是第一导电类型。例如，如图1A-D所示，在重掺杂(例如p++)衬底102上生长p型外延层106。外延层106可以包括附加的结构、层或区。
栅极结构115位于外延层106上方。例如，栅极结构115包括WSix(硅化钨)层117和多晶硅层118。如图所示，栅极结构115形成于栅极氧化物层112上，使得多晶硅层118夹在栅极氧化物层112和硅化钨层117之间。
在外延层106内形成两者都是第二导电类型的漏区108和源区104。例如，在MOSFET100A-D中形成n+漏区108和n+源区n+104。在操作期间，在外延层106中的源区104和漏区108之间形成沟道。沟道至少部分地布置在栅极结构115下方。如图所示，外延层106和衬底层102通过反向偏置结和MOSFET沟道与漏极接触122隔离。
此外，漏区108下面的附加注入用于形成第二导电类型的轻掺杂区。例如，n型轻掺杂(n-LDD)区111从栅极结构115下方至少部分地横向延伸到漏区108。然后，在一个实施例中，LDD区111的掺杂少于第一漏区108。
如图1A-D所示，源区104与栅极结构115的边缘粗略对准。在一个实施例中，源区104在外延层106中的栅极结构115下方横向延伸。
为了改善通过沟道的电流，接下来可以执行附加的注入(未示出)以选择性地增强外延浓度。例如，在外延层106内形成第一导电类型的体结构109。外延层106的掺杂少于体结构。例如，p型体结构109至少部分地形成在外延层106内的栅极结构115下方。p型体结构109也在源区104下方延伸。
其他共同特征包括氧化物层112，其与栅极结构115下方的栅极氧化物112组合形成。也就是说，氧化物层112被形成为在侧面和上方围绕栅极结构115。
此外，栅极屏蔽114形成于氧化物层112上。如图所示，栅极屏蔽114形成于氧化物层112上。此外，栅极屏蔽114与源区104接触，并且通过钛/氮化钛(TI/TIN)阻挡层121连接到源极-衬底馈通电极120，以减小器件的栅极结构115和漏区108之间的电场。栅极屏蔽114与漏极接触122隔离。阻挡层121给馈通元件120的内部做衬里(line)。为了良好的高频性能和增强的击穿电压特性，通过将栅极屏蔽局部连接到源区104，栅极屏蔽电阻低。所示的栅极屏蔽114由重掺杂多晶硅组成。
此外，在栅极屏蔽114和氧化物层112的某些部分的上方形成TEOS层116。TEOS层116还接触TI/TIN阻挡层121。此外，在TEOS层116上形成低温氧化物(LTO)层124。如图所示，LTO层124形成于馈通元件120和TEOS层116的表面上。此外，硼磷硅酸盐玻璃(BPSG)层126形成于LTO层124上。
形成阻挡层152，其给用于漏极接触122的沟槽做衬里(line)，并且在BPSG层126的表面延伸。在一个实施例中，阻挡层152包括Ti层和TiN层。用钨填充沟槽以形成漏极接触122。
在一个实施例中，漏极接触122和源极-衬底馈通元件120用钨填充。钨提供与硅的更好的热系数匹配和在掺杂硅的形成上的更低电阻。
在阻挡层152上形成金属层130。金属层130接触漏极接触122。例如，金属层130包括单独或组合的钛层和铝层。因此，馈通元件120通过LTO层124和BPSG层126与金属层130分离。
通过向栅极结构115施加电势来操作MOSFET器件100A-D，以完成电路，该电路包括但不限于源极接触(未示出)、源区104、漏区108以及外延层106、衬底层102、漏极接触122和馈通元件120中的结构。
当切换到关断状态时，MOSFET器件100A-D产生两个雪崩电流路径——横向电流路径和垂直电流路径。图1A-B中的MOSFET 100A和100B促进不导通该器件的n-p-n结的横向电流路径，而图lC-D中的MOSFET100C和100D促进垂直电流路径。
现在参考图1A，横向电流被促进，其避开了源区104，从而避免在UIS事件期间导通寄生双极n-p-n(漏极-体-源极)晶体管。横向雪崩电流被产生，其当被适当地控制时，被配置为耗散存储在电感器中的累积的功率。通过在MOSFET 100A中的p型区的适当配置，横向雪崩电流被控制，使得寄生双极晶体管不导通。然而，如果寄生双极晶体管在漏极到源极之间导通，则横向雪崩电流将迅速尖峰化，并加热器件至超过其熔点。此外，如果寄生双极晶体管导通，在UIS事件期间电压将崩溃到击穿电压以下，并且器件将不能满足规范要求。本发明的实施例通过减小跨源区104下方的p型区的电阻来控制横向雪崩电流。
因此，功率MOSFET 100A被配置为减小体区109的电阻，或者以另一种方式减小器件的横向电阻。这促进了通过体区的受控横向电流，其不导通与源区一起形成的n-p-n结，从而在UIS事件期间的关键阶段将电压保持在击穿电压之上。具体地，通过形成额外的p型掺杂区域(例如图1A的槽区170)来实现体区109电阻的减小。
具体地，图1A是根据本公开的一个实施例的功率MOSFET 100A的截面图，其包括形成在源区下方并且横向靠近并接触体结构的第一导电类型的第一槽区170。在图1A中，第一槽区170示出为p型，并且位于源区104下方。第一p型槽区170被配置为减小MOSFET 100A的p型区(例如，p型体109、p型槽-1 170和外延层106)上的横向电阻。通过第一槽区170p型体的电阻的减小促进了从漏区108开始并沿着n-LDD区111前进、通过p型体109和第一槽区170、通过馈通元件120并离开衬底102的横向雪崩电流路径。导电的沟槽状馈通元件120穿过外延层106并接触第一导电类型的衬底102，并且还接触第二导电类型的源区104。在一个实施例中，TiTiN阻挡层121位于馈通元件120附近。注意到，雪崩电流路径避开了源区104，从而保持寄生双极晶体管的n-p-n结处于截止状态。
在一个实施例中，高掺杂的第一槽区170至少部分地形成于源区104下方，并且横向靠近并接触体结构109。此外，第一槽区170靠近并接触阻挡层121和馈通元件120。也就是说，阻挡层121和馈通元件120被视为一个结构。在一个实施例中，体结构109的掺杂少于第一槽区170。在其他实施例中，第一槽区170在源极104下方横向延伸并且进一步在栅极结构115下方延伸。
现在转到图1B，根据本公开的一个实施例，在包括具有第一导电类型的第一槽区170和第二槽区175的功率MOSFET 100B的截面图中示出了功率MOSFET的跨p型区的横向电阻的进一步减小。附加的第二槽区175进一步减小了位于源区104下方的体区109的电阻。以这种方式，第二槽区175促进了通过体区的受控横向电流，其不导通与源区形成的n-p-n结，这在UIS事件期间的关键阶段保持电压高于击穿电压。
如图1B所示，p型第二槽区175至少部分地形成在第一槽区170的下方，并且还形成为靠近并接触馈通元件120和阻挡层121。此外，第二槽区175以接触衬底102的方式形成，或换句话说，槽区175被配置为一直到达p型缓冲区或衬底层102。在一些实施例中，第一槽区170和第二槽区横向延伸到源区104下方的p型外延层106中，并且进一步延伸到栅极结构115下方。
在一个实施例中，第二槽区175的掺杂少于第一槽区170。此外，p型体结构109的掺杂少于第一槽区170和第二槽区175中的每一个。通过第一和第二槽区170和175p型体109的电阻降低，分别促进了从漏区108开始并沿着n-LDD区111前进、通过p型体109、第一槽区170、第二槽区175，通过馈通元件120并离开衬底102的横向雪崩电流路径。注意，雪崩电流避开了源区104，从而保持寄生双极晶体管的n-p-n结处于截止状态。
图1C和1D是根据本公开的实施例的功率MOSFET 100C和100D的截面图，每个功率MOSFET包括在漏区下方的第一导电类型的钳位区和被配置为钳位跨漏源极结的电压的LDD区。MOSFET 100C和100D被配置为在UIS事件期间促进垂直雪崩电流路径。更具体地，在相应MOSFET中的垂直电流路径上的电流的增加能够减少在横向雪崩电流路径中流动的电流的总量。减小横向路径中的电流进一步确保了与源区104形成的寄生双极n-p-n晶体管在UIS事件期间保持在关断状态。
在UIS事件期间，MOSFET器件中的两个位置发生具有高电场。在由箭头195指示的区域中产生的电场促进跨与栅极结构115形成的p-n结的横向雪崩电流。在由箭头190指示的区域中产生的电场促进跨在n-LDD 111和p型外延层106之间形成的p-n结的垂直雪崩电流。本发明的实施例通过增加跨由箭头190指示的区域中的p-n结的电场来促进垂直雪崩电流超过横向雪崩电流场。例如，横向雪崩电流和垂直雪崩电流之间的电流比与由箭头190和195指示的两个位置处的电场比相关。支持由箭头190指示的区域的电场比由箭头195指示的区域的电场更高，促进了比相应的横向雪崩电流更高的垂直雪崩电流。
图1C的MOSFET 100C被配置为通过在与UIS事件期间的最大垂直电场相比时降低最大横向电场来减小横向雪崩电流。这通过钳位漏极到源极的结来实现。具体来说，第一导电类型的较高掺杂钳位区180(钳位A)位于漏极下方。
如图1C所示，漏极包括可接近(accessible)漏极接触122的第一漏区108。第一漏区108与栅极结构115分隔开。漏极还包括掺杂少于第一漏区108的第二漏区(n-LDD 111)。第二漏区111位于外延层106内的第一漏区下方。第二漏区111至少部分地延伸到栅极结构115下方。
在图1C中，钳位区180为p型并位于第一漏区108下方，使得第二漏区(n-LDD 111)将第一漏区108和钳位区180分离。在一个实施例中，p型外延层106的掺杂少于p型钳位区180。钳位区180形成于外延层106内。在一个实施例中，钳位区180与第一漏区108的边缘粗略对准。因此，钳位区180被配置为相比MOSFET 100C中横向电场增加垂直电场。以这种方式，促进从第一漏区108开始并前进通过n-LDD区111、通过钳位区180、通过外延层106并到达衬底102的垂直雪崩电流路径。
图1D的MOSFET 100D还被配置为通过在与UIS事件期间的最大垂直电场相比时降低最大横向电场来减小横向雪崩电流。这也通过钳位漏极到源极结来实现。具体地，第一导电类型的较高掺杂钳位区185(钳位B)位于漏极下方。图1D的钳位区185比图1C的钳位区180更横向地延伸。也就是说，钳位区185从第一漏区108朝向外延层106中的栅极结构115更横向地延伸。
在图1D中，n型钳位区185位于第二漏区111之下。因此，第二漏区(n-LDD 111)夹在第一漏区108和钳位区185之间。钳位区185形成于外延层106内。在一个实施例中，钳位区185与第二漏区111的边缘粗略对准。钳位区185被配置为相比MOSFET 100D中的横向电场增加垂直电场。以这种方式，促进从第一漏区108开始并且前进通过n-LDD区111、通过钳位区180、通过外延层106并到达衬底102的垂直雪崩电流路径。
本发明的实施例通过减小体区电阻(例如，MOSFET 100A和100B)和/或通过促进更多的垂直雪崩电流(例如，MOSFET 100C和100D)来减小横向雪崩电流来改善UIS事件的抗扰性。本发明的实施例支持包括以下一个或多个的各种配置：槽区170、槽区175、钳位区180和钳位区185。
图2是示出根据本公开的实施例的图1A-D中描述的功率MOSFET的器件UIS抗扰性结果的图表200。如图所示，柱210示出了不包括本发明的实施例中描述的任何特征(例如，槽区和/或钳位区)的传统功率MOSFET的UIS抗扰性响应。此外，柱220示出了在本发明的一个实施例中的图1A的MOSFET 100A的UIS抗扰性响应。在柱220中示出的UIS抗扰性响应比在柱210中示出的传统功率MOSFET的UIS抗扰性响应好大约5倍。此外，柱230示出了在一个实施例中的图1B的MOSFET 100B的UIS抗扰性响应。如图所示，MOSFET 100B具有比MOSFET100A更好的UIS抗扰性响应。柱240示出了图1C的MOSFET 100C的UIS抗扰性响应，柱250示出了图1D的MOSFET 100D的UIS抗扰性响应。如图所示，MOSFET 100D的UIS抗扰性响应稍好于MOSFET 100C。然而，MOSFET 100C和100D两者的UIS抗扰性响应比传统MOSFET器件的UIS抗扰性响应好大约9倍。
图3结合图4A-I示出了根据本发明实施例的制造功率MOSFET器件的工艺。尽管公开了具体步骤，但是这些步骤仅仅是示例。也就是说，根据本发明的实施例很好地适合于执行各种其他步骤或所述步骤的变型。附图未按比例绘制，并且在附图中可以仅示出结构的某些部分以及形成那些结构的各个层。此外，可以与本文讨论的工艺和步骤一起执行额外的制造工艺和步骤。也就是说，在本文示出和描述的步骤之前、之间和/或之后可以存在多个工艺步骤。此外，步骤的顺序可以不同于本文所描述的顺序。根据本发明的实施例可以替换传统器件或工艺的某些部分或者与其结合使用，而不会显著影响外部结构、工艺和步骤。
具体地，图3是示出根据本公开的实施例的用于制造功率MOSFET的方法的流程图300A，该功率MOSFET被配置用于减小跨源区下面的体区的横向电阻，和/或增加垂直雪崩电流。具体地，流程图300A提供了功率MOSFET器件的制造，该功率MOSFET器件包括位于源区下方的槽区。此外，图4A-I是根据本公开的实施例的示出功率MOSFET器件的元件的截面图，该元件被配置用于各个制造阶段的改进的UIS抗扰性。
在310中，该方法包括提供第一导电类型的衬底。例如，对于n沟道器件，第一导电类型包括p型。此外，对于p沟道器件，第一导电类型包括n型。与图4A-I一致，提供了高掺杂p++衬底。例如，图4A是示出MOSFET制造中的初始阶段400A的截面的示意图，并且包括p++衬底402。
在320中，该方法包括形成与衬底相邻的外延层，其中外延层包括第一导电类型。例如，在重掺杂(例如，p++)衬底402上生长p型外延层406，如图4A所示。可以执行附加的p型注入(未示出)以选择性地增强外延浓度。
可以生长并剥离牺牲氧化物层(未示出)。然后生长栅极氧化物层。栅极氧化物层可以与围绕稍后形成的栅极结构的氧化物层结合。
然后，作为形成栅极结构的开端，在栅极氧化物上沉积掺杂多晶硅和WSix(硅化钨)。在一些实施例中，只有掺杂的多晶硅层被沉积，使得稍后形成的栅极结构不包括WSix。例如，栅极结构415被示出为沉积在图4A中的外延层406上。在一个实施例中，栅极结构415的形成包括光刻工艺，以在要形成栅极结构的区域上选择性地沉积光致抗蚀剂(未示出)。可以使用等离子体蚀刻步骤来去除在形成栅极结构的区域之外的WSix和掺杂的多晶硅。执行蚀刻使得保留至少一些栅极氧化物层。以这种方式，330中的方法包括形成包括了WSix层和位于外延层406之上的多晶硅层的栅极结构415。
执行附加的注入步骤以在外延层406中形成附加结构。例如，可以使用另一光刻工艺来在将要形成体区的区域外的所有区域中选择性地沉积光致抗蚀剂。具体地，在340中，该方法包括在外延层中形成第一导电类型的体结构，其中体结构至少部分地形成在栅极叠层下方并且在源区下方横向延伸。如图4B所示，p型体区409被注入。垂直和倾斜注入的组合可用于形成体区409。在一种实现方式中，p型体注入与栅极结构415的边缘自对准。在清洗晶圆之后，可以执行注入退火或体驱动。使用热氧化或氧化物间隔物形成技术在栅极结构415的侧面创建另一氧化物层。
在350中，所述方法包括在源区下方形成槽区，并且横向靠近并接触体结构，其中槽区具有第一导电类型。也就是说，在体注入之后，使用光刻工艺将光刻胶留在槽区外部。例如，图4C是示出在MOSFET制造中的中间阶段400C的截面的示意图，并且包括沉积在形成p型槽区之外的区域中的光致抗蚀剂432。光致抗蚀剂432留下比由p型体区409所占据的区域更窄的间隙。通过具有不同剂量组合的不同能量注入的几个步骤形成p型槽区。例如，第一p型槽区470被示出为更靠近外延层406的表面，并且第二p型槽区475被示出更远离外延层406的表面。在一个实施例中，第二p型槽区475的掺杂少于第一p型槽区470。
在清洗晶圆之后，可以执行注入退火或体驱动。例如，执行高温退火步骤以驱动体409更深处、以及外延层406内的槽区470和475更深处的p型注入。
在360中，可以使用光刻工艺以在将要形成n-LDD区域的区域外的所有区域中选择性地沉积光致抗蚀剂431。使用一个或多个注入来形成延伸的漏极LDD区。例如，图4D是示出功率MOSFET的制造中的中间阶段400D的截面的示意图。执行n型注入以形成n-LDD区411。
在一个实施例中，引入附加的p型注入以在剥离光刻胶431之前在n-LDD下方形成钳位区。例如，执行p型注入以形成图4D中的p型钳位区485。通过这样做，节省了一个掩模步骤以形成钳位区485。如果在漏区下方形成更小的钳位区(例如，图1C的钳位区180)，则将需要与用于形成源区和漏区的掩模步骤分开的额外的掩模步骤。
在370中，可以使用光刻工艺在要形成源区和漏区的区域外的所有区域中选择性地沉积光致抗蚀剂。例如，图4E是示出功率MOSFET的制造中的中间阶段400E的截面的示意图，并且形成源区404。作为示例，砷的n型注入可以用于形成源区404和漏区408。在清洗之后，可以执行源极注入退火。
沉积等离子体或TEOS(原硅酸四乙酯)氧化物并退火以对抗栅极屏蔽氧化物层。例如，图4F是示出功率MOSFET的制造中的中间阶段400F的截面的示意图。栅极屏蔽氧化物层412被示出为围绕栅极结构415。
在一个实施例中，使用光刻工艺在除了栅极屏蔽到源极接触区之外的区域中选择性地沉积光致抗蚀剂。例如，光致抗蚀剂434沉积在区域中以将栅极屏蔽暴露于源极接触区429，如图4F所示。然后在该区域中蚀刻栅极屏蔽氧化物412，由此暴露下面的源区404。
在一个实施例中，在清洗晶圆并使用稀释的HF(氢氟酸)后预处理之后，然后沉积掺杂多晶硅栅极屏蔽。例如，图4G是示出在制造包括多晶硅栅极屏蔽414的功率MOSFET的中间阶段400G的截面的示意图。栅极屏蔽414沉积在氧化物层412的剩余部分上和源区404上。如图所示，栅极屏蔽414与下方的源区404接触。
使用另一光刻工艺在除了MOSFET的漏区上的区域之外的栅极屏蔽上选择性地沉积光致抗蚀剂。可以使用等离子体蚀刻步骤来去除期望和暴露区域中的栅极屏蔽材料414。在清洗晶圆之后，沉积相对厚的TEOS层416。例如，图4H是示出在包括TEOS层416的功率MOSFET的制造中的中间阶段400H的截面的示意图。如图所示，TEOS层416被回蚀刻以形成平坦表面497，而不暴露栅极屏蔽材料414。
形成源极到衬底的馈通元件。例如，使用光刻工艺在将要形成源极到衬底的馈通接触的区域之外的区域中选择性地沉积光致抗蚀剂(未示出)。在一种实现方式中，可以使用两步等离子体蚀刻来蚀刻用于馈通接触的沟槽。首先，可以使用等离子体氧化物蚀刻来蚀刻外延层顶部上的TEOS层。然后，可以使用等离子体硅蚀刻来形成穿过外延层并延伸到p++衬底402中的沟槽。在清洗晶圆并使用稀释的HF后预处理之后，沟槽的上部比下部更宽，在栅极屏蔽414与馈通元件420相交的点处形成凸缘。可沉积钛(Ti)层和氮化钛(TiN)层421的保形涂层(conformal coating)以给沟槽的侧面和底部做衬里(line)，随后快速热退火以形成硅化钛接触。
然后可以将CVD钨(W)层420沉积到沟槽中以形成馈通元件420。钨层足够厚以完全填充沟槽。在一种实现方式中，钨被回蚀刻以平坦化钨，使其仅保留在馈通接触区内。然后用等离子体蚀刻来去除暴露的钛和氮化钛层而不蚀刻钨。
图4I是示出功率MOSFET的制造中的最终阶段400I的截面的示意图。如图所示，沉积低温氧化物(LTO)层(未示出)和TEOS层416。BPSG层426可以沉积在馈通元件420和TEOS层416的上表面上，并退火以稳定这些材料。
在一个实施例中，可以用光刻工艺以在漏极接触区外的区域中选择性地沉积光致抗蚀剂(未示出)。然后使用等离子体蚀刻来蚀刻掉氧化物(例如，TEOS层416)并形成沟槽。在清洗晶圆并使用稀释的HG后预处理之后，通过沉积Ti层和TiN层来形成给沟槽做衬里并在BPSG 426的表面上延伸的阻挡层。快速热退火可用于形成硅化钛接触。CVD钨层可以被沉积到足以完全填充沟槽并形成漏极接触422的厚度。栅极接触(未示出)可以以类似的方式形成。
然后形成金属层。例如，在一个实施例中，可以沉积钛层和厚的铝层。可以使用光刻工艺在金属化区域上选择性地沉积光致抗蚀剂(未示出)，并且可以使用等离子体蚀刻来去除这些区域之外的铝层和钛层。
作为结果，形成如图4I所示的LDMOS结构。图4I示出了根据本发明实施例的半导体器件的一部分。图4I所示的器件可以被配置为倒装芯片。
因此，根据本公开的实施例，描述了LDMOS结构，其包括用于减小体区中的横向电阻的一个或多个槽区，和/或在漏极下方的用于促进垂直雪崩电流路径的钳位区。
虽然前述公开阐述了使用特定框图、流程图和示例的多个实施例，但是本文中描述和/或示出的每个框图组件、流程图步骤、操作和/或组件可以利用宽范围的硬件、软件或固件(或其任何组合)配置单独地和/或共同地实现。此外，包含在其他组件内的组件的任何公开应被视为示例，因为可以实现很多架构变型以实现相同的功能。
本文描述和/或示出的工艺参数和步骤顺序仅作为示例给出，并且可以根据需要改变。例如，虽然可以以特定顺序示出或讨论本文所示和/或描述的步骤，但是这些步骤不一定需要以所示或所讨论的顺序执行。本文描述和/或示出的各种示例性方法还可以省略本文描述或示出的一个或多个步骤，或者除了那些公开的步骤之外还包括额外的步骤。
为了解释的目的，前述描述已经参考具体实施例进行了描述。然而，上述说明性讨论并不意图穷举或将本发明限于所公开的精确形式。按照上面的教导，许多修改和变型是可能的。选择和描述实施例是为了最好地解释本发明的原理及其实际应用，从而使得本领域的其他技术人员能够最好地利用本发明以及具有各种修改的可以适合于预期的特定用途的多个实施例。
因此描述了根据本公开的实施例。虽然已经在特定实施例中描述了本公开，但是应当理解的是，本公开不应被解释为受这些实施例的限制，而是根据下面的权利要求来解释。

Claims (20)

1.一种半导体晶体管结构，包括：
具有第一导电类型的衬底；
与所述衬底相邻的外延层，所述外延层具有所述第一导电类型；
位于所述外延层之上的栅极结构，
在所述外延层内的具有第二导电类型的漏区；
在所述外延层内的具有所述第二导电类型的源区；
在所述外延层中的所述源区和漏区之间形成的沟道，其中所述沟道至少部分地布置在所述栅极结构下方；
在所述外延层内的具有所述第一导电类型的体结构，所述体结构至少部分地形成于所述栅极结构下方并在所述源区下方横向延伸，其中所述外延层的掺杂少于所述体结构；
导电沟槽状馈通元件，穿过所述外延层并接触所述第一导电类型衬底，并且穿过并接触所述第二导电类型源区；和
具有所述第一导电类型的槽区，形成于所述源区下方且横向靠近并接触所述体结构，其中所述槽区与所述沟槽状馈通元件接触。
2.根据权利要求1所述的半导体晶体管结构，其中所述槽区包括：
第一槽区，至少部分地形成于所述源区下方且横向靠近并接触所述体结构，其中所述体结构的掺杂少于所述第一槽区。
3.根据权利要求2所述的半导体晶体管结构，其中所述槽区包括：
第二槽区，至少部分地形成于所述第一槽区下方，其中所述第二槽区的掺杂少于所述第一槽区。
4.根据权利要求1所述的半导体晶体管结构，其中所述漏区包括：
第一区域，与漏极接触可接近并与所述栅极结构分隔开；和
第二区域，被轻掺杂并且至少部分地位于所述外延层内的所述第一区域下方，其中所述第二区域至少部分地延伸到所述栅极结构下方，其中所述第二区域的掺杂少于所述第一区域，其中所述第二区域与所述栅极结构的边缘粗略对准。
5.根据权利要求1所述的半导体晶体管结构，其中所述源区与所述栅极结构的边缘粗略对准。
6.根据权利要求1所述的半导体晶体管结构，其中所述栅极结构包括：
栅极氧化物层；
硅化钨层；和
夹在所述栅极氧化物层和所述硅化钨层之间的栅极多晶硅。
7.根据权利要求1所述的半导体晶体管结构，其中所述第一导电类型包括p型，并且其中所述第二导电类型包括n型。
8.一种半导体晶体管结构，包括：
具有第一导电类型的衬底；
与所述衬底相邻的外延层，所述外延层具有所述第一导电类型；
靠近并位于所述外延层之上的栅极结构，
在所述外延层内的具有第二导电类型的漏区；
在所述外延层内的具有所述第二导电类型的源区；
在所述外延层中的所述源区和漏区之间形成的沟道，其中，所述沟道至少部分地布置在所述栅极结构下方；
在所述外延层内的具有所述第一导电类型的体结构，所述体结构至少部分地形成于所述栅极结构下方并在所述源区下方横向延伸，其中所述外延层的掺杂少于所述体结构；
导电沟槽状馈通元件，穿过所述外延层并接触所述第一导电类型衬底，并且穿过并接触所述第二导电类型源区，并且穿过并接触形成于所述源区下方并且横向靠近并接触所述体结构的具有所述第一导电类型的槽区；
其中所述漏区包括与漏极接触可接近并与所述栅极结构分隔开的第一区域，和至少部分地位于所述外延层内的所述第一区域下方的、比所述第一区域掺杂更少的第二区域，使得所述第二区域至少部分地延伸至所述栅极结构下方，其中所述第二区域与所述栅极结构的边缘粗略对准；和
位于所述第一区域下方的具有第一导电类型的钳位区，使得所述第二区域将所述第一区域和所述钳位区分离开。
9.根据权利要求8所述的半导体晶体管结构，其中所述钳位区与所述第一区域的边缘粗略对准。
10.根据权利要求8所述的半导体晶体管结构，其中所述钳位区与轻掺杂的所述第二区域的边缘内粗略对准。
11.根据权利要求8所述的半导体晶体管结构，其中所述槽区包括：
第一槽区，至少部分地形成于所述源区下方，并且横向靠近并接触所述体结构，其中所述体结构的掺杂少于所述第一槽区。
12.根据权利要求11所述的半导体晶体管结构，其中所述槽区包括：
第二槽区，至少部分地形成于所述第一槽区下方，其中所述第二槽区的掺杂少于所述第一槽区。
13.根据权利要求8所述的半导体晶体管结构，其中所述第一导电类型包括p型，并且其中所述第二导电类型包括n型。
14.一种用于制造半导体晶体管结构的方法，包括：
提供具有第一导电类型的衬底；
形成与所述衬底相邻的外延层，其中所述外延层包括所述第一导电类型；
形成位于所述外延层之上的栅极结构；
在所述外延层内形成漏区，其中所述漏区包括第二导电类型；
在所述外延层内形成源区，其中所述源区包括所述第二导电类型，其中在所述源区和所述漏区之间的所述外延层中形成沟道，其中所述沟道至少部分地位于所述栅极结构下方；
在所述外延层内形成具有所述第一导电类型的体结构，其中所述体结构至少部分地形成于所述栅极结构下方并且在所述源区下方横向延伸；
在所述源区下方并且横向靠近并接触所述体结构形成槽区，其中所述槽区包括所述第一导电类型。和
形成导电沟槽状馈通元件，所述导电沟槽状馈通元件穿过所述外延层并接触所述第一导电类型衬底，并且穿过并接触所述第二导电类型源区；并且穿过并接触形成于所述源区下方并且横向靠近并接触所述体结构的具有所述第一导电类型的所述槽区。
15.根据权利要求14所述的方法，其中所述形成槽区还包括：
形成至少部分地在所述源区下方且横向靠近并接触所述体结构的第一槽区，其中所述体结构的掺杂少于所述第一槽区。
16.根据权利要求15所述的方法，其中所述形成槽区还包括：
形成至少部分地在所述第一槽区下方的第二槽区，其中所述第二槽区的掺杂少于所述第一槽区。
17.根据权利要求14所述的方法，其中所述形成漏区包括：
形成位于漏极接触下方并与所述栅极结构分隔开的第一区域；以及
形成轻掺杂的且位于所述外延层内的所述第一区域下方的第二区域，其中所述第二区域至少部分地延伸到所述栅极结构下方，其中所述第二区域的掺杂少于所述第一区域。
18.根据权利要求17所述的方法，还包括：
形成位于所述第一区域下方的具有所述第一导电类型的钳位区，使得所述第二区域将所述第一区域和所述钳位区分离开。
19.根据权利要求18所述的方法，其中所述形成钳位区还包括：
将所述钳位区向所述源区延伸，使得远离所述漏区的所述钳位区的边缘位于由与所述第一区域的第一边缘的粗略对准以及与轻掺杂的所述第二区域的第二边缘的第二粗略对准所限定的所述外延层中的区域内。
20.根据权利要求14所述的方法，其中所述第一导电类型包括p型，并且其中所述第二导电类型包括n型。
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