CN106469650B - 晶片的加工方法和电子器件 - Google Patents
晶片的加工方法和电子器件 Download PDFInfo
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- 238000003672 processing method Methods 0.000 title description 8
- 238000000227 grinding Methods 0.000 claims abstract description 121
- 238000005498 polishing Methods 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 45
- 238000012545 processing Methods 0.000 claims abstract description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 14
- 238000005247 gettering Methods 0.000 abstract description 27
- 230000000694 effects Effects 0.000 abstract description 26
- 235000012431 wafers Nutrition 0.000 description 118
- 239000007789 gas Substances 0.000 description 55
- 239000010410 layer Substances 0.000 description 21
- 230000001681 protective effect Effects 0.000 description 19
- 230000015572 biosynthetic process Effects 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 238000005520 cutting process Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000004575 stone Substances 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 238000005452 bending Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000007676 flexural strength test Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000012086 standard solution Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000003522 acrylic cement Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920000915 polyvinyl chloride Polymers 0.000 description 1
- 239000004800 polyvinyl chloride Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 125000003718 tetrahydrofuranyl group Chemical group 0.000 description 1
- 238000004876 x-ray fluorescence Methods 0.000 description 1
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- H01L21/02008—Multistep processes
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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Abstract
提供晶片的加工方法和电子器件。能够确保构成晶片的器件的抗折强度,并且还产生充分的吸杂效果。晶片的加工方法对晶片的背面进行加工,该晶片在正面上通过交叉的多条分割预定线划分而形成有多个器件,该晶片的加工方法具有如下的工序:背面磨削工序,对在正面上形成有器件的晶片的背面进行磨削而使该晶片薄化到规定的厚度;背面研磨工序,对磨削后的晶片的背面进行研磨而去除磨削畸变;以及DLC成膜工序,在研磨后的晶片的背面上成膜出类金刚石碳(DLC)膜。
Description
技术领域
本发明涉及晶片的加工方法和电子器件,能够充分地得到器件的抗折强度和吸杂效果。
背景技术
在晶片的正面上由分割预定线划分而形成有IC、LSI等器件,对于该晶片,在对其背面进行磨削而形成为规定的厚度之后,通过切割装置分割成一个个的器件芯片,分割出的器件芯片应用于各种电子设备等。
并且,在对晶片的背面进行磨削而将晶片形成为100μm以下的厚度之后,层叠晶片并将上下的器件的端子彼此连结而作为整体使其功能提升的被称为MCP(Multi ChipPackage:多芯片封装)的封装器件也已实用化(例如参照专利文献1)。
器件形成于硅基板的正面,在对背面进行磨削而形成为规定的厚度之后,进行切割而将器件分割成一个个的器件芯片。但是,存在当对晶片的背面进行磨削时在该背面上残留磨削应变而降低器件的抗折强度这样的问题。因此,提出如下的技术:使用研磨垫对磨削后的背面进行研磨而去除磨削应变,提高器件的抗折强度(例如参照专利文献2)。并且,通过等离子CVD法或对硅进行氮化的方法形成硅氮化膜,形成捕获重金属的吸杂层(例如参照专利文献3)。
专利文献1:日本特开2009-26992号公报
专利文献2:日本特开2006-80329号公报
专利文献3:日本特开2009-117653号公报
但是,要想通过CVD法成膜出硅氮化膜需要花费时间,生产效率不高。并且,在对基板的硅进行氮化而得到硅氮化膜的方法中,在硅中产生应力,容易产生翘曲。
发明内容
本发明是鉴于这样的问题而完成的,其目的在于提供一种晶片的加工方法和电子器件,确保构成晶片的器件的抗折强度,并且还能够产生充分的吸杂效果。
本发明的晶片的加工方法对晶片的背面进行加工,该晶片在正面上通过交叉的多条分割预定线划分而形成有多个器件,其中,该晶片的加工方法具有如下的工序:背面磨削工序,对在正面上形成有器件的晶片的背面进行磨削而使该晶片薄化到规定的厚度;背面研磨工序,对磨削后的晶片的背面进行研磨而去除磨削畸变;以及类金刚石碳成膜工序,在研磨后的晶片的背面上成膜出类金刚石碳膜。在该晶片的加工方法中,可以使类金刚石碳膜的厚度为10~100nm。
并且,本发明的电子器件构成为在背面上形成有类金刚石碳膜。
在本发明的晶片的加工方法中,由于在晶片的背面上成膜出类金刚石碳膜,因此能够确保构成晶片的器件的抗折强度,并且还能够产生充分的吸杂效果。并且,本发明的电子器件由于在背面上形成有类金刚石碳膜,因此能够确保抗折强度,并且还能够产生充分的吸杂效果。
附图说明
图1是示出晶片和正面保护带的分解立体图。
图2是示出背面磨削工序的立体图。
图3是示出背面研磨工序的立体图。
图4是示出成膜装置的例子的剖视图。
图5是示出第1实施方式的改质层形成工序的剖视图。
图6是示出第1实施方式的背面磨削工序的剖视图。
图7是示出第1实施方式的背面研磨工序的剖视图。
图8是示出第1实施方式的DLC成膜工序的剖视图。
图9是示出第1实施方式的扩展工序的剖视图。
图10是示出第1实施方式的背面磨削工序的剖视图。
图11是示出第2实施方式的改质层形成工序的剖视图。
图12是示出第2实施方式的背面研磨工序的剖视图。
图13是示出第2实施方式的扩展工序的剖视图。
图14是示出第2实施方式的DLC成膜工序的剖视图。
图15是示出由激光束照射而进行的正面槽形成工序的剖视图。
图16是示出由切削而进行的正面槽形成工序的剖视图。
图17是示出第3实施方式的背面研磨工序的剖视图。
图18是示出第3实施方式的扩展工序的剖视图。
图19是示出第3实施方式的DLC成膜工序的剖视图。
图20是示出试验对象的晶片的结构的俯视图。
图21是示出抗折强度试验的状态的剖视图。
标号说明
WF:晶片;W1:正面;L:分割预定线;D:器件;W2、W2′、W2″:背面;T:保护带;F:框架;1~61:芯片(器件);7:磨削装置;70:卡盘工作台;71:磨削单元;72:旋转轴;73:固定件;74:磨削轮;75:基台;76:磨削磨具;8:研磨装置;80:卡盘工作台;81:研磨单元;82:旋转轴;83:固定件;84:研磨轮;85:基台;86:研磨垫;9:成膜装置;90:保持工作台;900:支承部件;901:电极;91:气体喷出头;910:气体扩散空间;911:气体导入口;912:气体排出口;913:气体配管;92:腔室;93:气体提供部;94:匹配器;95:高频电源;96:排气管;97:排气装置;98:控制部;110:孔;111:基台;112:球状压子。
具体实施方式
图1所示的晶片WF是示出本发明的应用对象的晶片的一例,该晶片WF在由正面W1的分割预定线L划分出的区域中形成有多个电子器件D。以下,关于在对该晶片WF的背面W2实施了磨削加工和研磨加工之后,在所研磨的面上成膜出类金刚石碳(DLC)膜的方法进行说明。
(1)背面磨削工序
首先,在晶片WF的正面W1上粘贴保护带T。该保护带T例如在由聚氯乙烯等构成的片状基材的正面上涂布丙烯酸树脂系的粘接层而构成,通过在晶片WF的正面W1上粘贴该粘接层而保护正面W1。
接着,成为保护带T侧被吸引保持于图2所示的磨削装置7的卡盘工作台70而晶片WF的背面W2露出的状态。在该磨削装置7中具有磨削单元71,该磨削单元71在旋转轴72的下端的固定件73上装配磨削轮74而构成,磨削轮74在基台75的下表面上将多个磨削磨具76固定安装成圆环状而构成。磨削磨具76例如利用粘接剂固定金刚石磨粒而构成。
在磨削装置7中,使卡盘工作台70在例如A1方向上旋转,并且使旋转轴72在A2方向上旋转,并使磨削单元71下降,使旋转的磨削磨具76与晶片WF的背面W2接触,而对背面W2进行磨削。在磨削中,使磨削磨具76的旋转轨迹穿过晶片WF的中心。并且,当将晶片WF形成为规定的厚度时,使磨削单元71上升而结束磨削。
(2)背面研磨工序
接着,将背面W2被研磨且在正面W1粘贴有保护带T的晶片WF搬送到图3所示的研磨装置8。该研磨装置8具有:能够旋转的卡盘工作台80,其对晶片WF进行保持;以及研磨单元81,其在旋转轴82的下端的固定件83上装配研磨轮84而构成。研磨轮84在基台85的下表面固定安装有圆形的研磨垫86而构成。研磨垫86由例如无纺布、泡沫氨酯树脂等构成,且形成为直径比晶片W大。
晶片WF的保护带T侧被吸引保持在卡盘工作台80上,磨削后的背面W2′露出。并且,使卡盘工作台80在例如A3方向上旋转,并且使旋转轴82在A4方向上旋转,并使研磨单元81下降而使旋转的研磨垫86与晶片WF的背面W2′的整个面接触,从而对该背面W2′进行研磨。在研磨时,研磨垫86的下表面整个面与背面W2′接触。并且,当去除了晶片WF′的背面W2′的磨削畸变时,使研磨单元81上升而结束研磨。
另外,也可以使用具有图2所示的磨削单元71和图3所示的研磨单元81的装置,利用1个装置实施背面磨削工序和背面研磨工序。并且,背面研磨工序不仅可以是由研磨垫进行的研磨,例如也可以借助由高目数磨具进行的磨削、蚀刻等来进行。
(3)DLC成膜工序
通过研磨工序而去除了背面的磨削畸变的晶片WF被搬送到例如图4所示的成膜装置9。该成膜装置9具有:保持工作台90,其对晶片WF进行保持;气体喷出头91,其喷出气体;以及腔室92,其将保持工作台90和气体喷出头91收纳在内部。
通过支承部件900从下方支承保持工作台90。在保持工作台90的内部配设有电极901,该电极901接地。
在气体喷出头91的内部设置有气体扩散空间910,气体扩散空间910的上部与气体导入口911连通,气体扩散空间910的下部与气体排出口912连通。气体排出口912的下端朝向保持工作台90侧开口。
气体导入口911经由气体配管913连接有气体提供部93。气体提供部93分别蓄积有成膜气体和稀有气体。
气体喷出头91经由匹配器94连接有高频电源95。通过从高频电源95经由匹配器94对气体喷出头91提供高频电力,而能够将从气体排出口912排出的气体等离子化。
在腔室92的下部连接有排气管96,该排气管96连接有排气装置97。通过使该排气装置97进行动作而能够将腔室92的内部减压到规定的真空度。
在腔室92的侧部设置有用于进行晶片WF的搬入搬出的搬入搬出口920以及对该搬入搬出口920进行开闭的闸阀921。
成膜装置9具有控制部98,在控制部98的控制下,对各气体的排出量及时间、高频电力等条件进行控制。
在DLC成膜工序中,打开闸阀921,从搬入搬出口920搬入晶片WF。并且,通过排气装置97对腔室92内进行排气,使腔室92内的压力成为例如0.10~0.15Pa,并且使蓄积在气体提供部93中的成膜气体经由气体配管913和气体导入口911从气体排出部912喷出。作为成膜气体例如使用甲苯(C7H8)。除了甲苯(C7H8),例如也可以将C2H2、C4H6、C6H6等烃气体作为成膜气体。并且,也可以将C4H4O、C4H8O等包含碳、氢和氧的气体(CxHyOz)用作成膜气体。
将成膜气体导入至腔室92内,并且使保持工作台90的温度为例如带T不发生变形的温度即70℃以下,从高频电源95对气体喷出头91施加高频电力(例如RF高频率:13.56MHz(平行平板型)、RF输出:1kW),从而在气体喷出头91与保持工作台90之间产生高频电场,使成膜气体等离子化。于是,在晶片WF的研磨后的背面W2″上成膜出作为无定形碳的一种的类金刚石碳(DLC)。并且,通过以规定的时间进行该成膜,而成膜出规定的厚度的无定形碳膜。
在成膜过程中,除了成膜气体之外,还可以从气体提供部93导入作为稀释气体的Ar等稀有气体。稀有气体的等离子对晶片WF的背面W2″进行溅蚀(Sputtering),而能够将附着于晶片背面的有机物等去除,清洁背面W2″。并且,由于He等稀有气体有助于成膜气体的等离子化,因此成膜气体的等离子化得到促进。作为稀有气体例如可以根据用途而使用氦气(He)、氩气(Ar)等。另外,稀有气体向腔室92的导入也可以在成膜气体的导入前进行。
当作为成膜气体使用包含氧的气体时,由于氧等离子将成膜后的DLC膜的薄弱部分去除并且推进成膜,因此能够形成更致密的DLC膜。并且,通过控制包含在成膜气体中的氢的量,而能够控制DLC膜的硬度。
然后,可以借助切削刀具或激光照射等公知的方法,沿着图1所示的分割预定线L分割成一个个的芯片。在该情况下,除了基于切削刀具或照射激光而进行的全切割的切断外,还可以进行半切割、或者在沿着分割预定线L照射激光而形成改质层之后对晶片施加外力而分割成一个个的芯片。
另外,也可以在将晶片WF分割成一个个的芯片之后,在一个个的芯片的背面成膜出DLC膜。作为该方法例如存在以下所示的第1实施方式至第3实施方式。
[第1实施方式]
(1-1)改质层形成工序
最初,如图5所示,在晶片WF的正面W1粘贴保护带T。并且,在激光加工装置200的保持工作台201上对保护带T侧进行保持,使晶片W的背面W2露出。
接着,从激光照射头202朝向晶片WF的背面W2照射对于晶片WF具有透过性的波长的激光束203,并沿着图1所示的分割预定线L在内部聚光,形成改质层204。改质层204形成于通过之后的背面磨削而被去除的部分。例如,在晶片W的最终的完工厚度为H的情况下,改质层204的下端与从正面W1起以H的量位于上方的位置相比还位于上方。这样,沿着所有的分割预定线L在晶片WF的内部形成改质层204。
(1-2)背面磨削工序
接着,如图6所示,在图2所示的磨削装置7的卡盘工作台70上对保护带T侧进行保持。并且,使卡盘工作台70在A1方向上旋转,并且一边使磨削轮74在A2方向上旋转一边使磨削单元71下降,使旋转的磨削磨具76与晶片WF的背面W2接触而进行磨削。于是,从改质层204朝向正面W1形成裂痕205而沿着分割预定线L将晶片WF分割成一个个的芯片C。并且,当磨削到背面W2′而将晶片W(芯片C)形成为厚度H时,使磨削单元71上升而结束磨削。
(1-3)背面研磨工序
在背面磨削工序结束后,如图7所示,在研磨装置8的卡盘工作台80上对保护带T侧进行保持。并且,使卡盘工作台80在A3方向上旋转,并且一边使研磨轮84在A4方向上旋转一边使研磨单元81下降,对芯片C的背面C2进行研磨而去除磨削畸变。
另外,当在背面磨削工序中未形成裂痕205的情况下,有时在本工序中形成裂痕而将晶片WF分割成一个个的芯片C。并且,背面研磨工序不仅限于由研磨垫进行的研磨,例如也可以通过由高目数磨具进行的磨削、蚀刻等而进行。
(1-4)DLC成膜工序
接着,如图8所示,在一个个的芯片C的研磨后的背面C2′上成膜出DLC膜100。成膜的方法与在图4所示的晶片WF的背面W2″上进行成膜的方法相同。由于通过背面磨削工序去除了芯片侧壁的改质层、以及/或者通过研磨工序去除结晶畸变,侧壁或背面侧的吸杂效果会消失,因此成膜出DLC膜而产生吸杂效果是有效的。
并且,在本工序中,与在晶片W的背面上进行成膜的情况不同,由于在相邻的芯片C之间存在间隔,因此在芯片C的侧面C3上也覆盖有DLC膜100。图5和图6所示的改质层204具有吸杂效果,但改质层204通过背面磨削工序被去除而失去吸杂效果。但是,通过本工序在侧面C3上也覆盖DLC膜100,从而能够使各芯片C产生吸杂效果。
另外,当在本实施方式的背面磨削工序或者背面研磨工序中,图6所示的裂痕205未到达正面W1而未将晶片W分割成一个个的芯片C的情况下,在背面磨削工序之后或者背面研磨工序之后,实施图9所示的扩展工序。在扩展工序中,如图9所示,在扩展带T1上粘贴磨削后的背面W2′或者研磨后的背面W2″,在扩展带T1的外周部粘贴框架F。并且,在扩展装置300的保持台301上对扩展带T1侧进行保持,并且将框架F载置在框架支承台302上并进行固定。该框架支承台302固定于活塞303,气缸304使活塞303升降从而该框架支承台302升降。
当使固定了框架F的框架支承台302下降时,形成分割槽206而分割成一个个的芯片C。另外,在即使进行扩展也未被分割的情况下,也可以返回到背面磨削工序或者背面研磨工序,然后再次实施扩展工序。
[第2实施方式]
(2-1)背面磨削工序
最初,如图10所示,在晶片WF的正面W1上粘贴保护带T,在图2所示的磨削装置7的卡盘工作台70上对保护带T侧进行保持。并且,使卡盘工作台70在A1方向上旋转,并且一边使磨削轮74在A2方向上旋转一边使磨削单元71下降,使旋转的磨削磨具76与晶片WF的背面W2接触而进行磨削。并且,当磨削到背面W2′而将晶片WF形成为规定的厚度H时,使磨削单元71上升而结束磨削。
(2-2)改质层形成工序
接着,如图11所示,在激光加工装置200的保持工作台201上对保护带T侧进行保持,使晶片W的被磨削后的背面W2′露出。并且,从激光照射头202朝向晶片WF的背面W2′照射对于晶片WF具有透过性的波长的激光束203,沿着图1所示的分割预定线L聚光到内部,形成改质层207。这样,沿着所有的分割预定线L在晶片WF的内部形成改质层207。
(2-3)背面研磨工序
接着,如图12所示,在研磨装置8的卡盘工作台80上对保护带T侧进行保持。并且,使卡盘工作台80在A3方向上旋转,并且一边使研磨轮84在A4方向上旋转一边使研磨单元81下降,对晶片W的背面磨削后的背面W2′进行研磨而去除磨削畸变。当通过研磨而以改质层207为起点形成裂痕208时,被分割成一个个的芯片Ca。另外,如果改质层207形成于能够在背面研磨工序中被去除的位置,则由于在一个个的芯片Ca中不会残留改质层207,因此不会导致抗折强度的降低。并且,背面研磨工序不仅限于由研磨垫进行的研磨,例如也可以是由高目数磨具进行的磨削、蚀刻等。
(2-4)扩展工序
当在背面研磨工序中未形成裂痕208而未被分割成芯片Ca的情况下,实施图13所示的扩展工序。在扩展工序中,将研磨后的背面W2″粘贴于扩展带T2,在扩展带T2的外周部粘贴框架F。并且,在扩展装置300的保持台301上对扩展带T2侧进行保持,并且将框架F载置在框架支承台302上并进行固定。该框架支承台302固定于活塞303,气缸304使活塞303升降从而该框架支承台302升降。
当使固定有框架F的框架支承台302下降时,以改质层207为起点形成分割槽209而分割成一个个的芯片Ca。另外,在即使进行扩展也未被分割的情况下,也可以返回背面研磨工序进行背面研磨,然后再次实施扩展工序。
(2-5)DLC成膜工序
接着,如图14所示,在一个个的芯片Ca的研磨后的背面Ca2上成膜出DLC膜101。成膜的方法与在图4所示的晶片WF的背面W2″上进行成膜的方法相同。由于通过背面研磨工序去除结晶畸变,会消除背面侧的吸杂效果,因此成膜出DLC膜而产生吸杂效果是有效的。
并且,在本工序中,由于在相邻的芯片Ca之间存在间隔,因此在芯片Ca的侧面C4上也覆盖有DLC膜101。由于在侧面C4上也覆盖有DLC膜101,因此能够提高各芯片Ca的吸杂效果。
[第3实施方式]
(3-1)背面磨削工序
最初,如图10所示,在晶片WF的正面W1上粘贴保护带T,在图2所示的磨削装置7的卡盘工作台70上对保护带T侧进行保持。并且,使卡盘工作台70在A1方向上旋转,并且一边使磨削轮74在A2方向上旋转一边使磨削单元71下降,使旋转的磨削磨具76与晶片WF的背面W2接触而进行磨削。并且,当磨削到背面W2′而将晶片WF形成为规定的厚度H时,使磨削单元71上升而结束磨削。
(3-2)正面槽形成工序
接着,如图15所示,从正面W1剥离保护带T并且将带T3粘贴于背面W2′,在激光加工装置200的保持工作台201上对带T3侧进行保持,使晶片W的正面W1露出。并且,从激光照射头202朝向晶片WF的背面W2′照射相对于晶片WF具有吸收性的波长的激光束210,沿着图1所示的分割预定线L聚光在正面W1,在正面W1上形成加工槽211。这样,沿着所有的分割预定线L在晶片WF的正面W1上形成加工槽211。
在本工序中也可以使用图16所示的切削装置400。在该情况下,在切削装置400的卡盘工作台401上对带T3侧进行保持。并且,使装配于主轴402的切削刀具403一边旋转一边下降,并沿着分割预定线L切入。此时,通过将切入深度控制为规定的深度以便切削刀具403不会贯穿晶片WF,而在正面W1上形成加工槽404。这样,沿着所有的分割预定线L切入切削刀具403而形成加工槽404。
另外,作为在上述激光加工装置200或者切削装置400中粘贴于背面W2′的带T3也可以使用切割带,在切割带的外周部粘贴环状的框架,由此通过框架隔着切割带支承晶片WF。
(3-3)背面研磨工序
接着,如图17所示,从背面W2′剥离带T3,并且在正面W1上粘贴保护带T,在研磨装置8的卡盘工作台80上对保护带T侧进行保持。并且,使卡盘工作台80在A3方向上旋转,并且一边使研磨轮84在A4方向上旋转一边使研磨单元81下降,对晶片W的背面磨削后的背面W2′进行研磨而去除磨削畸变。如果通过研磨以加工槽211(404)为起点而形成裂痕212,则被分割成一个个的芯片Cb。另外,背面研磨工序不仅限于由研磨垫进行的研磨,例如也可以是由高目数磨具进行的磨削、蚀刻等。
(3-4)扩展工序
当在背面研磨工序中未将晶片WF分割成一个个的芯片Cb的情况下,进行扩展工序。在本工序中,如图18所示,在研磨后的背面W2″上粘贴扩展带T4,在扩展带T4的外周部粘贴框架F。并且,在扩展装置300的保持台301上保持扩展带T2侧,并且将框架F载置于框架支承台并进行固定。该框架支承台302固定于活塞303,气缸304使活塞303升降而该该框架支承台302升降。
当使固定了框架F的框架支承台302下降时,以加工槽211(404)为起点形成分割槽213而分割成一个个的芯片Cb。另外,在即使扩展也无法分割的情况下,也可以返回背面研磨工序进行背面研磨,然后再次实施扩展工序。
(5)DLC成膜工序
接着,如图19所示,在一个个的芯片Cb的研磨后的背面Cb2上成膜出DLC膜102。成膜的方法与在图4所示的晶片WF的背面W2″上进行成膜的方法相同。由于在相邻的芯片Cb之间存在间隔,因此在芯片Cb的侧面C5上也覆盖有DLC膜102。由于在侧面C5上也覆盖有DLC膜102,因此能够提高各芯片Cb的吸杂效果。
另外,在第3实施方式中,背面磨削工序和正面槽形成工序也可以颠倒次序地实施。
【实施例1】
进行用于求出DLC膜的膜厚的试验,该DLC膜用于适当地确保器件的吸杂效果。具体而言,在经过了上述背面磨削工序、背面研磨工序的多个晶片的背面上,分别成膜出膜厚不同的DLC膜,利用铜强制性地污染各个晶片,并进行吸杂效果的测定,对DLC膜的膜厚与吸杂效果的关系进行考察。并且,与吸杂效果的测定一同进行抗折强度试验。在本试验中,晶片使用如下的规格。
晶片:硅晶片
晶片的直径:8英寸
晶片的厚度(器件的厚度):200μm(背面研磨后)
器件尺寸:10mm×10mm
每1张晶片的器件数:61(参照图20)
(1)吸杂效果试验
(A)DLC成膜步骤
准备3张对背面进行了磨削及研磨的晶片,通过所述DLC成膜工序,在该3张晶片的背面上分别覆盖膜厚为100[nm]、50[nm]、10[nm]的硅氮化膜。并且,对于这些所有的晶片,分别执行以下的(A)~(D)的步骤。
(B)强制污染步骤
对于上述所有的晶片,在成膜有DLC的面上,对直径8英寸的晶片的该背面的面积涂布1.0×1013[atoms/cm2]的Cu标准液(硫酸铜),对所有器件进行铜的强制污染。
(C)加热步骤
对于所有的晶片,在使Cu标准液干燥之后,在350℃的温度下加热3小时,使晶片内的铜原子处于容易扩散的状态。
(D)测定步骤
将所有的晶片冷却,对于各个晶片,使用TXRF(全反射X射线荧光分析仪:Tecnos株式会社制造)对涂布了Cu标准液的背面的反面(正面)的铜原子量进行测定。详细而言,将晶片的正面分割成按照15mm×15mm划分的区域,对于各个区域按照每一个部位测定铜原子量,求出平均值和最大值。另外,在强制污染步骤前,也通过相同的方法来测定铜原子的检测量。
在本步骤中,当在晶片的正面上检测出铜原子的情况下,能够判断为铜原子扩散至内部,吸杂效果不存在或者不充分。另一方面,当在器件的正面上未检测出铜原子的情况下,能够判断为铜原子被硅氮化膜侧捕捉,存在充分的吸杂效果。试验结果如以下的表1所示。另外,将用于对是否检测出铜原子进行判断的阈值设为0.5×1010[atoms/cm2]。
表1
晶片号码 | 膜厚[mm] | RF频率[MHz] | 成膜时间 | 吸杂效果 |
1 | 100 | 13.56 | 2分钟 | ○ |
2 | 50 | 13.56 | 1分钟 | ○ |
3 | 10 | 13.56 | 12秒 | ○ |
从上述表1的试验结果可知,在强制污染后,在任意的晶片中,铜原子的检测量小于阈值,确认出在形成了DLC膜的晶片上存在吸杂效果。
(2)抗折强度试验
如图20所示,晶片WF由芯片编号1~61的61个芯片构成。对于这样的晶片WF,在执行了上述DLC成膜步骤之后,分割成一个个的芯片,对于每个芯片测定抗折强度。另外,在DLC成膜步骤中,将膜厚设为100[nm]、50[nm]、10[nm]。并且,对于只实施了背面磨削工序的晶片以及实施了背面磨削工序和背面研磨工序的晶片测定抗折强度。抗折强度测定的具体的方法如下。
(E)抗折强度测定步骤
使用株式会社岛津制作所制造的压缩试验机(AGI-1kN9),测定各芯片的抗折强度。具体的测定方法如下。
(E)-1
如图21所示,在中央部形成有圆形的孔110的基台111上分别载置各芯片1~61。此时,使覆盖在背面上的DLC膜朝下。
(E)-2
通过具有球面的球状压子112朝向下方(箭头A5方向)按压于各芯片1~61。
(E)-3
在各器件1~61裂开的瞬间,使用以下的式(1)来计算抗折强度δ。
【式1】
在上述式(1)中,各变量的含义和值如下(参照图21)。
W:破坏强度(在测定时得到的值)[kgf]
h:器件的厚度=200[μm]
v:泊松比(硅)=0.28
a:孔的半径=3.5[mm]
a0:器件的半径=5[mm]
v2:泊松比(球状压子)=0.3
并且,在上述式(1)中,a1是球状压子112与器件的接触半径,使用以下的式(2)进行计算。
【式2】
在上述式(2)中,各变量的含义和值如下。
ε1:杨氏模量(硅)=1.31×105[MPa]
ε2:杨氏模量(球状压子)=2.01×104[MPa]
r:球状压子的半径=3.0[mm]
对于所有的芯片进行基于上述式(1)的抗折强度的计算,按照各膜厚求出抗折强度的平均值。其结果如以下的表2。
表2
晶片号码 | 膜厚[nm] | 抗折强度[MPa] |
1 | 100 | 1195 |
2 | 50 | 1271 |
3 | 10 | 1177 |
4 | 0(磨削+研磨) | 1160 |
5 | 0(只磨削) | 552 |
如表2所示,对于所有成膜有DLC的晶片,确认出它们的抗折强度大于1000[MPa],能够得到与施加磨削+研磨(背面磨削工序和背面研磨工序)且未成膜出DLC的4号的晶片同等以上的抗折强度。
(3)关于最适合的膜厚
通过表1所示的吸杂效果试验的结果,像已经描述的那样,通过使硅氮化膜的膜厚为10[nm]以上,而能够确保充分的吸杂效果。另一方面,从表2的结果可知,若将DLC膜的膜厚设为10~100[nm],能够确保充分的抗折强度。因此,确认出为了能够得到充分的吸杂效果并且使抗折强度也充分,可以将DLC膜的膜厚设为10~100[nm]。
Claims (3)
1.一种晶片的加工方法,对晶片的背面进行加工,该晶片在正面上通过交叉的多条分割预定线划分而形成有多个器件,其中,该晶片的加工方法具有如下的工序:
改质层形成工序,沿着多条分割预定线在该晶片的内部形成用于分割成各个芯片的改质层;
背面磨削工序,对在正面上形成有器件的晶片的背面进行磨削而使该晶片薄化到规定的厚度,并且将在该改质层形成工序中形成的该改质层去除;
背面研磨工序,对磨削后的晶片的背面进行研磨而去除磨削畸变;以及
类金刚石碳成膜工序,使成膜气体等离子化而在研磨后的完全分离的各个芯片的背面及全部侧面上成膜出类金刚石碳膜,该各个芯片是在该背面磨削工序或背面研磨工序中形成的。
2.根据权利要求1所述的晶片的加工方法,其中,
所述类金刚石碳膜的厚度为10~100nm。
3.一种电子器件,其中,
该电子器件以沿着多条分割预定线在晶片的内部形成的改质层作为分割的起点进行分割而成,并且分割而成的该电子器件的全部侧面不残留该改质层,
在该电子器件的背面及全部侧面上形成有类金刚石碳膜。
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